Fix ARM64 rewrites with NO_RWX_PAGES
Tested on nvidia jetson and Android, so far works great.
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@ -55,8 +55,8 @@
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// sub/add the pointer offset. CodeCache will point to the RW pointer for simplicity.
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#ifdef FEAT_NO_RWX_PAGES
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extern uintptr_t cc_rx_offset;
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#define CC_RW2RX(ptr) (void*)(((uintptr_t)ptr) + cc_rx_offset)
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#define CC_RX2RW(ptr) (void*)(((uintptr_t)ptr) - cc_rx_offset)
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#define CC_RW2RX(ptr) (void*)(((uintptr_t)(ptr)) + cc_rx_offset)
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#define CC_RX2RW(ptr) (void*)(((uintptr_t)(ptr)) - cc_rx_offset)
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#else
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#define CC_RW2RX(ptr) (ptr)
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#define CC_RX2RW(ptr) (ptr)
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@ -59,11 +59,7 @@ void fault_handler (int sn, siginfo_t * si, void *segfault_ctx)
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context_from_segfault(&ctx, segfault_ctx);
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bool dyna_cde = ((unat)ctx.pc>(unat)CodeCache) && ((unat)ctx.pc<(unat)(CodeCache + CODE_SIZE));
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//ucontext_t* ctx=(ucontext_t*)ctxr;
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//printf("mprot hit @ ptr 0x%08X @@ code: %08X, %d\n",si->si_addr,ctx->uc_mcontext.arm_pc,dyna_cde);
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bool dyna_cde = ((unat)CC_RX2RW(ctx.pc) > (unat)CodeCache) && ((unat)CC_RX2RW(ctx.pc) < (unat)(CodeCache + CODE_SIZE));
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if (VramLockedWrite((u8*)si->si_addr) || BM_LockedWrite((u8*)si->si_addr))
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return;
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@ -1442,13 +1442,14 @@ void ngen_CC_Finish(shil_opcode* op)
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bool ngen_Rewrite(unat& host_pc, unat, unat)
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{
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//printf("ngen_Rewrite pc %p\n", host_pc);
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void *host_pc_rw = CC_RX2RW(host_pc);
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RuntimeBlockInfo *block = bm_GetBlock((void*)host_pc);
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if (block == NULL)
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{
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printf("ngen_Rewrite: Block at %p not found\n", (void *)host_pc);
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return false;
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}
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u32 *code_ptr = (u32*)host_pc;
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u32 *code_ptr = (u32*)host_pc_rw;
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auto it = block->memory_accesses.find(code_ptr);
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if (it == block->memory_accesses.end())
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{
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@ -1466,7 +1467,7 @@ bool ngen_Rewrite(unat& host_pc, unat, unat)
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assembler->GenWriteMemorySlow(op);
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assembler->Finalize(true);
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delete assembler;
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host_pc = (unat)(code_ptr - 2);
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host_pc = (unat)CC_RW2RX(code_ptr - 2);
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return true;
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}
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