From 5c5c872afc7a488bd8861ae957a6a5134e42427e Mon Sep 17 00:00:00 2001 From: Flyinghead Date: Tue, 21 Mar 2023 11:32:21 +0100 Subject: [PATCH] aica: small dma transfer must be correctly scheduled Previously transfer taking less than 4096 cycles would be instantly executed. Fixes Sports Jam announcer broken audio. Issue #980 --- core/hw/aica/aica_if.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/core/hw/aica/aica_if.cpp b/core/hw/aica/aica_if.cpp index 1b90cbe1e..24c29f2bb 100644 --- a/core/hw/aica/aica_if.cpp +++ b/core/hw/aica/aica_if.cpp @@ -12,6 +12,7 @@ #include "hw/sh4/sh4_sched.h" #include "profiler/dc_profiler.h" #include "hw/sh4/dyna/blockmanager.h" +#include "hw/sh4/sh4_interpreter.h" #include "hw/arm7/arm7.h" #include "cfg/option.h" @@ -395,7 +396,7 @@ static void Write_SB_ADST(u32 addr, u32 data) // Schedule the end of DMA transfer interrupt int cycles = len * (SH4_MAIN_CLOCK / 2 / G2_BUS_CLOCK); // 16 bits @ 25 MHz - if (cycles < 4096) + if (cycles < SH4_TIMESLICE / 2) dma_end_sched(0, 0, 0); else sh4_sched_request(dma_sched_id, cycles);