From 5ab3d7b59bc987862c99219ed67fef58a0bf55b0 Mon Sep 17 00:00:00 2001
From: Jan Holthuis <jan.holthuis@ruhr-uni-bochum.de>
Date: Mon, 3 Aug 2015 16:58:15 +0200
Subject: [PATCH] core/hw/sh4/dyna/shil.cpp: Fix '&&' within '||' warning

Here's the original compiler warning:
../../core/hw/sh4/dyna/shil.cpp:700:24: warning: '&&' within '||'
      [-Wlogical-op-parentheses]
  ...if (op->rd.is_reg() && op->rd._reg==reg_sr_T ||  op->op==shop_ifb)
         ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~ ~~
../../core/hw/sh4/dyna/shil.cpp:700:24: note: place parentheses around the '&&'
      expression to silence this warning
  ...if (op->rd.is_reg() && op->rd._reg==reg_sr_T ||  op->op==shop_ifb)
                         ^
         (                                       )
../../core/hw/sh4/dyna/shil.cpp:843:25: warning: '&&' within '||'
      [-Wlogical-op-parentheses]
                        if (op->rs1.is_reg() && op->rs1._reg==reg_sr_T
                            ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
../../core/hw/sh4/dyna/shil.cpp:843:25: note: place parentheses around the '&&'
      expression to silence this warning
                        if (op->rs1.is_reg() && op->rs1._reg==reg_sr_T
                                             ^
                            (                                         )
../../core/hw/sh4/dyna/shil.cpp:844:25: warning: '&&' within '||'
      [-Wlogical-op-parentheses]
                                || op->rs2.is_reg() &&
op->rs2._reg==reg_sr_T
                                ~~ ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
../../core/hw/sh4/dyna/shil.cpp:844:25: note: place parentheses around the '&&'
      expression to silence this warning
                                || op->rs2.is_reg() && op->rs2._reg==reg_sr_T
                                                    ^
                                   (                                         )
../../core/hw/sh4/dyna/shil.cpp:845:25: warning: '&&' within '||'
      [-Wlogical-op-parentheses]
                                || op->rs3.is_reg() && op->rs3._reg==reg_sr_T
                                ~~ ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
../../core/hw/sh4/dyna/shil.cpp:845:25: note: place parentheses around the '&&'
      expression to silence this warning
                                || op->rs3.is_reg() && op->rs3._reg==reg_sr_T
                                                    ^
                                   (                                         )
---
 core/hw/sh4/dyna/shil.cpp | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/core/hw/sh4/dyna/shil.cpp b/core/hw/sh4/dyna/shil.cpp
index 54e3f0b5f..4591cd892 100644
--- a/core/hw/sh4/dyna/shil.cpp
+++ b/core/hw/sh4/dyna/shil.cpp
@@ -697,7 +697,7 @@ void dejcond(RuntimeBlockInfo* blk)
 
 		if (found)
 		{
-			if (op->rd.is_reg() && op->rd._reg==reg_sr_T ||  op->op==shop_ifb)
+			if ((op->rd.is_reg() && op->rd._reg==reg_sr_T) ||  op->op==shop_ifb)
 			{
 				found=false;
 			}
@@ -840,9 +840,9 @@ void srt_waw(RuntimeBlockInfo* blk)
 
 		if (found)
 		{
-			if (op->rs1.is_reg() && op->rs1._reg==reg_sr_T
-				|| op->rs2.is_reg() && op->rs2._reg==reg_sr_T
-				|| op->rs3.is_reg() && op->rs3._reg==reg_sr_T
+			if ((op->rs1.is_reg() && op->rs1._reg==reg_sr_T)
+				|| (op->rs2.is_reg() && op->rs2._reg==reg_sr_T)
+				|| (op->rs3.is_reg() && op->rs3._reg==reg_sr_T)
 				|| op->op==shop_ifb)
 			{
 				found=false;