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lr switch: enable aica arm and dsp dynarecs. handle rw/rx offset

This commit is contained in:
Flyinghead 2021-07-13 20:51:17 +02:00
parent 8c02345dfd
commit 4d38e69f63
5 changed files with 27 additions and 13 deletions
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3
core/build.h
View File

@ -183,9 +183,6 @@
#ifdef __SWITCH__
#define FEAT_NO_RWX_PAGES
// for now:
#define FEAT_AREC DYNAREC_NONE
#define FEAT_DSPREC DYNAREC_NONE
#endif
//defaults

12
core/hw/aica/dsp_arm64.cpp
View File

@ -29,6 +29,7 @@
using namespace vixl::aarch64;
static u8 *pCodeBuffer;
static ptrdiff_t rx_offset;
class DSPAssembler : public MacroAssembler
{
@ -364,7 +365,7 @@ private:
template <typename R, typename... P>
void GenCallRuntime(R (*function)(P...))
{
ptrdiff_t offset = reinterpret_cast<uintptr_t>(function) - GetBuffer()->GetStartAddress<uintptr_t>();
ptrdiff_t offset = reinterpret_cast<uintptr_t>(function) - GetBuffer()->GetStartAddress<uintptr_t>() - rx_offset;
verify(offset >= -128 * 1024 * 1024 && offset <= 128 * 1024 * 1024);
verify((offset & 3) == 0);
Label function_label;
@ -453,12 +454,15 @@ void dsp_recompile()
void dsp_rec_init()
{
if (!vmem_platform_prepare_jit_block(dsp.DynCode, sizeof(dsp.DynCode), (void**)&pCodeBuffer))
die("mprotect failed in arm64 dsp");
#ifdef FEAT_NO_RWX_PAGES
verify(vmem_platform_prepare_jit_block(dsp.DynCode, sizeof(dsp.DynCode), (void**)&pCodeBuffer, (uintptr_t *)&rx_offset));
#else
verify(vmem_platform_prepare_jit_block(dsp.DynCode, sizeof(dsp.DynCode), (void**)&pCodeBuffer));
#endif
}
void dsp_rec_step()
{
((void (*)())pCodeBuffer)();
((void (*)())(pCodeBuffer + rx_offset))();
}
#endif

9
core/hw/arm7/arm7_rec.cpp
View File

@ -59,6 +59,8 @@ alignas(4096) static u8 ARM7_TCB[ICacheSize] __attribute__((section("__TEXT, .te
#error ARM7_TCB ALLOC
#endif
ptrdiff_t rx_offset;
#pragma pack(push,1)
union ArmOpBits
{
@ -654,8 +656,11 @@ void flush()
void init()
{
if (!vmem_platform_prepare_jit_block(ARM7_TCB, ICacheSize, (void**)&ICache))
die("vmem_platform_prepare_jit_block failed");
#ifdef FEAT_NO_RWX_PAGES
verify(vmem_platform_prepare_jit_block(ARM7_TCB, ICacheSize, (void**)&ICache, (uintptr_t *)&rx_offset));
#else
verify(vmem_platform_prepare_jit_block(ARM7_TCB, ICacheSize, (void**)&ICache));
#endif
icPtr = ICache;

8
core/hw/arm7/arm7_rec.h
View File

@ -444,6 +444,14 @@ static inline void advance(u32 size) {
icPtr += size;
}
extern ptrdiff_t rx_offset;
static inline void *writeToExec(void * addr) {
return (char *)addr + rx_offset;
}
static inline void *execToWrite(void * addr) {
return (char *)addr - rx_offset;
}
}
void arm7backend_compile(const std::vector<ArmOp>& block_ops, u32 cycles);

8
core/hw/arm7/arm7_rec_arm64.cpp
View File

@ -30,7 +30,7 @@ using namespace vixl::aarch64;
namespace aicaarm {
static void (*arm_dispatch)();
static void (*arm_dispatch)(); // Not an executable address
class Arm7Compiler;
@ -106,7 +106,7 @@ class Arm7Compiler : public MacroAssembler
void call(void *loc)
{
ptrdiff_t offset = reinterpret_cast<uintptr_t>(loc) - GetBuffer()->GetStartAddress<uintptr_t>();
ptrdiff_t offset = reinterpret_cast<uintptr_t>(loc) - reinterpret_cast<uintptr_t>(recompiler::writeToExec(GetBuffer()->GetStartAddress<void *>()));
Label function_label;
BindToOffset(&function_label, offset);
Bl(&function_label);
@ -637,12 +637,12 @@ public:
Label arm_exit;
// arm_compilecode:
arm_compilecode = GetCursorAddress<void (*)()>();
arm_compilecode = (void (*)())recompiler::writeToExec(GetCursorAddress<void *>());
call((void*)recompiler::compile);
B(&arm_dispatch_label);
// arm_mainloop(regs, entry points)
arm_mainloop = GetCursorAddress<arm_mainloop_t>();
arm_mainloop = (arm_mainloop_t)recompiler::writeToExec(GetCursorAddress<void *>());
Stp(x25, x26, MemOperand(sp, -96, AddrMode::PreIndex));
Stp(x27, x28, MemOperand(sp, 16));
Stp(x29, x30, MemOperand(sp, 32));