diff --git a/core/build.h b/core/build.h index 1214440fd..9e2bd19df 100755 --- a/core/build.h +++ b/core/build.h @@ -121,14 +121,11 @@ #define USE_WINCE_HACK #endif -#define DC_PLATFORM_MASK 7 -#define DC_PLATFORM_DREAMCAST 0 /* Works, for the most part */ -#define DC_PLATFORM_DEV_UNIT 1 /* This is missing hardware */ -#define DC_PLATFORM_NAOMI 2 /* Works, for the most part */ -#define DC_PLATFORM_NAOMI2 3 /* Needs to be done, 2xsh4 + 2xpvr + custom TNL */ -#define DC_PLATFORM_ATOMISWAVE 4 /* Works, for the most part */ -#define DC_PLATFORM_HIKARU 5 /* Needs to be done, 2xsh4, 2x aica , custom vpu */ -#define DC_PLATFORM_AURORA 6 /* Needs to be done, Uses newer 300 mhz sh4 + 150 mhz pvr mbx SoC */ +#define DC_PLATFORM_DREAMCAST 0 +#define DC_PLATFORM_DEV_UNIT 1 +#define DC_PLATFORM_NAOMI 2 +#define DC_PLATFORM_NAOMI2 3 +#define DC_PLATFORM_ATOMISWAVE 4 //HOST_CPU #define CPU_X86 0x20000001 @@ -139,14 +136,12 @@ #define CPU_PPC 0x20000006 #define CPU_PPC64 0x20000007 #define CPU_ARM64 0x20000008 -#define CPU_MIPS64 0x20000009 //FEAT_SHREC, FEAT_AREC, FEAT_DSPREC #define DYNAREC_NONE 0x40000001 #define DYNAREC_JIT 0x40000002 #define DYNAREC_CPP 0x40000003 - //automatic #if defined(__x86_64__) || defined(_M_X64) @@ -235,15 +230,11 @@ #define VRAM_SIZE_MAX (16*1024*1024) #define ARAM_SIZE_MAX (8*1024*1024) -#define GD_CLOCK 33868800 //GDROM XTAL -- 768fs - -#define AICA_CORE_CLOCK (GD_CLOCK*4/3) //[45158400] GD->PLL 3:4 -> AICA CORE -- 1024fs -#define ADAC_CLOCK (AICA_CORE_CLOCK/4) //[11289600] 44100*256, AICA CORE -> PLL 4:1 -> ADAC -- 256fs -#define AICA_ARM_CLOCK (AICA_CORE_CLOCK/2) //[22579200] AICA CORE -> PLL 2:1 -> ARM -#define AICA_SDRAM_CLOCK (GD_CLOCK*2) //[67737600] GD-> PLL 2 -> SDRAM -#define SH4_MAIN_CLOCK (200*1000*1000) //[200000000] XTal(13.5) -> PLL (33.3) -> PLL 1:6 (200) -#define SH4_RAM_CLOCK (100*1000*1000) //[100000000] XTal(13.5) -> PLL (33.3) -> PLL 1:3 (100) , also suplied to HOLLY chip -#define G2_BUS_CLOCK (25*1000*1000) //[25000000] from Holly, from SH4_RAM_CLOCK w/ 2 2:1 plls +#define GD_CLOCK 33868800 //GDROM XTAL -- 768fs +#define AICA_CORE_CLOCK (GD_CLOCK * 4 / 3) //[45158400] GD->PLL 3:4 -> AICA CORE -- 1024fs +#define AICA_ARM_CLOCK (AICA_CORE_CLOCK / 2) //[22579200] AICA CORE -> PLL 2:1 -> ARM +#define SH4_MAIN_CLOCK (200 * 1000 * 1000) //[200000000] XTal(13.5) -> PLL (33.3) -> PLL 1:6 (200) +#define G2_BUS_CLOCK (25 * 1000 * 1000) //[25000000] from Holly, from SH4_RAM_CLOCK w/ 2 2:1 plls #if defined(GLES) && !defined(GLES3) && !defined(GLES2) // Only use GL ES 2.0 API functions diff --git a/core/emulator.cpp b/core/emulator.cpp index 0bf549bf6..11e134e03 100644 --- a/core/emulator.cpp +++ b/core/emulator.cpp @@ -394,7 +394,7 @@ static void setPlatform(int platform) case DC_PLATFORM_ATOMISWAVE: settings.platform.ram_size = 16 * 1024 * 1024; settings.platform.vram_size = 8 * 1024 * 1024; - settings.platform.aram_size = 8 * 1024 * 1024; + settings.platform.aram_size = 2 * 1024 * 1024; settings.platform.bios_size = 128 * 1024; settings.platform.flash_size = 128 * 1024; // sram break; diff --git a/core/hw/arm7/arm7.h b/core/hw/arm7/arm7.h index cced9e27d..e98d84a72 100644 --- a/core/hw/arm7/arm7.h +++ b/core/hw/arm7/arm7.h @@ -99,7 +99,7 @@ typedef union alignas(8) extern reg_pair arm_Reg[RN_ARM_REG_COUNT]; // AICA ARM cpu clock: 22.5792 MHz -#define ARM_CYCLES_PER_SAMPLE 512 +#define ARM_CYCLES_PER_SAMPLE (AICA_ARM_CLOCK / 44100) extern int arm7ClockTicks; void CPUFiq(); diff --git a/core/hw/holly/sb.cpp b/core/hw/holly/sb.cpp index 683967d01..5fb8f6151 100644 --- a/core/hw/holly/sb.cpp +++ b/core/hw/holly/sb.cpp @@ -264,8 +264,6 @@ void sb_write_reg(u32 addr, u32 data) SB_REGN_32(reg_addr) = (data & mask) | or_mask; } -u32 SB_FFST_rc; -u32 SB_FFST; static u32 read_SB_FFST(u32 addr) { return 0; diff --git a/core/serialize.cpp b/core/serialize.cpp index d8329c5c4..650e551fc 100644 --- a/core/serialize.cpp +++ b/core/serialize.cpp @@ -52,10 +52,6 @@ extern u32 SB_ADST; //./core/hw/aica/aica_mem.o extern u8 aica_reg[0x8000]; -//./core/hw/holly/sb.o -extern u32 SB_FFST_rc; -extern u32 SB_FFST; - //./core/hw/holly/sb_mem.o extern MemChip *sys_rom; extern WritableChip *sys_nvmem; @@ -190,8 +186,6 @@ void dc_serialize(Serializer& ser) register_serialize(sb_regs, ser); ser << SB_ISTNRM; ser << SB_ISTNRM1; - ser << SB_FFST_rc; - ser << SB_FFST; ser << SB_ADST; sys_rom->Serialize(ser); @@ -339,6 +333,8 @@ static void dc_deserialize_libretro(Deserializer& deser) } deser.deserialize(aica_ram.data, aica_ram.size); + if (settings.platform.isAtomiswave()) + deser.skip(6 * 1024 * 1024); deser >> VREG; deser >> ARMRST; deser >> rtc_EN; @@ -349,8 +345,8 @@ static void dc_deserialize_libretro(Deserializer& deser) register_deserialize(sb_regs, deser); deser >> SB_ISTNRM; - deser >> SB_FFST_rc; - deser >> SB_FFST; + deser.skip(); // SB_FFST_rc; + deser.skip(); // SB_FFST; SB_ADST = 0; deser.skip(); // sys_nvmem->size @@ -624,7 +620,11 @@ void dc_deserialize(Deserializer& deser) } if (!deser.rollback()) + { deser.deserialize(aica_ram.data, aica_ram.size); + if (settings.platform.isAtomiswave()) + deser.skip(6 * 1024 * 1024, Deserializer::V30); + } deser >> VREG; deser >> ARMRST; deser >> rtc_EN; @@ -641,8 +641,11 @@ void dc_deserialize(Deserializer& deser) deser >> SB_ISTNRM1; else SB_ISTNRM1 = 0; - deser >> SB_FFST_rc; - deser >> SB_FFST; + if (deser.version() < Deserializer::V30) + { + deser.skip(); // SB_FFST_rc; + deser.skip(); // SB_FFST; + } if (deser.version() >= Deserializer::V15) deser >> SB_ADST; else diff --git a/core/serialize.h b/core/serialize.h index 70421e2ac..fbed29f6a 100644 --- a/core/serialize.h +++ b/core/serialize.h @@ -65,7 +65,8 @@ public: V27, V28, V29, - Current = V29, + V30, + Current = V30, Next = Current + 1, };