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arm64: support for 64b immediate memory reads

This commit is contained in:
Flyinghead 2019-09-27 14:40:47 +02:00
parent ae4f378747
commit 419785b929
1 changed files with 59 additions and 31 deletions
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50
core/rec-ARM64/rec_arm64.cpp
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@ -1885,10 +1885,12 @@ private:
void* ptr = _vmem_write_const(addr, isram, size > 4 ? 4 : size);
Register reg2;
if (size != 8)
{
if (op.rs2.is_imm())
{
Mov(w0, op.rs2._imm);
reg2 = w0;
Mov(w1, op.rs2._imm);
reg2 = w1;
}
else if (regalloc.IsAllocg(op.rs2))
{
@ -1896,26 +1898,38 @@ private:
}
else if (regalloc.IsAllocf(op.rs2))
{
Fmov(w0, regalloc.MapVRegister(op.rs2));
reg2 = w0;
Fmov(w1, regalloc.MapVRegister(op.rs2));
reg2 = w1;
}
else
die("Invalid rs2 param");
}
if (isram)
{
Ldr(x1, reinterpret_cast<uintptr_t>(ptr));
Ldr(x0, reinterpret_cast<uintptr_t>(ptr));
switch (size)
{
case 1:
Strb(reg2, MemOperand(x1));
Strb(reg2, MemOperand(x0));
break;
case 2:
Strh(reg2, MemOperand(x1));
Strh(reg2, MemOperand(x0));
break;
case 4:
Str(reg2, MemOperand(x1));
Str(reg2, MemOperand(x0));
break;
case 8:
#ifdef EXPLODE_SPANS
verify(op.rs2.count() == 2 && regalloc.IsAllocf(op.rs2, 0) && regalloc.IsAllocf(op.rs2, 1));
Str(regalloc.MapVRegister(op.rs2, 0), MemOperand(x1));
Str(regalloc.MapVRegister(op.rs2, 1), MemOperand(x1, 4));
#else
shil_param_to_host_reg(op.rs2, x1);
Str(x1, MemOperand(x0));
#endif
break;
default:
@ -1926,8 +1940,21 @@ private:
else
{
// Not RAM
Mov(w1, reg2);
Mov(w0, addr);
if (size == 8)
{
// Need to call the handler twice
shil_param_to_host_reg(op.rs2, x1);
GenCallRuntime((void (*)())ptr);
Mov(w0, addr + 4);
shil_param_to_host_reg(op.rs2, x1);
Lsr(x1, x1, 32);
GenCallRuntime((void (*)())ptr);
}
else
{
Mov(w1, reg2);
switch(size)
{
@ -1943,11 +1970,12 @@ private:
GenCallRuntime((void (*)())ptr);
break;
case 8:
die("SZ_64F not supported");
default:
die("Invalid size");
break;
}
}
}
return true;
}