arm64: Use x28 as sh4 regs base pointer. Reg cache to avoid fetches.
Block check optimization
This commit is contained in:
Flyinghead
parent
67a4eb8f1f
commit
3d8b01c515
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@ -1,9 +1,11 @@
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#include <unistd.h>
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#include <sys/mman.h>
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#include "types.h"
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#if FEAT_SHREC == DYNAREC_JIT
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#include <unistd.h>
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#include <sys/mman.h>
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#include <map>
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#include "deps/vixl/aarch64/macro-assembler-aarch64.h"
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using namespace vixl::aarch64;
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@ -163,10 +165,11 @@ public:
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if (force_checks)
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CheckBlock(block);
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Stp(x29, x30, MemOperand(sp, -16, PreIndex));
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Mov(x29, sp);
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Stp(x28, x30, MemOperand(sp, -16, PreIndex));
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// Use x28 as sh4 context pointer
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Mov(x28, reinterpret_cast<uintptr_t>(&p_sh4rcb->cntx));
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Mov(x9, (size_t)&cycle_counter);
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Mov(x9, reinterpret_cast<uintptr_t>(&cycle_counter));
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Ldr(w10, MemOperand(x9));
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Sub(w10, w10, block->guest_cycles);
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Str(w10, MemOperand(x9));
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@ -179,28 +182,26 @@ public:
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case shop_ifb: // Interpreter fallback
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if (op.rs1._imm) // if NeedPC()
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{
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Mov(x9, (size_t)&next_pc);
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Mov(w10, op.rs2._imm);
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Str(w10, MemOperand(x9));
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Str(w10, sh4_context_mem_operand(&next_pc));
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}
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Mov(*call_regs[0], op.rs3._imm);
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CallRuntime(OpDesc[op.rs3._imm]->oph);
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reg_cache.clear();
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break;
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case shop_jcond:
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case shop_jdyn:
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Mov(x9, (size_t)op.rs1.reg_ptr());
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Ldr(w10, MemOperand(x9));
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Ldr(w10, sh4_context_mem_operand(op.rs1.reg_ptr()));
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if (op.rs2.is_imm()) {
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Mov(w9, op.rs2._imm);
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Add(w10, w10, w9);
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}
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Mov(x9, (size_t)op.rd.reg_ptr());
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Str(w10, MemOperand(x9));
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Str(w10, sh4_context_mem_operand(op.rd.reg_ptr()));
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reg_cache.clear();
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break;
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case shop_mov32:
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@ -215,8 +216,8 @@ public:
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verify(op.rd.is_reg());
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verify(op.rs1.is_reg() || op.rs1.is_imm());
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shil_param_to_host_reg(op.rs1, x10);
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host_reg_to_shil_param(op.rd, x10);
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shil_param_to_host_reg(op.rs1, x15);
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host_reg_to_shil_param(op.rd, x15);
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break;
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case shop_readm:
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@ -226,6 +227,7 @@ public:
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{
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shil_param_to_host_reg(op.rs3, w10);
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Add(*call_regs[0], *call_regs[0], w10);
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flush_reg_cache(*call_regs[0]);
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}
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u32 size = op.flags & 0x7f;
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@ -254,6 +256,7 @@ public:
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die("1..8 bytes");
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break;
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}
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reg_cache.clear();
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if (size != 8)
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host_reg_to_shil_param(op.rd, w0);
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@ -269,6 +272,7 @@ public:
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{
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shil_param_to_host_reg(op.rs3, w10);
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Add(*call_regs[0], *call_regs[0], w10);
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flush_reg_cache(*call_regs[0]);
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}
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u32 size = op.flags & 0x7f;
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@ -299,6 +303,7 @@ public:
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die("1..8 bytes");
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break;
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}
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reg_cache.clear();
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}
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break;
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@ -308,8 +313,6 @@ public:
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}
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}
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Mov(x9, (size_t)&next_pc);
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switch (block->BlockType)
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{
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@ -317,7 +320,7 @@ public:
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case BET_StaticCall:
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// next_pc = block->BranchBlock;
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Ldr(w10, block->BranchBlock);
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Str(w10, MemOperand(x9));
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Str(w10, sh4_context_mem_operand(&next_pc));
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break;
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case BET_Cond_0:
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@ -330,10 +333,9 @@ public:
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Mov(w10, block->NextBlock);
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if (block->has_jcond)
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Mov(x11, (size_t)&Sh4cntx.jdyn);
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Ldr(w11, sh4_context_mem_operand(&Sh4cntx.jdyn));
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else
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Mov(x11, (size_t)&sr.T);
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Ldr(w11, MemOperand(x11));
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Ldr(w11, sh4_context_mem_operand(&sr.T));
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Cmp(w11, block->BlockType & 1);
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Label branch_not_taken;
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@ -342,7 +344,7 @@ public:
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Mov(w10, block->BranchBlock);
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Bind(&branch_not_taken);
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Str(w10, MemOperand(x9));
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Str(w10, sh4_context_mem_operand(&next_pc));
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}
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break;
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@ -350,9 +352,8 @@ public:
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case BET_DynamicCall:
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case BET_DynamicRet:
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// next_pc = *jdyn;
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Mov(x10, (size_t)&Sh4cntx.jdyn);
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Ldr(w10, MemOperand(x10));
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Str(w10, MemOperand(x9));
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Ldr(w10, sh4_context_mem_operand(&Sh4cntx.jdyn));
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Str(w10, sh4_context_mem_operand(&next_pc));
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break;
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case BET_DynamicIntr:
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@ -360,15 +361,14 @@ public:
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if (block->BlockType == BET_DynamicIntr)
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{
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// next_pc = *jdyn;
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Mov(x10, (size_t)&Sh4cntx.jdyn);
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Ldr(w10, MemOperand(x10));
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Ldr(w10, sh4_context_mem_operand(&Sh4cntx.jdyn));
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}
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else
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{
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// next_pc = next_pc_value;
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Mov(w10, block->NextBlock);
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}
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Str(w10, MemOperand(x9));
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Str(w10, sh4_context_mem_operand(&next_pc));
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CallRuntime(UpdateINTC);
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break;
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@ -378,7 +378,7 @@ public:
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}
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Ldp(x29, x30, MemOperand(sp, 16, PostIndex));
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Ldp(x28, x30, MemOperand(sp, 16, PostIndex));
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Ret();
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Label code_end;
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@ -464,8 +464,7 @@ public:
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case CPT_f32:
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if (prm.is_reg()) {
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Mov(x9, (size_t)prm.reg_ptr());
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Ldr(*call_fregs[fregused], MemOperand(x9));
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Ldr(*call_fregs[fregused], sh4_context_mem_operand(prm.reg_ptr()));
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}
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else {
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verify(prm.is_null());
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@ -475,8 +474,9 @@ public:
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case CPT_ptr:
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verify(prm.is_reg());
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flush_reg_cache(*call_regs64[regused]);
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// push the ptr itself
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Mov(*call_regs64[regused++], (size_t)prm.reg_ptr());
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Mov(*call_regs64[regused++], reinterpret_cast<uintptr_t>(prm.reg_ptr()));
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break;
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case CPT_u32rv:
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@ -488,56 +488,52 @@ public:
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}
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}
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CallRuntime((void (*)())function);
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reg_cache.clear();
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}
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private:
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void CheckBlock(RuntimeBlockInfo* block)
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{
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s32 sz = block->sh4_code_size;
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u32 sa = block->addr;
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Label blockcheck_fail;
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Label blockcheck_success;
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u8* ptr = GetMemPtr(block->addr, sz);
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if (ptr == NULL)
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// FIXME Can a block cross a RAM / non-RAM boundary??
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return;
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Mov(x9, reinterpret_cast<uintptr_t>(ptr));
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while (sz > 0)
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{
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void* ptr = GetMemPtr(sa, sz > 8 ? 8 : sz);
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if (ptr != NULL)
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{
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Mov(x9, (size_t)reinterpret_cast<uintptr_t>(ptr));
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if (sz >= 8)
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{
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Ldr(x10, MemOperand(x9));
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Mov(x11, *(u64*)ptr);
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Ldr(x10, MemOperand(x9, 8, PostIndex));
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Ldr(x11, *(u64*)ptr);
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Cmp(x10, x11);
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sz -= 8;
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sa += 8;
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ptr += 8;
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}
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else if (sz >= 4)
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{
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Ldr(w10, MemOperand(x9));
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Mov(w11, *(u32*)ptr);
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Ldr(w10, MemOperand(x9, 4, PostIndex));
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Ldr(w11, *(u32*)ptr);
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Cmp(w10, w11);
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sz -= 4;
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sa += 4;
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ptr += 4;
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}
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else
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{
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Ldrh(w10, MemOperand(x9));
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Ldrh(w10, MemOperand(x9, 2, PostIndex));
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Mov(w11, *(u16*)ptr);
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Cmp(w10, w11);
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sz -= 2;
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sa += 2;
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ptr += 2;
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}
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B(ne, &blockcheck_fail);
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}
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else
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{
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sz -= 4;
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sa += 4;
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}
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}
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B(&blockcheck_success);
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Bind(&blockcheck_fail);
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@ -547,14 +543,34 @@ private:
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Bind(&blockcheck_success);
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}
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MemOperand sh4_context_mem_operand(void *p)
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{
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u32 offset = (u8*)p - (u8*)&p_sh4rcb->cntx;
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verify((offset & 3) == 0 && offset <= 16380); // FIXME 64-bit regs need multiple of 8 up to 32760
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return MemOperand(x28, offset);
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}
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void shil_param_to_host_reg(const shil_param& param, const Register& reg)
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{
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if (param.is_imm()) {
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Mov(reg, param._imm);
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flush_reg_cache(reg);
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}
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else if (param.is_reg()) {
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Mov(x9, (size_t)param.reg_ptr());
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Ldr(reg, MemOperand(x9));
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const Register *cached_reg = reg_cache[param._reg];
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if (cached_reg != NULL)
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{
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if (cached_reg != ®)
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{
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Mov(reg, *cached_reg);
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set_reg_cache(param._reg, reg);
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}
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}
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else
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{
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Ldr(reg, sh4_context_mem_operand(param.reg_ptr()));
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set_reg_cache(param._reg, reg);
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}
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}
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else {
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verify(param.is_null());
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@ -563,8 +579,24 @@ private:
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void host_reg_to_shil_param(const shil_param& param, const CPURegister& reg)
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{
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Mov(x9, (size_t)param.reg_ptr());
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Str(reg, MemOperand(x9));
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Str(reg, sh4_context_mem_operand(param.reg_ptr()));
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if (reg.IsRegister())
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set_reg_cache(param._reg, (const Register&)reg);
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}
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void set_reg_cache(Sh4RegType sh4_reg_type, const Register& reg)
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{
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flush_reg_cache(reg);
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reg_cache[sh4_reg_type] = ®
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}
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void flush_reg_cache(const Register& reg)
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{
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for (auto it = reg_cache.begin(); it != reg_cache.end();)
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if (it->second != NULL && it->second->GetCode() == reg.GetCode())
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it = reg_cache.erase(it);
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else
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it++;
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}
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struct CC_PS
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@ -576,7 +608,7 @@ private:
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std::vector<const WRegister*> call_regs;
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std::vector<const XRegister*> call_regs64;
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std::vector<const VRegister*> call_fregs;
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std::map<Sh4RegType, const Register*> reg_cache;
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};
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static Arm64Assembler* compiler;
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