From 35cd1fcf144c585a09b6b9cf08b81b9f41f218cc Mon Sep 17 00:00:00 2001 From: Flyinghead Date: Mon, 1 Jul 2019 15:22:04 +0200 Subject: [PATCH] sh4: use new logging --- core/hw/sh4/interpr/sh4_fpu.cpp | 6 +- core/hw/sh4/interpr/sh4_interpreter.cpp | 12 ++-- core/hw/sh4/interpr/sh4_opcodes.cpp | 79 ++++++++++----------- core/hw/sh4/modules/bsc.cpp | 3 + core/hw/sh4/modules/ccn.cpp | 10 ++- core/hw/sh4/modules/dmac.cpp | 8 +-- core/hw/sh4/modules/fastmmu.cpp | 6 +- core/hw/sh4/modules/mmu.cpp | 50 +++++++------- core/hw/sh4/modules/tmu.cpp | 10 +-- core/hw/sh4/modules/wince.h | 28 ++++---- core/hw/sh4/sh4_core.h | 8 +-- core/hw/sh4/sh4_core_regs.cpp | 4 +- core/hw/sh4/sh4_mmr.cpp | 91 ++++++++++++------------- core/hw/sh4/sh4_opcode_list.cpp | 2 +- core/log/Log.h | 1 + core/log/LogManager.cpp | 1 + 16 files changed, 157 insertions(+), 162 deletions(-) diff --git a/core/hw/sh4/interpr/sh4_fpu.cpp b/core/hw/sh4/interpr/sh4_fpu.cpp index 71d6abd2c..859c87512 100644 --- a/core/hw/sh4/interpr/sh4_fpu.cpp +++ b/core/hw/sh4/interpr/sh4_fpu.cpp @@ -61,12 +61,12 @@ INLINE void Denorm32(float &value) if ((*v<=0x007FFFFF) && *v>0) { *v=0; - printf("Fixed +denorm\n"); + INFO_LOG(INTERPRETER, "Fixed +denorm"); } else if ((*v<=0x807FFFFF) && *v>0x80000000) { *v=0x80000000; - printf("Fixed -denorm\n"); + INFO_LOG(INTERPRETER, "Fixed -denorm"); } } } @@ -733,6 +733,6 @@ sh4op(i1111_nn01_1111_1101) void iNimp(const char*str) { - printf("Unimplemented sh4 FPU instruction: %s\n", str); + WARN_LOG(INTERPRETER, "Unimplemented sh4 FPU instruction: %s", str); //Sh4_int_Stop(); } diff --git a/core/hw/sh4/interpr/sh4_interpreter.cpp b/core/hw/sh4/interpr/sh4_interpreter.cpp index a2074443d..3a1c9e3c2 100644 --- a/core/hw/sh4/interpr/sh4_interpreter.cpp +++ b/core/hw/sh4/interpr/sh4_interpreter.cpp @@ -102,7 +102,7 @@ void Sh4_int_Step() { if (sh4_int_bCpuRun) { - printf("Sh4 Is running , can't step\n"); + WARN_LOG(INTERPRETER, "Sh4 Is running , can't step"); } else { @@ -116,7 +116,7 @@ void Sh4_int_Skip() { if (sh4_int_bCpuRun) { - printf("Sh4 Is running, can't Skip\n"); + WARN_LOG(INTERPRETER, "Sh4 Is running, can't Skip"); } else { @@ -128,7 +128,7 @@ void Sh4_int_Reset(bool Manual) { if (sh4_int_bCpuRun) { - printf("Sh4 Is running, can't Reset\n"); + WARN_LOG(INTERPRETER, "Sh4 Is running, can't Reset"); } else { @@ -149,7 +149,7 @@ void Sh4_int_Reset(bool Manual) UpdateFPSCR(); //Any more registers have default value ? - printf("Sh4 Reset\n"); + INFO_LOG(INTERPRETER, "Sh4 Reset"); } } @@ -189,7 +189,7 @@ void ExecuteDelayslot_RTE() #if !defined(NO_MMU) } catch (SH4ThrownException& ex) { - msgboxf("Exception in RTE delay slot", MBX_ICONERROR); + ERROR_LOG(INTERPRETER, "Exception in RTE delay slot"); } #endif } @@ -300,7 +300,7 @@ void Sh4_int_Init() void Sh4_int_Term() { Sh4_int_Stop(); - printf("Sh4 Term\n"); + INFO_LOG(INTERPRETER, "Sh4 Term"); } /* diff --git a/core/hw/sh4/interpr/sh4_opcodes.cpp b/core/hw/sh4/interpr/sh4_opcodes.cpp index 7330db791..9ede446f2 100644 --- a/core/hw/sh4/interpr/sh4_opcodes.cpp +++ b/core/hw/sh4/interpr/sh4_opcodes.cpp @@ -61,7 +61,7 @@ void dofoo(sh4_opcode op) // 0xxx void cpu_iNimp(u32 op, const char* info) { - printf("\n\nUnimplemented opcode: %08X next_pc: %08X pr: %08X msg: %s\n", op, next_pc, pr, info); + ERROR_LOG(INTERPRETER, "Unimplemented opcode: %08X next_pc: %08X pr: %08X msg: %s", op, next_pc, pr, info); //next_pc = pr; //debug hackfix: try to recover by returning from call die("iNimp reached\n"); //sh4_cpu.Stop(); @@ -69,9 +69,7 @@ void cpu_iNimp(u32 op, const char* info) void cpu_iWarn(u32 op, const char* info) { - printf("Check opcode : %X : ", op); - printf("%s", info); - printf(" @ %X\n", curr_pc); + INFO_LOG(INTERPRETER, "Check opcode : %X : %s @ %X", op, info, curr_pc); } //this file contains ALL register to register full moves @@ -1586,7 +1584,7 @@ sh4op(i0011_nnnn_mmmm_0100) u32 n=GetN(op); u32 m=GetM(op); - unsigned long tmp0, tmp2; + u32 tmp0, tmp2; unsigned char old_q, tmp1; old_q = sr.Q; @@ -1596,39 +1594,44 @@ sh4op(i0011_nnnn_mmmm_0100) r[n] |= (unsigned long)sr.T; tmp0 = r[n]; // this need only be done once here .. - tmp2 = r[m]; + // Old implementation +// tmp2 = r[m]; +// +// if( 0 == old_q ) +// { +// if( 0 == sr.M ) +// { +// r[n] -= tmp2; +// tmp1 = (r[n]>tmp0); +// sr.Q = (sr.Q==0) ? tmp1 : (u8)(tmp1==0) ; +// } +// else +// { +// r[n] += tmp2; +// tmp1 =(r[n]tmp0); +// sr.Q = (sr.Q==0) ? (u8)(tmp1==0) : tmp1 ; +// } +// } - if( 0 == old_q ) - { - if( 0 == sr.M ) - { - r[n] -= tmp2; - tmp1 = (r[n]>tmp0); - sr.Q = (sr.Q==0) ? tmp1 : (u8)(tmp1==0) ; - } - else - { - r[n] += tmp2; - tmp1 =(r[n]tmp0); - sr.Q = (sr.Q==0) ? (u8)(tmp1==0) : tmp1 ; - } - } - sr.T = (sr.Q==sr.M); + r[n] += (2 * (old_q ^ sr.M) - 1) * r[m]; + sr.Q ^= old_q ^ (sr.M ? r[n] > tmp0 : r[n] >= tmp0); + + sr.T = (sr.Q == sr.M); } //************************ Simple maths ************************ @@ -2136,7 +2139,7 @@ sh4op(i0100_nnnn_0000_1110) sh4op(iNotImplemented) { #ifndef NO_MMU - printf("iNimp %04X\n", op); + INFO_LOG(INTERPRETER, "iNimp %04X", op); SH4ThrownException ex = { next_pc - 2, 0x180, 0x100 }; throw ex; #else diff --git a/core/hw/sh4/modules/bsc.cpp b/core/hw/sh4/modules/bsc.cpp index a0a5889f3..c939c4e5e 100644 --- a/core/hw/sh4/modules/bsc.cpp +++ b/core/hw/sh4/modules/bsc.cpp @@ -160,6 +160,9 @@ void bsc_reset() BSC_PCTRB.full=0x0; //BSC_PDTRB.full; undef BSC_GPIOIC.full=0x0; +#if DC_PLATFORM == DC_PLATFORM_NAOMI || DC_PLATFORM == DC_PLATFORM_ATOMISWAVE + BSC_RFCR.full = 17; +#endif } void bsc_term() { diff --git a/core/hw/sh4/modules/ccn.cpp b/core/hw/sh4/modules/ccn.cpp index 459771393..a455e97c1 100644 --- a/core/hw/sh4/modules/ccn.cpp +++ b/core/hw/sh4/modules/ccn.cpp @@ -13,9 +13,6 @@ //Types -#define printf_smc(...) // printf - - u32 CCN_QACR_TR[2]; template @@ -86,15 +83,16 @@ void CCN_CCR_write(u32 addr, u32 value) if (temp.ICI) { - printf_smc("Sh4: i-cache invalidation %08X\n",curr_pc); + DEBUG_LOG(SH4, "Sh4: i-cache invalidation %08X", curr_pc); if (settings.dynarec.SmcCheckLevel == NoCheck) { //TODO: Add skip/check vectors for Shikigami No Shiro II (uses ICI frequently) //which game is 0xAC13DBF8 from ? if (curr_pc != 0xAC13DBF8) { - printf("Sh4: code cache clear (ICI) pc: %08X\n",curr_pc); - sh4_cpu.ResetCache(); + // Disabled as it causes instant crash by invalidating the block the dynarec is currently running + //DEBUG_LOG(DYNAREC, "Sh4: code cache clear (ICI) pc: %08X", curr_pc); + //sh4_cpu.ResetCache(); } } } diff --git a/core/hw/sh4/modules/dmac.cpp b/core/hw/sh4/modules/dmac.cpp index 887aeb4df..57fd87242 100644 --- a/core/hw/sh4/modules/dmac.cpp +++ b/core/hw/sh4/modules/dmac.cpp @@ -36,17 +36,17 @@ void DMAC_Ch2St() if(0x8201 != (dmaor &DMAOR_MASK)) { - printf("\n!\tDMAC: DMAOR has invalid settings (%X) !\n", dmaor); + INFO_LOG(SH4, "DMAC: DMAOR has invalid settings (%X) !", dmaor); return; } if (len & 0x1F) { - printf("\n!\tDMAC: SB_C2DLEN has invalid size (%X) !\n", len); + INFO_LOG(SH4, "DMAC: SB_C2DLEN has invalid size (%X) !", len); return; } - //printf(">>\tDMAC: Ch2 DMA SRC=%X DST=%X LEN=%X\n", src, dst, len ); + DEBUG_LOG(SH4, ">> DMAC: Ch2 DMA SRC=%X DST=%X LEN=%X", src, dst, len); // Direct DList DMA (Ch2) @@ -127,7 +127,7 @@ void DMAC_Ch2St() } else { - printf("\n!\tDMAC: SB_C2DSTAT has invalid address (%X) !\n", dst); + INFO_LOG(SH4, "DMAC: SB_C2DSTAT has invalid address (%X) !", dst); src+=len; } diff --git a/core/hw/sh4/modules/fastmmu.cpp b/core/hw/sh4/modules/fastmmu.cpp index 798d1cd50..c1d685b4e 100644 --- a/core/hw/sh4/modules/fastmmu.cpp +++ b/core/hw/sh4/modules/fastmmu.cpp @@ -39,10 +39,6 @@ extern u32 sq_remap[64]; #include "wince.h" -#define printf_mmu(...) -//#define printf_mmu printf -#define printf_win32(...) - extern const u32 mmu_mask[4]; const TLB_Entry *lru_entry = NULL; @@ -327,7 +323,7 @@ u32 mmu_data_translation(u32 va, u32& rv) if (va == unresolved_unicode_string) { unresolved_unicode_string = 0; - printf("RESOLVED %s\n", get_unicode_string(va).c_str()); + INFO_LOG(SH4, "RESOLVED %s", get_unicode_string(va).c_str()); } } #endif diff --git a/core/hw/sh4/modules/mmu.cpp b/core/hw/sh4/modules/mmu.cpp index 83981dde3..d3aae1f62 100644 --- a/core/hw/sh4/modules/mmu.cpp +++ b/core/hw/sh4/modules/mmu.cpp @@ -21,11 +21,11 @@ bool UTLB_Sync(u32 entry) { u32 vpn_sq = ((UTLB[entry].Address.VPN & 0x7FFFF) >> 10) & 0x3F;//upper bits are always known [0xE0/E1/E2/E3] sq_remap[vpn_sq] = UTLB[entry].Data.PPN << 10; - printf("SQ remap %d : 0x%X to 0x%X\n", entry, UTLB[entry].Address.VPN << 10, UTLB[entry].Data.PPN << 10); + INFO_LOG(SH4, "SQ remap %d : 0x%X to 0x%X", entry, UTLB[entry].Address.VPN << 10, UTLB[entry].Data.PPN << 10); } else { - printf("MEM remap %d : 0x%X to 0x%X\n", entry, UTLB[entry].Address.VPN << 10, UTLB[entry].Data.PPN << 10); + INFO_LOG(SH4, "MEM remap %d : 0x%X to 0x%X", entry, UTLB[entry].Address.VPN << 10, UTLB[entry].Data.PPN << 10); } return true; @@ -33,7 +33,7 @@ bool UTLB_Sync(u32 entry) //Sync memory mapping to MMU, suspend compiled blocks if needed.entry is a ITLB entry # , -1 is for full sync void ITLB_Sync(u32 entry) { - printf("ITLB MEM remap %d : 0x%X to 0x%X\n",entry,ITLB[entry].Address.VPN<<10,ITLB[entry].Data.PPN<<10); + INFO_LOG(SH4, "ITLB MEM remap %d : 0x%X to 0x%X",entry,ITLB[entry].Address.VPN<<10,ITLB[entry].Data.PPN<<10); } void mmu_set_state() @@ -83,8 +83,7 @@ u32 mmu_full_lookup(u32 va, u32& idx, u32& rv); #include "wince.h" #endif -#define printf_mmu(...) -#define printf_win32(...) +#define printf_mmu(...) DEBUG_LOG(SH4, __VA_ARGS__) ReadMem8Func ReadMem8; ReadMem16Func ReadMem16; @@ -134,7 +133,7 @@ u32 ITLB_LRU_USE[64]; //sync mem mapping to mmu , suspend compiled blocks if needed.entry is a UTLB entry # , -1 is for full sync bool UTLB_Sync(u32 entry) { - printf_mmu("UTLB MEM remap %d : 0x%X to 0x%X : %d asid %d size %d\n", entry, UTLB[entry].Address.VPN << 10, UTLB[entry].Data.PPN << 10, UTLB[entry].Data.V, + printf_mmu("UTLB MEM remap %d : 0x%X to 0x%X : %d asid %d size %d", entry, UTLB[entry].Address.VPN << 10, UTLB[entry].Data.PPN << 10, UTLB[entry].Data.V, UTLB[entry].Address.ASID, UTLB[entry].Data.SZ0 + UTLB[entry].Data.SZ1 * 2); if (UTLB[entry].Data.V == 0) return true; @@ -155,7 +154,7 @@ bool UTLB_Sync(u32 entry) //sync mem mapping to mmu , suspend compiled blocks if needed.entry is a ITLB entry # , -1 is for full sync void ITLB_Sync(u32 entry) { - printf_mmu("ITLB MEM remap %d : 0x%X to 0x%X : %d\n", entry, ITLB[entry].Address.VPN << 10, ITLB[entry].Data.PPN << 10, ITLB[entry].Data.V); + printf_mmu("ITLB MEM remap %d : 0x%X to 0x%X : %d", entry, ITLB[entry].Address.VPN << 10, ITLB[entry].Data.PPN << 10, ITLB[entry].Data.V); } #endif @@ -178,13 +177,12 @@ void mmu_raise_exception(u32 mmu_error, u32 address, u32 am) { //No error case MMU_ERROR_NONE: - printf("Error : mmu_raise_exception(MMU_ERROR_NONE)\n"); - getc(stdin); + die("Error : mmu_raise_exception(MMU_ERROR_NONE)"); break; //TLB miss case MMU_ERROR_TLB_MISS: - printf_mmu("MMU_ERROR_UTLB_MISS 0x%X, handled\n", address); + printf_mmu("MMU_ERROR_UTLB_MISS 0x%X, handled", address); if (am == MMU_TT_DWRITE) //WTLBMISS - Write Data TLB Miss Exception RaiseException(0x60, 0x400); else if (am == MMU_TT_DREAD) //RTLBMISS - Read Data TLB Miss Exception @@ -197,12 +195,12 @@ void mmu_raise_exception(u32 mmu_error, u32 address, u32 am) //TLB Multihit case MMU_ERROR_TLB_MHIT: - printf("MMU_ERROR_TLB_MHIT @ 0x%X\n", address); + INFO_LOG(SH4, "MMU_ERROR_TLB_MHIT @ 0x%X", address); break; //Mem is read/write protected (depends on translation type) case MMU_ERROR_PROTECTED: - printf_mmu("MMU_ERROR_PROTECTED 0x%X, handled\n", address); + printf_mmu("MMU_ERROR_PROTECTED 0x%X, handled", address); if (am == MMU_TT_DWRITE) //WRITEPROT - Write Data TLB Protection Violation Exception RaiseException(0xC0, 0x100); else if (am == MMU_TT_DREAD) //READPROT - Data TLB Protection Violation Exception @@ -216,7 +214,7 @@ void mmu_raise_exception(u32 mmu_error, u32 address, u32 am) //Mem is write protected , firstwrite case MMU_ERROR_FIRSTWRITE: - printf_mmu("MMU_ERROR_FIRSTWRITE\n"); + printf_mmu("MMU_ERROR_FIRSTWRITE"); verify(am == MMU_TT_DWRITE); //FIRSTWRITE - Initial Page Write Exception RaiseException(0x80, 0x100); @@ -235,17 +233,17 @@ void mmu_raise_exception(u32 mmu_error, u32 address, u32 am) #ifdef TRACE_WINCE_SYSCALLS if (!print_wince_syscall(address)) #endif - printf_mmu("MMU_ERROR_BADADDR(i) 0x%X\n", address); + printf_mmu("MMU_ERROR_BADADDR(i) 0x%X", address); RaiseException(0xE0, 0x100); return; } - printf_mmu("MMU_ERROR_BADADDR(d) 0x%X, handled\n", address); + printf_mmu("MMU_ERROR_BADADDR(d) 0x%X, handled", address); return; break; //Can't Execute case MMU_ERROR_EXECPROT: - printf("MMU_ERROR_EXECPROT 0x%X\n", address); + INFO_LOG(SH4, "MMU_ERROR_EXECPROT 0x%X", address); //EXECPROT - Instruction TLB Protection Violation Exception RaiseException(0xA0, 0x100); @@ -267,12 +265,12 @@ void DoMMUException(u32 address, u32 mmu_error, u32 access_type) { //No error case MMU_ERROR_NONE: - printf("Error : mmu_raise_exception(MMU_ERROR_NONE)\n"); + die("Error : mmu_raise_exception(MMU_ERROR_NONE)"); break; //TLB miss case MMU_ERROR_TLB_MISS: - printf_mmu("MMU_ERROR_UTLB_MISS 0x%X, handled\n", address); + printf_mmu("MMU_ERROR_UTLB_MISS 0x%X, handled", address); if (access_type == MMU_TT_DWRITE) //WTLBMISS - Write Data TLB Miss Exception Do_Exception(next_pc, 0x60, 0x400); else if (access_type == MMU_TT_DREAD) //RTLBMISS - Read Data TLB Miss Exception @@ -285,12 +283,12 @@ void DoMMUException(u32 address, u32 mmu_error, u32 access_type) //TLB Multihit case MMU_ERROR_TLB_MHIT: - printf("MMU_ERROR_TLB_MHIT @ 0x%X\n", address); + INFO_LOG(SH4, "MMU_ERROR_TLB_MHIT @ 0x%X", address); break; //Mem is read/write protected (depends on translation type) case MMU_ERROR_PROTECTED: - printf_mmu("MMU_ERROR_PROTECTED 0x%X, handled\n", address); + printf_mmu("MMU_ERROR_PROTECTED 0x%X, handled", address); if (access_type == MMU_TT_DWRITE) //WRITEPROT - Write Data TLB Protection Violation Exception Do_Exception(next_pc, 0xC0, 0x100); else if (access_type == MMU_TT_DREAD) //READPROT - Data TLB Protection Violation Exception @@ -304,7 +302,7 @@ void DoMMUException(u32 address, u32 mmu_error, u32 access_type) //Mem is write protected , firstwrite case MMU_ERROR_FIRSTWRITE: - printf_mmu("MMU_ERROR_FIRSTWRITE\n"); + printf_mmu("MMU_ERROR_FIRSTWRITE"); verify(access_type == MMU_TT_DWRITE); //FIRSTWRITE - Initial Page Write Exception Do_Exception(next_pc, 0x80, 0x100); @@ -323,17 +321,17 @@ void DoMMUException(u32 address, u32 mmu_error, u32 access_type) #ifdef TRACE_WINCE_SYSCALLS if (!print_wince_syscall(address)) #endif - printf_mmu("MMU_ERROR_BADADDR(i) 0x%X\n", address); + printf_mmu("MMU_ERROR_BADADDR(i) 0x%X", address); Do_Exception(next_pc, 0xE0, 0x100); return; } - printf_mmu("MMU_ERROR_BADADDR(d) 0x%X, handled\n", address); + printf_mmu("MMU_ERROR_BADADDR(d) 0x%X, handled", address); return; break; //Can't Execute case MMU_ERROR_EXECPROT: - printf("MMU_ERROR_EXECPROT 0x%X\n", address); + INFO_LOG(SH4, "MMU_ERROR_EXECPROT 0x%X", address); //EXECPROT - Instruction TLB Protection Violation Exception Do_Exception(next_pc, 0xA0, 0x100); @@ -526,7 +524,7 @@ u32 mmu_data_translation(u32 va, u32& rv) if (va == unresolved_unicode_string) { unresolved_unicode_string = 0; - printf("RESOLVED %s\n", get_unicode_string(va).c_str()); + INFO_LOG(SH4, "RESOLVED %s", get_unicode_string(va).c_str()); } } #endif @@ -651,7 +649,7 @@ void mmu_set_state() { if (CCN_MMUCR.AT == 1 && settings.dreamcast.FullMMU) { - printf("Enabling Full MMU support\n"); + NOTICE_LOG(SH4, "Enabling Full MMU support"); IReadMem16 = &mmu_IReadMem16; ReadMem8 = &mmu_ReadMem; ReadMem16 = &mmu_ReadMem; diff --git a/core/hw/sh4/modules/tmu.cpp b/core/hw/sh4/modules/tmu.cpp index 90be18616..b37951c53 100644 --- a/core/hw/sh4/modules/tmu.cpp +++ b/core/hw/sh4/modules/tmu.cpp @@ -176,15 +176,15 @@ void UpdateTMUCounts(u32 reg) break; case 5: //reserved - printf("TMU ch%d - TCR%d mode is reserved (5)",reg,reg); + INFO_LOG(SH4, "TMU ch%d - TCR%d mode is reserved (5)",reg,reg); break; case 6: //RTC - printf("TMU ch%d - TCR%d mode is RTC (6), can't be used on Dreamcast",reg,reg); + INFO_LOG(SH4, "TMU ch%d - TCR%d mode is RTC (6), can't be used on Dreamcast",reg,reg); break; case 7: //external - printf("TMU ch%d - TCR%d mode is External (7), can't be used on Dreamcast",reg,reg); + INFO_LOG(SH4, "TMU ch%d - TCR%d mode is External (7), can't be used on Dreamcast",reg,reg); break; } tmu_shift[reg]+=2; @@ -203,13 +203,13 @@ void TMU_TCR_write(u32 addr, u32 data) //Chan 2 not used functions u32 TMU_TCPR2_read(u32 addr) { - EMUERROR("Read from TMU_TCPR2 - this register should be not used on Dreamcast according to docs"); + INFO_LOG(SH4, "Read from TMU_TCPR2 - this register should be not used on Dreamcast according to docs"); return 0; } void TMU_TCPR2_write(u32 addr, u32 data) { - EMUERROR2("Write to TMU_TCPR2 - this register should be not used on Dreamcast according to docs, data=%d",data); + INFO_LOG(SH4, "Write to TMU_TCPR2 - this register should be not used on Dreamcast according to docs, data=%d", data); } void write_TMU_TSTR(u32 addr, u32 data) diff --git a/core/hw/sh4/modules/wince.h b/core/hw/sh4/modules/wince.h index eb724c64c..d967df55b 100644 --- a/core/hw/sh4/modules/wince.h +++ b/core/hw/sh4/modules/wince.h @@ -312,33 +312,31 @@ static bool print_wince_syscall(u32 address) sprintf(method_buf, "[%d]", meth_id); method = method_buf; } - printf("WinCE %08x %04x.%04x %s: %s", address, getCurrentProcessId() & 0xffff, getCurrentThreadId() & 0xffff, api, method); + INFO_LOG(SH4, "WinCE %08x %04x.%04x %s: %s", address, getCurrentProcessId() & 0xffff, getCurrentThreadId() & 0xffff, api, method); if (address == 0xfffffd51) // SetLastError - printf(" dwErrCode = %x\n", r[4]); + INFO_LOG(SH4, " dwErrCode = %x", r[4]); else if (address == 0xffffd5ef) // CreateFile - printf(" lpFileName = %s\n", get_unicode_string(r[4]).c_str()); + INFO_LOG(SH4, " lpFileName = %s", get_unicode_string(r[4]).c_str()); else if (address == 0xfffffd97) // CreateProc - printf(" imageName = %s, commandLine = %s\n", get_unicode_string(r[4]).c_str(), get_unicode_string(r[5]).c_str()); + INFO_LOG(SH4, " imageName = %s, commandLine = %s", get_unicode_string(r[4]).c_str(), get_unicode_string(r[5]).c_str()); else if (!strcmp("DebugNotify", method)) - printf(" %x, %x\n", r[4], r[5]); + INFO_LOG(SH4, " %x, %x\n", r[4], r[5]); else if (address == 0xffffd5d3) // RegOpenKeyExW - printf(" hKey = %x, lpSubKey = %s\n", r[4], get_unicode_string(r[5]).c_str()); + INFO_LOG(SH4, " hKey = %x, lpSubKey = %s", r[4], get_unicode_string(r[5]).c_str()); else if (!strcmp("LoadLibraryW", method)) - printf(" fileName = %s\n", get_unicode_string(r[4]).c_str()); + INFO_LOG(SH4, " fileName = %s", get_unicode_string(r[4]).c_str()); else if (!strcmp("GetProcAddressW", method)) - printf(" hModule = %x, procName = %s\n", r[4], get_unicode_string(r[5]).c_str()); + INFO_LOG(SH4, " hModule = %x, procName = %s", r[4], get_unicode_string(r[5]).c_str()); else if (!strcmp("NKvDbgPrintfW", method)) - printf(" fmt = %s\n", get_unicode_string(r[4]).c_str()); + INFO_LOG(SH4, " fmt = %s", get_unicode_string(r[4]).c_str()); else if (!strcmp("OutputDebugStringW", method)) - printf(" str = %s\n", get_unicode_string(r[4]).c_str()); + INFO_LOG(SH4, " str = %s", get_unicode_string(r[4]).c_str()); else if (!strcmp("RegisterAFSName", method)) - printf(" name = %s\n", get_unicode_string(r[4]).c_str()); + INFO_LOG(SH4, " name = %s", get_unicode_string(r[4]).c_str()); else if (!strcmp("CreateAPISet", method)) - printf(" name = %s\n", get_ascii_string(r[4]).c_str()); + INFO_LOG(SH4, " name = %s", get_ascii_string(r[4]).c_str()); else if (!strcmp("Register", method) && !strcmp("APISET", api)) - printf(" p = %x, id = %x\n", r[4], r[5]); - else - printf("\n"); + INFO_LOG(SH4, " p = %x, id = %x", r[4], r[5]); // might be useful to detect errors? (hidden & dangerous) //if (!strcmp("GetProcName", method)) // os_DebugBreak(); diff --git a/core/hw/sh4/sh4_core.h b/core/hw/sh4/sh4_core.h index 15ec9fb02..42eb69dac 100644 --- a/core/hw/sh4/sh4_core.h +++ b/core/hw/sh4/sh4_core.h @@ -43,7 +43,7 @@ static INLINE f64 GetDR(u32 n) { #ifdef TRACE if (n>7) - printf("DR_r INDEX OVERRUN %d >7",n); + INFO_LOG(SH4, "DR_r INDEX OVERRUN %d >7", n); #endif DoubleReg t; @@ -57,7 +57,7 @@ static INLINE f64 GetXD(u32 n) { #ifdef TRACE if (n>7) - printf("XD_r INDEX OVERRUN %d >7",n); + INFO_LOG(SH4, "XD_r INDEX OVERRUN %d >7", n); #endif DoubleReg t; @@ -71,7 +71,7 @@ static INLINE void SetDR(u32 n,f64 val) { #ifdef TRACE if (n>7) - printf("DR_w INDEX OVERRUN %d >7",n); + INFO_LOG(SH4, "DR_w INDEX OVERRUN %d >7", n); #endif DoubleReg t; t.dbl=val; @@ -85,7 +85,7 @@ static INLINE void SetXD(u32 n,f64 val) { #ifdef TRACE if (n>7) - printf("XD_w INDEX OVERRUN %d >7",n); + INFO_LOG(SH4, "XD_w INDEX OVERRUN %d >7", n); #endif DoubleReg t; diff --git a/core/hw/sh4/sh4_core_regs.cpp b/core/hw/sh4/sh4_core_regs.cpp index 5bbfff5c7..c20c7ddef 100644 --- a/core/hw/sh4/sh4_core_regs.cpp +++ b/core/hw/sh4/sh4_core_regs.cpp @@ -45,7 +45,7 @@ bool UpdateSR() { if (sr.RB) { - printf("UpdateSR MD=0;RB=1 , this must not happen\n"); + WARN_LOG(SH4, "UpdateSR MD=0;RB=1 , this must not happen"); sr.RB =0;//error - must always be 0 } if (old_sr.RB) @@ -240,7 +240,7 @@ u32* Sh4_int_GetRegisterPtr(Sh4RegType reg) return &Sh4cntx.jdyn; default: - EMUERROR2("Unknown register ID %d",reg); + ERROR_LOG(SH4, "Unknown register ID %d", reg); die("Invalid reg"); return 0; break; diff --git a/core/hw/sh4/sh4_mmr.cpp b/core/hw/sh4/sh4_mmr.cpp index da28ec5d4..ca6ca8830 100644 --- a/core/hw/sh4/sh4_mmr.cpp +++ b/core/hw/sh4/sh4_mmr.cpp @@ -28,17 +28,17 @@ Array SCIF(10,true); //SCIF : 10 registers u32 sh4io_read_noacc(u32 addr) { - EMUERROR("sh4io: Invalid read access @@ %08X",addr); + INFO_LOG(SH4, "sh4io: Invalid read access @@ %08X", addr); return 0; } void sh4io_write_noacc(u32 addr, u32 data) { - EMUERROR("sh4io: Invalid write access @@ %08X %08X",addr,data); + INFO_LOG(SH4, "sh4io: Invalid write access @@ %08X %08X", addr, data); //verify(false); } void sh4io_write_const(u32 addr, u32 data) { - EMUERROR("sh4io: Const write ignored @@ %08X <- %08X",addr,data); + INFO_LOG(SH4, "sh4io: Const write ignored @@ %08X <- %08X", addr, data); } void sh4_rio_reg(Array& arr, u32 addr, RegIO flags, u32 sz, RegReadAddrFP* rf, RegWriteAddrFP* wf) @@ -77,7 +77,7 @@ u32 sh4_rio_read(Array& sb_regs, u32 addr) #ifdef TRACE if (offset & 3/*(size-1)*/) //4 is min align size { - EMUERROR("Unaligned System Bus register read"); + INFO_LOG(SH4, "Unaligned System Bus register read"); } #endif @@ -105,7 +105,7 @@ u32 sh4_rio_read(Array& sb_regs, u32 addr) else { if (!(sb_regs[offset].flags& REG_NOT_IMPL)) - EMUERROR("ERROR [wrong size read on register]"); + INFO_LOG(SH4, "ERROR [wrong size read on register]"); } #endif // if ((sb_regs[offset].flags& REG_NOT_IMPL)) @@ -120,7 +120,7 @@ void sh4_rio_write(Array& sb_regs, u32 addr, u32 data) #ifdef TRACE if (offset & 3/*(size-1)*/) //4 is min align size { - EMUERROR("Unaligned System bus register write"); + INFO_LOG(SH4, "Unaligned System bus register write"); } #endif offset>>=2; @@ -165,10 +165,10 @@ offset>>=2; else { if (!(sb_regs[offset].flags& REG_NOT_IMPL)) - EMUERROR4("ERROR: Wrong size write on register - offset=%x, data=%x, size=%d",offset,data,sz); + INFO_LOG(SH4, "ERROR: Wrong size write on register - offset=%x, data=%x, size=%d",offset,data,sz); } if ((sb_regs[offset].flags& REG_NOT_IMPL)) - EMUERROR3("Write to System Control Regs, not implemented - addr=%x, data=%x",addr,data); + INFO_LOG(SH4, "Write to System Control Regs, not implemented - addr=%x, data=%x",addr,data); #endif } @@ -190,7 +190,7 @@ T DYNACALL ReadMem_P4(u32 addr) case 0xE1: case 0xE2: case 0xE3: - EMUERROR("Unhandled p4 read [Store queue] 0x%x",addr); + INFO_LOG(SH4, "Unhandled p4 read [Store queue] 0x%x", addr); return 0; break; @@ -249,15 +249,14 @@ T DYNACALL ReadMem_P4(u32 addr) break; case 0xFF: - EMUERROR("Unhandled p4 read [area7] 0x%x",addr); + INFO_LOG(SH4, "Unhandled p4 read [area7] 0x%x", addr); break; default: - EMUERROR("Unhandled p4 read [Reserved] 0x%x",addr); + INFO_LOG(SH4, "Unhandled p4 read [Reserved] 0x%x", addr); break; } - EMUERROR("Read from P4 not implemented - addr=%x",addr); return 0; } @@ -279,7 +278,7 @@ void DYNACALL WriteMem_P4(u32 addr,T data) case 0xE1: case 0xE2: case 0xE3: - EMUERROR("Unhandled p4 Write [Store queue] 0x%x",addr); + INFO_LOG(SH4, "Unhandled p4 Write [Store queue] 0x%x", addr); break; case 0xF0: @@ -337,7 +336,7 @@ void DYNACALL WriteMem_P4(u32 addr,T data) if (addr&0x80) { #ifdef NO_MMU - EMUERROR("Unhandled p4 Write [Unified TLB address array, Associative Write] 0x%x = %x",addr,data); + INFO_LOG(SH4, "Unhandled p4 Write [Unified TLB address array, Associative Write] 0x%x = %x", addr, data); #endif CCN_PTEH_type t; @@ -398,15 +397,13 @@ void DYNACALL WriteMem_P4(u32 addr,T data) } case 0xFF: - EMUERROR("Unhandled p4 Write [area7] 0x%x = %x",addr,data); + INFO_LOG(SH4, "Unhandled p4 Write [area7] 0x%x = %x", addr, data); break; default: - EMUERROR("Unhandled p4 Write [Reserved] 0x%x",addr); + INFO_LOG(SH4, "Unhandled p4 Write [Reserved] 0x%x", addr); break; } - - EMUERROR3("Write to P4 not implemented - addr=%x, data=%x",addr,data); } @@ -420,7 +417,7 @@ T DYNACALL ReadMem_sq(u32 addr) { if (sz!=4) { - EMUERROR("Store Queue Error - only 4 byte read are possible[x%X]",addr); + INFO_LOG(SH4, "Store Queue Error - only 4 byte read are possible[x%X]", addr); return 0xDE; } @@ -435,7 +432,7 @@ template void DYNACALL WriteMem_sq(u32 addr,T data) { if (sz!=4) - EMUERROR("Store Queue Error - only 4 byte writes are possible[x%X=0x%X]",addr,data); + INFO_LOG(SH4, "Store Queue Error - only 4 byte writes are possible[x%X=0x%X]", addr, data); u32 united_offset=addr & 0x3C; @@ -481,7 +478,7 @@ T DYNACALL ReadMem_area7(u32 addr) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -492,7 +489,7 @@ T DYNACALL ReadMem_area7(u32 addr) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -504,16 +501,16 @@ T DYNACALL ReadMem_area7(u32 addr) else if ((addr>=BSC_SDMR2_addr) && (addr<= 0x1F90FFFF)) { //dram settings 2 / write only - EMUERROR("Read from write-only registers [dram settings 2]"); + INFO_LOG(SH4, "Read from write-only registers [dram settings 2]"); } else if ((addr>=BSC_SDMR3_addr) && (addr<= 0x1F94FFFF)) { //dram settings 3 / write only - EMUERROR("Read from write-only registers [dram settings 3]"); + INFO_LOG(SH4, "Read from write-only registers [dram settings 3]"); } else { - EMUERROR2("Out of range on register index . %x",addr); + INFO_LOG(SH4, "Out of range on register index . %x", addr); } break; @@ -526,7 +523,7 @@ T DYNACALL ReadMem_area7(u32 addr) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -537,7 +534,7 @@ T DYNACALL ReadMem_area7(u32 addr) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -548,7 +545,7 @@ T DYNACALL ReadMem_area7(u32 addr) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -559,7 +556,7 @@ T DYNACALL ReadMem_area7(u32 addr) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -570,7 +567,7 @@ T DYNACALL ReadMem_area7(u32 addr) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -581,7 +578,7 @@ T DYNACALL ReadMem_area7(u32 addr) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -592,7 +589,7 @@ T DYNACALL ReadMem_area7(u32 addr) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -613,7 +610,7 @@ T DYNACALL ReadMem_area7(u32 addr) } - //EMUERROR2("Unknown Read from Area7 - addr=%x",addr); + //INFO_LOG(SH4, "Unknown Read from Area7 - addr=%x", addr); return 0; } @@ -647,7 +644,7 @@ void DYNACALL WriteMem_area7(u32 addr,T data) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -659,7 +656,7 @@ void DYNACALL WriteMem_area7(u32 addr,T data) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -681,7 +678,7 @@ void DYNACALL WriteMem_area7(u32 addr,T data) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -695,7 +692,7 @@ void DYNACALL WriteMem_area7(u32 addr,T data) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -707,7 +704,7 @@ void DYNACALL WriteMem_area7(u32 addr,T data) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -719,7 +716,7 @@ void DYNACALL WriteMem_area7(u32 addr,T data) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -731,7 +728,7 @@ void DYNACALL WriteMem_area7(u32 addr,T data) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -743,7 +740,7 @@ void DYNACALL WriteMem_area7(u32 addr,T data) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -755,7 +752,7 @@ void DYNACALL WriteMem_area7(u32 addr,T data) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -767,7 +764,7 @@ void DYNACALL WriteMem_area7(u32 addr,T data) } else { - EMUERROR2("Out of range on register index %x",addr); + INFO_LOG(SH4, "Out of range on register index %x", addr); } break; @@ -808,13 +805,13 @@ T DYNACALL ReadMem_area7_OCR_T(u32 addr) return (T)*(u32*)&OnChipRAM[addr&OnChipRAM_MASK]; else { - EMUERROR("ReadMem_area7_OCR_T: template SZ is wrong = %d",sz); + ERROR_LOG(SH4, "ReadMem_area7_OCR_T: template SZ is wrong = %d", sz); return 0xDE; } } else { - EMUERROR("On Chip Ram Read, but OCR is disabled"); + INFO_LOG(SH4, "On Chip Ram Read, but OCR is disabled"); return 0xDE; } } @@ -833,12 +830,12 @@ void DYNACALL WriteMem_area7_OCR_T(u32 addr,T data) *(u32*)&OnChipRAM[addr&OnChipRAM_MASK]=data; else { - EMUERROR("WriteMem_area7_OCR_T: template SZ is wrong = %d",sz); + ERROR_LOG(SH4, "WriteMem_area7_OCR_T: template SZ is wrong = %d", sz); } } else { - EMUERROR("On Chip Ram Write, but OCR is disabled"); + INFO_LOG(SH4, "On Chip Ram Write, but OCR is disabled"); } } diff --git a/core/hw/sh4/sh4_opcode_list.cpp b/core/hw/sh4/sh4_opcode_list.cpp index 7ae9b64ef..916853894 100644 --- a/core/hw/sh4/sh4_opcode_list.cpp +++ b/core/hw/sh4/sh4_opcode_list.cpp @@ -608,7 +608,7 @@ std::string disassemble_op(const char* tx1, u32 pc, u16 opcode) ti++; } - printf("Sh4Dissasm : Tag not known\"%s\"\n",tx1); + DEBUG_LOG(SH4, "Sh4Dissasm : Tag not known\"%s\"", tx1); buf[0] = '<'; buf[1] = *tx1; diff --git a/core/log/Log.h b/core/log/Log.h index dc35e1615..f046c1f93 100644 --- a/core/log/Log.h +++ b/core/log/Log.h @@ -28,6 +28,7 @@ enum LOG_TYPE PVR, RENDERER, SAVESTATE, + SH4, NUMBER_OF_LOGS // Must be last }; diff --git a/core/log/LogManager.cpp b/core/log/LogManager.cpp index bf2ccefc2..051f9eee7 100644 --- a/core/log/LogManager.cpp +++ b/core/log/LogManager.cpp @@ -111,6 +111,7 @@ LogManager::LogManager() m_log[LogTypes::PVR] = {"PVR", "PowerVR GPU"}; m_log[LogTypes::RENDERER] = {"RENDERER", "OpenGL Renderer"}; m_log[LogTypes::SAVESTATE] = {"SAVESTATE", "Save States"}; + m_log[LogTypes::SH4] = {"SH4", "SH4 Modules"}; RegisterListener(LogListener::FILE_LISTENER, new FileLogListener("flycast.log")); RegisterListener(LogListener::CONSOLE_LISTENER, new ConsoleListener());