ssa: fix regression

due to fff03f64a3
Issue #1773
This commit is contained in:
Flyinghead 2024-12-08 10:40:44 +01:00
parent fff03f64a3
commit 15617c1816
1 changed files with 26 additions and 22 deletions

View File

@ -285,32 +285,36 @@ private:
{
// Replace shld/shad with shl/shr/sar
u32 r2 = op.rs2.imm_value();
if ((r2 & 0x1F) == 0)
if (r2 != 0) // r2 == 0 is nop, handled in SimplifyExpressionPass()
{
if (op.op == shop_shld)
// rd = 0
ReplaceByMov32(op, 0);
else
if ((r2 & 0x1F) == 0)
{
// rd = r1 >> 31;
op.op = shop_sar;
op.rs2._imm = 31;
if (op.op == shop_shld) {
// rd = 0
ReplaceByMov32(op, 0);
}
else
{
// rd = r1 >> 31
op.op = shop_sar;
op.rs2._imm = 31;
stats.constant_ops_replaced++;
}
}
else if ((r2 & 0x80000000) == 0)
{
// rd = r1 << (r2 & 0x1F)
op.op = shop_shl;
op.rs2._imm = r2 & 0x1F;
stats.constant_ops_replaced++;
}
else
{
// rd = r1 >> ((~r2 & 0x1F) + 1)
op.op = op.op == shop_shad ? shop_sar : shop_shr;
op.rs2._imm = (~r2 & 0x1F) + 1;
stats.constant_ops_replaced++;
}
}
else if ((r2 & 0x80000000) == 0)
{
// rd = r1 << (r2 & 0x1F)
op.op = shop_shl;
op.rs2._imm = r2 & 0x1F;
stats.constant_ops_replaced++;
}
else
{
// rd = r1 >> ((~r2 & 0x1F) + 1)
op.op = op.op == shop_shad ? shop_sar : shop_shr;
op.rs2._imm = (~r2 & 0x1F) + 1;
stats.constant_ops_replaced++;
}
}
}