add shil dynarec
This commit is contained in:
Joseph Mattiello
parent
0c85801096
commit
1205e6daca
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@ -0,0 +1,18 @@
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#pragma once
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// Simple Arm-NEON helpers used by SH4 interpreter fast paths
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#if defined(__aarch64__)
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#include <arm_neon.h>
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// Multiply-accumulate 4 pairs of signed 16-bit values and return 64-bit sum
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static inline int64_t mac_w_4x(const uint16_t* __restrict pA,
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const uint16_t* __restrict pB)
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{
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int16x4_t a = vld1_s16((const int16_t*)pA); // load 4 halfwords
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int16x4_t b = vld1_s16((const int16_t*)pB);
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int32x4_t prod = vmull_s16(a, b); // 4 × 32-bit products
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// add horizontally: pairwise add, then widen to 64-bit and add again
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int64x2_t sum2 = vpaddlq_s32(vcombine_s32(vget_low_s32(prod),
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vget_high_s32(prod)));
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return vgetq_lane_s64(sum2, 0) + vgetq_lane_s64(sum2, 1);
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}
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#endif // __aarch64__
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@ -0,0 +1,110 @@
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#include "shil_dynarec.h"
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#include "hw/sh4/sh4_core.h"
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#include "hw/sh4/sh4_interrupts.h"
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#include "hw/sh4/sh4_mem.h"
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#include "oslib/oslib.h"
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// Simple stub function that will be used as the "compiled" code pointer
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static void shil_interpreter_stub() {
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// This function should never actually be called
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// The mainloop will detect SHIL blocks and call the interpreter directly
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}
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void ShilDynarec::init(Sh4CodeBuffer& buffer) {
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this->codeBuffer = &buffer;
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}
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void ShilDynarec::compile(RuntimeBlockInfo* block, bool smc_checks, bool optimise) {
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// For SHIL interpreter, we don't actually compile anything
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// We just set the code pointer to our stub function
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// The real magic happens in mainloop() which detects this and calls the interpreter
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block->code = (DynarecCodeEntryPtr)shil_interpreter_stub;
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block->host_code_size = 4; // Minimal size
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block->host_opcodes = block->oplist.size(); // Number of SHIL opcodes
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}
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void ShilDynarec::executeShilBlock(RuntimeBlockInfo* block) {
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ShilInterpreter::executeBlock(block);
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}
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void ShilDynarec::mainloop(void* cntx) {
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// Set up context
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p_sh4rcb = (Sh4RCB*)((u8*)cntx - sizeof(Sh4cntx));
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try {
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while (sh4_int_bCpuRun) {
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// Check for exceptions first
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if (UpdateSystem()) {
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// Exception occurred, continue with exception PC
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continue;
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}
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// Get the next block to execute
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DynarecCodeEntryPtr code_ptr = rdv_FindOrCompile();
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if (code_ptr == ngen_FailedToFindBlock) {
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code_ptr = rdv_FailedToFindBlock(next_pc);
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}
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// Check if this is a SHIL interpreter block
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if (code_ptr == (DynarecCodeEntryPtr)shil_interpreter_stub) {
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// This is a SHIL block - execute via interpreter
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RuntimeBlockInfoPtr block = bm_GetBlock(next_pc);
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if (block) {
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executeShilBlock(block.get());
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// After executing the block, determine next PC based on block type
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switch (BET_GET_CLS(block->BlockType)) {
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case BET_CLS_Static:
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if (block->BlockType == BET_StaticIntr) {
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next_pc = block->NextBlock;
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} else {
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next_pc = block->BranchBlock;
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}
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break;
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case BET_CLS_Dynamic:
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// PC should have been set by the block execution
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next_pc = Sh4cntx.pc;
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break;
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case BET_CLS_COND:
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// Conditional branch - check the condition
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if (sr.T) {
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next_pc = block->BranchBlock;
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} else {
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next_pc = block->NextBlock;
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}
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break;
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}
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} else {
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// Block not found - this shouldn't happen
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ERROR_LOG(DYNAREC, "SHIL block not found for PC %08X", next_pc);
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break;
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}
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} else {
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// This is a regular JIT block - this shouldn't happen in SHIL mode
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ERROR_LOG(DYNAREC, "Unexpected JIT block in SHIL mode at PC %08X", next_pc);
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break;
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}
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}
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} catch (const SH4ThrownException& ex) {
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// Handle SH4 exceptions
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Do_Exception(next_pc, ex.expEvn);
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} catch (const FlycastException& ex) {
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// Handle other exceptions
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ERROR_LOG(DYNAREC, "Exception in SHIL mainloop: %s", ex.what());
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sh4_int_bCpuRun = false;
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}
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}
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void ShilDynarec::handleException(host_context_t& context) {
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// For the interpreter, we don't need to do anything special
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// Exceptions are handled normally in the mainloop
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}
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bool ShilDynarec::rewrite(host_context_t& context, void *faultAddress) {
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// Memory rewriting is not needed for the interpreter
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return false;
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}
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@ -0,0 +1,36 @@
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#pragma once
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#include "ngen.h"
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#include "shil_interpreter.h"
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/// A dynarec backend that interprets SHIL instead of compiling to native code
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class ShilDynarec : public Sh4Dynarec {
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private:
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Sh4CodeBuffer* codeBuffer = nullptr;
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public:
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// Initialize the dynarec
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void init(Sh4CodeBuffer& codeBuffer) override;
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// "Compile" the block by storing it for interpretation
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void compile(RuntimeBlockInfo* block, bool smc_checks, bool optimise) override;
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// Run the main execution loop
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void mainloop(void* cntx) override;
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// Handle exceptions
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void handleException(host_context_t& context) override;
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// Memory rewrite (not needed for interpreter)
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bool rewrite(host_context_t& context, void *faultAddress) override;
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// Canonical implementation callbacks (not used in interpreter mode)
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void canonStart(const shil_opcode *op) override {}
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void canonParam(const shil_opcode *op, const shil_param *param, CanonicalParamType paramType) override {}
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void canonCall(const shil_opcode *op, void *function) override {}
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void canonFinish(const shil_opcode *op) override {}
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private:
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/// Execute a SHIL block via interpretation
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static void executeShilBlock(RuntimeBlockInfo* block);
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};
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@ -0,0 +1,537 @@
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#include "shil_interpreter.h"
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#include "hw/sh4/sh4_core.h"
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#include "hw/sh4/sh4_mem.h"
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#include "hw/sh4/sh4_interrupts.h"
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#include "hw/sh4/sh4_opcode_list.h"
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#include "emulator.h"
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#include "cfg/cfg.h"
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#include "blockmanager.h"
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#include "ngen.h"
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#include <cmath>
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// Global flag to enable SHIL interpretation mode
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bool enable_shil_interpreter = false;
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// Initialize SHIL interpreter setting from config
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void init_shil_interpreter_setting() {
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static bool initialized = false;
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if (!initialized) {
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enable_shil_interpreter = cfgLoadBool("dynarec", "UseShilInterpreter", false);
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initialized = true;
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}
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}
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// Global flag to indicate if we should exit block execution
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static bool should_exit_block = false;
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// OPTIMIZATION: Inline register access functions to avoid function call overhead
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static inline u32 getRegValue(const shil_param& param) {
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if (param.is_imm()) {
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return param.imm_value();
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} else if (param.is_reg()) {
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return *param.reg_ptr();
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}
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return 0;
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}
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static inline void setRegValue(const shil_param& param, u32 value) {
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if (param.is_reg()) {
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*param.reg_ptr() = value;
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}
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}
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static inline f32 getFloatRegValue(const shil_param& param) {
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if (param.is_imm()) {
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return *(f32*)¶m._imm;
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} else if (param.is_reg()) {
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return *(f32*)param.reg_ptr();
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}
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return 0.0f;
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}
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static inline void setFloatRegValue(const shil_param& param, f32 value) {
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if (param.is_reg()) {
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*(f32*)param.reg_ptr() = value;
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}
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}
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// OPTIMIZATION: Fast path for common register-to-register moves
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static inline void fastMov32(const shil_param& dst, const shil_param& src) {
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if (dst.is_reg() && src.is_reg()) {
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*dst.reg_ptr() = *src.reg_ptr();
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} else if (dst.is_reg() && src.is_imm()) {
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*dst.reg_ptr() = src.imm_value();
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} else {
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setRegValue(dst, getRegValue(src));
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}
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}
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// OPTIMIZATION: Fast path for common arithmetic operations
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static inline void fastAdd(const shil_param& dst, const shil_param& src1, const shil_param& src2) {
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if (dst.is_reg() && src1.is_reg() && src2.is_reg()) {
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*dst.reg_ptr() = *src1.reg_ptr() + *src2.reg_ptr();
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} else if (dst.is_reg() && src1.is_reg() && src2.is_imm()) {
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*dst.reg_ptr() = *src1.reg_ptr() + src2.imm_value();
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} else {
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setRegValue(dst, getRegValue(src1) + getRegValue(src2));
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}
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}
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static inline void fastSub(const shil_param& dst, const shil_param& src1, const shil_param& src2) {
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if (dst.is_reg() && src1.is_reg() && src2.is_reg()) {
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*dst.reg_ptr() = *src1.reg_ptr() - *src2.reg_ptr();
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} else if (dst.is_reg() && src1.is_reg() && src2.is_imm()) {
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*dst.reg_ptr() = *src1.reg_ptr() - src2.imm_value();
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} else {
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setRegValue(dst, getRegValue(src1) - getRegValue(src2));
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}
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}
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// OPTIMIZATION: Fast path for bitwise operations
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static inline void fastAnd(const shil_param& dst, const shil_param& src1, const shil_param& src2) {
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if (dst.is_reg() && src1.is_reg() && src2.is_reg()) {
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*dst.reg_ptr() = *src1.reg_ptr() & *src2.reg_ptr();
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} else if (dst.is_reg() && src1.is_reg() && src2.is_imm()) {
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*dst.reg_ptr() = *src1.reg_ptr() & src2.imm_value();
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} else {
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setRegValue(dst, getRegValue(src1) & getRegValue(src2));
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}
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}
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static inline void fastOr(const shil_param& dst, const shil_param& src1, const shil_param& src2) {
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if (dst.is_reg() && src1.is_reg() && src2.is_reg()) {
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*dst.reg_ptr() = *src1.reg_ptr() | *src2.reg_ptr();
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} else if (dst.is_reg() && src1.is_reg() && src2.is_imm()) {
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*dst.reg_ptr() = *src1.reg_ptr() | src2.imm_value();
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} else {
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setRegValue(dst, getRegValue(src1) | getRegValue(src2));
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}
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}
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static inline void fastXor(const shil_param& dst, const shil_param& src1, const shil_param& src2) {
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if (dst.is_reg() && src1.is_reg() && src2.is_reg()) {
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*dst.reg_ptr() = *src1.reg_ptr() ^ *src2.reg_ptr();
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} else if (dst.is_reg() && src1.is_reg() && src2.is_imm()) {
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*dst.reg_ptr() = *src1.reg_ptr() ^ src2.imm_value();
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} else {
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setRegValue(dst, getRegValue(src1) ^ getRegValue(src2));
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}
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}
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// Remove old member functions - they're now static inline
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u32 ShilInterpreter::getRegValue(const shil_param& param) {
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return ::getRegValue(param);
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}
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void ShilInterpreter::setRegValue(const shil_param& param, u32 value) {
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::setRegValue(param, value);
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}
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f32 ShilInterpreter::getFloatRegValue(const shil_param& param) {
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return ::getFloatRegValue(param);
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}
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void ShilInterpreter::setFloatRegValue(const shil_param& param, f32 value) {
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::setFloatRegValue(param, value);
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}
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u64 ShilInterpreter::getReg64Value(const shil_param& param) {
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if (param.is_imm()) {
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return param.imm_value();
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} else if (param.is_reg()) {
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return *reinterpret_cast<u64*>(param.reg_ptr());
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}
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return 0;
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}
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void ShilInterpreter::setReg64Value(const shil_param& param, u64 value) {
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if (param.is_reg()) {
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*reinterpret_cast<u64*>(param.reg_ptr()) = value;
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}
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}
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void* ShilInterpreter::getPointer(const shil_param& param) {
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if (param.is_reg()) {
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return param.reg_ptr();
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}
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return nullptr;
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}
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u32 ShilInterpreter::handleMemoryRead(const shil_param& addr, u32 size) {
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u32 address = getRegValue(addr);
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switch (size) {
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case 1: return ReadMem8(address);
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case 2: return ReadMem16(address);
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case 4: return ReadMem32(address);
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default: return 0;
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}
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}
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void ShilInterpreter::handleMemoryWrite(const shil_param& addr, const shil_param& value, u32 size) {
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u32 address = getRegValue(addr);
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u32 val = getRegValue(value);
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switch (size) {
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case 1: WriteMem8(address, val); break;
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case 2: WriteMem16(address, val); break;
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case 4: WriteMem32(address, val); break;
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}
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}
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void ShilInterpreter::handleInterpreterFallback(const shil_opcode& op) {
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// Set PC if needed
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if (op.rs1.imm_value()) {
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next_pc = op.rs2.imm_value();
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}
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// Call SH4 instruction handler directly
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u32 opcode = op.rs3.imm_value();
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OpDesc[opcode]->oph(opcode);
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// Exit block after fallback
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should_exit_block = true;
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}
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void ShilInterpreter::handleDynamicJump(const shil_opcode& op) {
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// Set dynamic PC
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u32 target = getRegValue(op.rs1);
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if (!op.rs2.is_null()) {
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target += getRegValue(op.rs2);
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}
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*op.rd.reg_ptr() = target;
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should_exit_block = true;
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}
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void ShilInterpreter::handleConditionalJump(const shil_opcode& op) {
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// Set conditional jump target
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u32 target = getRegValue(op.rs2);
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*op.rd.reg_ptr() = target;
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should_exit_block = true;
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}
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// OPTIMIZATION: Optimized executeOpcode with fast paths and better branch prediction
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void ShilInterpreter::executeOpcode(const shil_opcode& op) {
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// OPTIMIZATION: Fast paths for the most common operations
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switch (op.op) {
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case shop_mov32:
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fastMov32(op.rd, op.rs1);
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return;
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case shop_add:
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fastAdd(op.rd, op.rs1, op.rs2);
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return;
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case shop_sub:
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fastSub(op.rd, op.rs1, op.rs2);
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return;
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case shop_and:
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fastAnd(op.rd, op.rs1, op.rs2);
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return;
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case shop_or:
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fastOr(op.rd, op.rs1, op.rs2);
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return;
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case shop_xor:
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fastXor(op.rd, op.rs1, op.rs2);
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return;
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case shop_readm: {
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u32 addr = getRegValue(op.rs1);
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u32 size = op.rs2._imm;
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// OPTIMIZATION: Fast path for common 32-bit reads
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if (__builtin_expect(size == 4, 1)) {
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setRegValue(op.rd, ReadMem32(addr));
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return;
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}
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// Handle other sizes
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u32 value = 0;
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switch (size) {
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case 1: value = ReadMem8(addr); break;
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case 2: value = ReadMem16(addr); break;
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case 8: {
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u64 val64 = ReadMem64(addr);
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setRegValue(op.rd, (u32)val64);
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setRegValue(op.rd2, (u32)(val64 >> 32));
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return;
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}
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}
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setRegValue(op.rd, value);
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return;
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}
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case shop_writem: {
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u32 addr = getRegValue(op.rs1);
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u32 size = op.rs2._imm;
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// OPTIMIZATION: Fast path for common 32-bit writes
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if (__builtin_expect(size == 4, 1)) {
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WriteMem32(addr, getRegValue(op.rs3));
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return;
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}
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// Handle other sizes
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u32 value = getRegValue(op.rs3);
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switch (size) {
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case 1: WriteMem8(addr, value); break;
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case 2: WriteMem16(addr, value); break;
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case 8: {
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u64 val64 = ((u64)getRegValue(op.rs3) << 32) | getRegValue(op.rs2);
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WriteMem64(addr, val64);
|
||||
break;
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
case shop_jcond:
|
||||
if (__builtin_expect(sr.T == op.rs2._imm, 0)) {
|
||||
next_pc = getRegValue(op.rs1);
|
||||
should_exit_block = true;
|
||||
}
|
||||
return;
|
||||
|
||||
case shop_jdyn:
|
||||
next_pc = getRegValue(op.rs1);
|
||||
should_exit_block = true;
|
||||
return;
|
||||
|
||||
case shop_pref:
|
||||
// Prefetch instruction - no-op for interpreter
|
||||
return;
|
||||
|
||||
// Continue with remaining opcodes
|
||||
case shop_mov64:
|
||||
setRegValue(op.rd, getRegValue(op.rs1));
|
||||
setRegValue(op.rd2, getRegValue(op.rs2));
|
||||
break;
|
||||
|
||||
case shop_mul_u16:
|
||||
setRegValue(op.rd, (u16)getRegValue(op.rs1) * (u16)getRegValue(op.rs2));
|
||||
break;
|
||||
|
||||
case shop_mul_s16:
|
||||
setRegValue(op.rd, (s16)getRegValue(op.rs1) * (s16)getRegValue(op.rs2));
|
||||
break;
|
||||
|
||||
case shop_mul_i32:
|
||||
setRegValue(op.rd, (s32)getRegValue(op.rs1) * (s32)getRegValue(op.rs2));
|
||||
break;
|
||||
|
||||
case shop_mul_u64:
|
||||
{
|
||||
u64 result = (u64)getRegValue(op.rs1) * (u64)getRegValue(op.rs2);
|
||||
setRegValue(op.rd, (u32)result);
|
||||
setRegValue(op.rd2, (u32)(result >> 32));
|
||||
}
|
||||
break;
|
||||
|
||||
case shop_mul_s64:
|
||||
{
|
||||
s64 result = (s64)(s32)getRegValue(op.rs1) * (s64)(s32)getRegValue(op.rs2);
|
||||
setRegValue(op.rd, (u32)result);
|
||||
setRegValue(op.rd2, (u32)(result >> 32));
|
||||
}
|
||||
break;
|
||||
|
||||
case shop_not:
|
||||
setRegValue(op.rd, ~getRegValue(op.rs1));
|
||||
break;
|
||||
|
||||
case shop_shl:
|
||||
setRegValue(op.rd, getRegValue(op.rs1) << (getRegValue(op.rs2) & 0x1F));
|
||||
break;
|
||||
|
||||
case shop_shr:
|
||||
setRegValue(op.rd, getRegValue(op.rs1) >> (getRegValue(op.rs2) & 0x1F));
|
||||
break;
|
||||
|
||||
case shop_sar:
|
||||
setRegValue(op.rd, (s32)getRegValue(op.rs1) >> (getRegValue(op.rs2) & 0x1F));
|
||||
break;
|
||||
|
||||
case shop_neg:
|
||||
setRegValue(op.rd, -(s32)getRegValue(op.rs1));
|
||||
break;
|
||||
|
||||
case shop_swaplb:
|
||||
{
|
||||
u32 val = getRegValue(op.rs1);
|
||||
setRegValue(op.rd, (val & 0xFFFF0000) | ((val & 0xFF) << 8) | ((val >> 8) & 0xFF));
|
||||
}
|
||||
break;
|
||||
|
||||
case shop_test:
|
||||
sr.T = (getRegValue(op.rs1) & getRegValue(op.rs2)) == 0 ? 1 : 0;
|
||||
break;
|
||||
|
||||
case shop_seteq:
|
||||
sr.T = (getRegValue(op.rs1) == getRegValue(op.rs2)) ? 1 : 0;
|
||||
break;
|
||||
|
||||
case shop_setge:
|
||||
sr.T = ((s32)getRegValue(op.rs1) >= (s32)getRegValue(op.rs2)) ? 1 : 0;
|
||||
break;
|
||||
|
||||
case shop_setgt:
|
||||
sr.T = ((s32)getRegValue(op.rs1) > (s32)getRegValue(op.rs2)) ? 1 : 0;
|
||||
break;
|
||||
|
||||
case shop_setab:
|
||||
sr.T = (getRegValue(op.rs1) > getRegValue(op.rs2)) ? 1 : 0;
|
||||
break;
|
||||
|
||||
case shop_setae:
|
||||
sr.T = (getRegValue(op.rs1) >= getRegValue(op.rs2)) ? 1 : 0;
|
||||
break;
|
||||
|
||||
case shop_ext_s8:
|
||||
setRegValue(op.rd, (s32)(s8)getRegValue(op.rs1));
|
||||
break;
|
||||
|
||||
case shop_ext_s16:
|
||||
setRegValue(op.rd, (s32)(s16)getRegValue(op.rs1));
|
||||
break;
|
||||
|
||||
case shop_cvt_i2f_n:
|
||||
setFloatRegValue(op.rd, (f32)(s32)getRegValue(op.rs1));
|
||||
break;
|
||||
|
||||
case shop_cvt_f2i_t:
|
||||
setRegValue(op.rd, (u32)(s32)getFloatRegValue(op.rs1));
|
||||
break;
|
||||
|
||||
case shop_fadd:
|
||||
setFloatRegValue(op.rd, getFloatRegValue(op.rs1) + getFloatRegValue(op.rs2));
|
||||
break;
|
||||
|
||||
case shop_fsub:
|
||||
setFloatRegValue(op.rd, getFloatRegValue(op.rs1) - getFloatRegValue(op.rs2));
|
||||
break;
|
||||
|
||||
case shop_fmul:
|
||||
setFloatRegValue(op.rd, getFloatRegValue(op.rs1) * getFloatRegValue(op.rs2));
|
||||
break;
|
||||
|
||||
case shop_fdiv:
|
||||
setFloatRegValue(op.rd, getFloatRegValue(op.rs1) / getFloatRegValue(op.rs2));
|
||||
break;
|
||||
|
||||
case shop_fabs:
|
||||
setFloatRegValue(op.rd, fabsf(getFloatRegValue(op.rs1)));
|
||||
break;
|
||||
|
||||
case shop_fneg:
|
||||
setFloatRegValue(op.rd, -getFloatRegValue(op.rs1));
|
||||
break;
|
||||
|
||||
case shop_fsqrt:
|
||||
setFloatRegValue(op.rd, sqrtf(getFloatRegValue(op.rs1)));
|
||||
break;
|
||||
|
||||
case shop_fmac:
|
||||
setFloatRegValue(op.rd, getFloatRegValue(op.rs1) * getFloatRegValue(op.rs2) + getFloatRegValue(op.rs3));
|
||||
break;
|
||||
|
||||
case shop_fseteq:
|
||||
sr.T = (getFloatRegValue(op.rs1) == getFloatRegValue(op.rs2)) ? 1 : 0;
|
||||
break;
|
||||
|
||||
case shop_fsetgt:
|
||||
sr.T = (getFloatRegValue(op.rs1) > getFloatRegValue(op.rs2)) ? 1 : 0;
|
||||
break;
|
||||
|
||||
case shop_ifb:
|
||||
// Interpreter fallback - execute original SH4 instruction
|
||||
if (op.rs1._imm) {
|
||||
next_pc = op.rs2._imm;
|
||||
}
|
||||
{
|
||||
u32 opcode = op.rs3._imm;
|
||||
OpDesc[opcode]->oph(opcode);
|
||||
}
|
||||
should_exit_block = true;
|
||||
break;
|
||||
|
||||
default:
|
||||
// Unhandled opcode - fallback to interpreter
|
||||
WARN_LOG(DYNAREC, "Unhandled SHIL opcode: %d", op.op);
|
||||
should_exit_block = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// OPTIMIZATION: Optimized block execution with reduced function call overhead
|
||||
void ShilInterpreter::executeBlock(RuntimeBlockInfo* block) {
|
||||
should_exit_block = false;
|
||||
|
||||
// OPTIMIZATION: Cache block size to avoid repeated size() calls
|
||||
const size_t block_size = block->oplist.size();
|
||||
|
||||
// OPTIMIZATION: Direct pointer access to opcodes
|
||||
const shil_opcode* opcodes = block->oplist.data();
|
||||
|
||||
for (size_t i = 0; i < block_size && __builtin_expect(!should_exit_block, 1); i++) {
|
||||
executeOpcode(opcodes[i]);
|
||||
}
|
||||
}
|
||||
|
||||
// OPTIMIZATION: Optimized mainloop with reduced overhead
|
||||
void shil_interpreter_mainloop(void* v_cntx) {
|
||||
// Set up context similar to JIT mainloop
|
||||
p_sh4rcb = (Sh4RCB*)((u8*)v_cntx - sizeof(Sh4Context));
|
||||
|
||||
try {
|
||||
while (__builtin_expect(Sh4cntx.CpuRunning, 1)) {
|
||||
// OPTIMIZATION: Reduce interrupt checking frequency
|
||||
if (__builtin_expect(Sh4cntx.cycle_counter <= 0, 0)) {
|
||||
Sh4cntx.cycle_counter += SH4_TIMESLICE;
|
||||
if (UpdateSystem_INTC()) {
|
||||
// Interrupt occurred, continue to handle it
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
// Get current PC
|
||||
u32 pc = next_pc;
|
||||
|
||||
// Find or create block for current PC
|
||||
RuntimeBlockInfoPtr blockPtr = bm_GetBlock(pc);
|
||||
RuntimeBlockInfo* block = nullptr;
|
||||
|
||||
if (__builtin_expect(blockPtr != nullptr, 1)) {
|
||||
block = blockPtr.get();
|
||||
} else {
|
||||
// Block doesn't exist, we need to create and decode it
|
||||
// This will trigger the normal block creation process
|
||||
DynarecCodeEntryPtr code = rdv_CompilePC(0);
|
||||
if (!code) {
|
||||
ERROR_LOG(DYNAREC, "Failed to create block for PC: %08X", pc);
|
||||
break;
|
||||
}
|
||||
|
||||
// Get the block again after compilation
|
||||
blockPtr = bm_GetBlock(pc);
|
||||
if (!blockPtr) {
|
||||
ERROR_LOG(DYNAREC, "Block creation succeeded but block not found for PC: %08X", pc);
|
||||
break;
|
||||
}
|
||||
block = blockPtr.get();
|
||||
}
|
||||
|
||||
// Check if this is a SHIL interpreter block
|
||||
if (__builtin_expect(reinterpret_cast<uintptr_t>(block->code) & 0x1, 1)) {
|
||||
// This is a SHIL interpreter block
|
||||
ShilInterpreter::executeBlock(block);
|
||||
} else {
|
||||
// This is a regular JIT block - shouldn't happen in interpreter mode
|
||||
ERROR_LOG(DYNAREC, "Unexpected JIT block in SHIL interpreter mode");
|
||||
break;
|
||||
}
|
||||
|
||||
// Update cycle counter
|
||||
Sh4cntx.cycle_counter -= block->guest_cycles;
|
||||
}
|
||||
} catch (const SH4ThrownException&) {
|
||||
ERROR_LOG(DYNAREC, "SH4ThrownException in SHIL interpreter mainloop");
|
||||
throw FlycastException("Fatal: Unhandled SH4 exception");
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
#pragma once
|
||||
|
||||
#include "types.h"
|
||||
#include "shil.h"
|
||||
#include "blockmanager.h"
|
||||
|
||||
/// SHIL Interpreter - executes SHIL opcodes directly without JIT compilation
|
||||
class ShilInterpreter {
|
||||
public:
|
||||
/// Execute a single SHIL opcode
|
||||
static void executeOpcode(const shil_opcode& op);
|
||||
|
||||
/// Execute an entire SHIL block
|
||||
static void executeBlock(RuntimeBlockInfo* block);
|
||||
|
||||
/// Get register value for SHIL parameter
|
||||
static u32 getRegValue(const shil_param& param);
|
||||
|
||||
/// Set register value for SHIL parameter
|
||||
static void setRegValue(const shil_param& param, u32 value);
|
||||
|
||||
/// Get float register value for SHIL parameter
|
||||
static f32 getFloatRegValue(const shil_param& param);
|
||||
|
||||
/// Set float register value for SHIL parameter
|
||||
static void setFloatRegValue(const shil_param& param, f32 value);
|
||||
|
||||
/// Get 64-bit register value for SHIL parameter
|
||||
static u64 getReg64Value(const shil_param& param);
|
||||
|
||||
/// Set 64-bit register value for SHIL parameter
|
||||
static void setReg64Value(const shil_param& param, u64 value);
|
||||
|
||||
/// Get pointer for SHIL parameter
|
||||
static void* getPointer(const shil_param& param);
|
||||
|
||||
private:
|
||||
/// Handle memory read operations
|
||||
static u32 handleMemoryRead(const shil_param& addr, u32 size);
|
||||
|
||||
/// Handle memory write operations
|
||||
static void handleMemoryWrite(const shil_param& addr, const shil_param& value, u32 size);
|
||||
|
||||
/// Handle interpreter fallback (shop_ifb)
|
||||
static void handleInterpreterFallback(const shil_opcode& op);
|
||||
|
||||
/// Handle dynamic jumps (shop_jdyn)
|
||||
static void handleDynamicJump(const shil_opcode& op);
|
||||
|
||||
/// Handle conditional jumps (shop_jcond)
|
||||
static void handleConditionalJump(const shil_opcode& op);
|
||||
|
||||
/// Handle illegal instructions (shop_illegal)
|
||||
static void handleIllegalInstruction(const shil_opcode& op);
|
||||
};
|
||||
|
||||
/// Simple flag to enable SHIL interpretation mode
|
||||
extern bool enable_shil_interpreter;
|
||||
|
||||
/// Initialize SHIL interpreter setting from config
|
||||
void init_shil_interpreter_setting();
|
||||
|
||||
/// SHIL interpretation mainloop
|
||||
void shil_interpreter_mainloop(void* v_cntx);
|
||||
Loading…
Reference in New Issue