dynarec: more accurate cycle counting. limit code duplication
arm, arm64, x86: only account for current block cycles if block is executed. Test cycle_counter before updating it. arm, arm64: use function for mmu block check (vaddr and FPU ops) to reduce host code size per block.
This commit is contained in:
Flyinghead
parent
4eb5cd928e
commit
0b1f69bfd2
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@ -58,9 +58,8 @@ using namespace vixl::aarch32;
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Block linking
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Reg alloc
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r0~r4: scratch
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r5,r6,r7,r10,r11: allocated
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r5,r6,r7,r9,r10,r11: allocated
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r8: sh4 cntx
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r9: cycle counter
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fpu reg alloc
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d8:d15, single storage
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@ -119,7 +118,8 @@ static void storeSh4Reg(Register Rt, u32 Sh4_Reg)
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ass.Str(Rt, MemOperand(r8, shRegOffs));
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}
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const int alloc_regs[] = { 5, 6, 7, 10, 11, -1 };
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const int alloc_regs[] = { 5, 6, 7, 9, 10, 11, -1 };
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const int alloc_regs_mmu[] = { 5, 6, 7, 10, 11, -1 };
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const int alloc_fpu[] = { 16, 17, 18, 19, 20, 21, 22, 23,
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24, 25, 26, 27, 28, 29, 30, 31, -1 };
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@ -173,6 +173,8 @@ static const void *ngen_LinkBlock_cond_Next_stub;
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static void (*ngen_FailedToFindBlock_)();
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static void (*mainloop)(void *);
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static void (*handleException)();
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static void (*checkBlockFpu)();
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static void (*checkBlockNoFpu)();
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static void generate_mainloop();
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@ -1991,7 +1993,7 @@ void ngen_Compile(RuntimeBlockInfo* block, bool force_checks, bool reset, bool s
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block->code = (DynarecCodeEntryPtr)emit_GetCCPtr();
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//reg alloc
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reg.DoAlloc(block, alloc_regs, alloc_fpu);
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reg.DoAlloc(block, mmu_enabled() ? alloc_regs_mmu : alloc_regs, alloc_fpu);
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u8* blk_start = ass.GetCursorAddress<u8 *>();
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@ -2000,90 +2002,76 @@ void ngen_Compile(RuntimeBlockInfo* block, bool force_checks, bool reset, bool s
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reg.OpBegin(&block->oplist[0], 0);
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// block checks
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if (force_checks || mmu_enabled())
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if (mmu_enabled())
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{
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ass.Mov(r0, block->vaddr);
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ass.Mov(r1, block->addr);
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if (block->has_fpu_op)
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call((void *)checkBlockFpu);
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else
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call((void *)checkBlockNoFpu);
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}
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if (force_checks)
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{
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u32 addr = block->addr;
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ass.Mov(r0, addr);
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if (mmu_enabled())
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{
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loadSh4Reg(r2, reg_nextpc);
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ass.Mov(r1, block->vaddr);
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ass.Cmp(r2, r1);
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jump(ngen_blockcheckfail, ne);
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}
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if (force_checks)
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s32 sz = block->sh4_code_size;
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while (sz > 0)
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{
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s32 sz = block->sh4_code_size;
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while (sz > 0)
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if (sz > 2)
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{
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if (sz > 2)
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u32* ptr = (u32*)GetMemPtr(addr, 4);
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if (ptr != nullptr)
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{
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u32* ptr = (u32*)GetMemPtr(addr, 4);
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if (ptr != nullptr)
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{
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ass.Mov(r2, (u32)ptr);
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ass.Ldr(r2, MemOperand(r2));
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ass.Mov(r1, *ptr);
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ass.Cmp(r1, r2);
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ass.Mov(r2, (u32)ptr);
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ass.Ldr(r2, MemOperand(r2));
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ass.Mov(r1, *ptr);
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ass.Cmp(r1, r2);
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jump(ngen_blockcheckfail, ne);
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}
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addr += 4;
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sz -= 4;
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}
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else
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{
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u16* ptr = (u16 *)GetMemPtr(addr, 2);
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if (ptr != nullptr)
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{
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ass.Mov(r2, (u32)ptr);
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ass.Ldrh(r2, MemOperand(r2));
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ass.Mov(r1, *ptr);
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ass.Cmp(r1, r2);
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jump(ngen_blockcheckfail, ne);
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}
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addr += 2;
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sz -= 2;
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jump(ngen_blockcheckfail, ne);
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}
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addr += 4;
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sz -= 4;
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}
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}
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if (mmu_enabled() && block->has_fpu_op)
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{
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Label fpu_enabled;
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loadSh4Reg(r1, reg_sr_status);
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ass.Tst(r1, 1 << 15); // test SR.FD bit
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ass.B(eq, &fpu_enabled);
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else
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{
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u16* ptr = (u16 *)GetMemPtr(addr, 2);
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if (ptr != nullptr)
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{
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ass.Mov(r2, (u32)ptr);
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ass.Ldrh(r2, MemOperand(r2));
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ass.Mov(r1, *ptr);
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ass.Cmp(r1, r2);
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ass.Mov(r0, block->vaddr); // pc
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ass.Mov(r1, Sh4Ex_FpuDisabled);// exception code
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call((void *)Do_Exception);
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loadSh4Reg(r4, reg_nextpc);
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jump(no_update);
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ass.Bind(&fpu_enabled);
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jump(ngen_blockcheckfail, ne);
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}
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addr += 2;
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sz -= 2;
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}
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}
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}
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//scheduler
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u32 cyc = block->guest_cycles;
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if (!ImmediateA32::IsImmediateA32(cyc))
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cyc &= ~3;
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if (!mmu_enabled())
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ass.Ldr(r1, MemOperand(r8, rcbOffset(cntx.cycle_counter)));
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ass.Cmp(r1, 0);
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Label cyclesRemaining;
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ass.B(pl, &cyclesRemaining);
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ass.Mov(r0, block->vaddr);
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call(intc_sched);
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ass.Mov(r1, r0);
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ass.Bind(&cyclesRemaining);
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const u32 cycles = block->guest_cycles;
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if (!ImmediateA32::IsImmediateA32(cycles))
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{
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ass.Sub(SetFlags, r9, r9, cyc);
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ass.Sub(r1, r1, cycles & ~3);
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ass.Sub(r1, r1, cycles & 3);
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}
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else
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{
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ass.Ldr(r0, MemOperand(r8, rcbOffset(cntx.cycle_counter)));
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ass.Sub(SetFlags, r0, r0, cyc);
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ass.Str(r0, MemOperand(r8, rcbOffset(cntx.cycle_counter)));
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// FIXME condition?
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ass.Mov(r4, block->vaddr);
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storeSh4Reg(r4, reg_nextpc);
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ass.Sub(r1, r1, cycles);
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}
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call(intc_sched, le);
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ass.Str(r1, MemOperand(r8, rcbOffset(cntx.cycle_counter)));
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//compile the block's opcodes
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shil_opcode* op;
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@ -2229,8 +2217,6 @@ static void generate_mainloop()
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{
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// r8: context
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ass.Mov(r8, r0);
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// r9: cycle counter
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ass.Ldr(r9, MemOperand(r0, rcbOffset(cntx.cycle_counter)));
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}
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else
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{
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@ -2253,29 +2239,24 @@ static void generate_mainloop()
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// this code is here for fall-through behavior of do_iter
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Label do_iter;
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Label cleanup;
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// intc_sched:
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// intc_sched: r0 is pc, r1 is cycle_counter
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intc_sched = ass.GetCursorAddress<const void *>();
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if (!mmu_enabled())
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ass.Add(r9, r9, SH4_TIMESLICE);
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else
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{
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ass.Ldr(r0, MemOperand(r8, rcbOffset(cntx.cycle_counter)));
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ass.Add(r0, r0, SH4_TIMESLICE);
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ass.Str(r0, MemOperand(r8, rcbOffset(cntx.cycle_counter)));
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}
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ass.Mov(r4, lr);
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call((void *)UpdateSystem);
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ass.Mov(lr, r4);
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ass.Cmp(r0, 0);
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ass.B(ne, &do_iter);
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ass.Add(r1, r1, SH4_TIMESLICE);
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ass.Str(r1, MemOperand(r8, rcbOffset(cntx.cycle_counter)));
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ass.Str(r0, MemOperand(r8, rcbOffset(cntx.pc)));
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ass.Ldr(r0, MemOperand(r8, rcbOffset(cntx.CpuRunning)));
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ass.Cmp(r0, 0);
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ass.Bx(ne, lr);
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// do_iter:
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ass.B(eq, &cleanup);
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ass.Mov(r4, lr);
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call((void *)UpdateSystem_INTC);
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ass.Cmp(r0, 0);
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ass.B(ne, &do_iter);
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ass.Mov(lr, r4);
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ass.Ldr(r0, MemOperand(r8, rcbOffset(cntx.cycle_counter)));
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ass.Bx(lr);
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// do_iter:
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ass.Bind(&do_iter);
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ass.Mov(r0, r4);
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call((void *)rdv_DoInterrupts);
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ass.Mov(r4, r0);
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ass.Ldr(r4, MemOperand(r8, rcbOffset(cntx.pc)));
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// no_update:
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no_update = ass.GetCursorAddress<const void *>();
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@ -2303,8 +2284,6 @@ static void generate_mainloop()
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ass.Bind(&cleanup);
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if (mmu_enabled())
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ass.Add(sp, sp, 8); // pop context & alignment
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else
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ass.Str(r9, MemOperand(r8, rcbOffset(cntx.cycle_counter)));
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{
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UseScratchRegisterScope scope(&ass);
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scope.ExcludeAll();
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@ -2322,6 +2301,29 @@ static void generate_mainloop()
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ass.B(&longjumpLabel);
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}
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// MMU Check block (with fpu)
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// r0: vaddr, r1: addr
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checkBlockFpu = ass.GetCursorAddress<void (*)()>();
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Label fpu_enabled;
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loadSh4Reg(r2, reg_sr_status);
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ass.Tst(r2, 1 << 15); // test SR.FD bit
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ass.B(eq, &fpu_enabled);
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ass.Mov(r1, Sh4Ex_FpuDisabled); // exception code
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call((void *)Do_Exception);
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loadSh4Reg(r4, reg_nextpc);
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ass.B(&no_updateLabel);
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ass.Bind(&fpu_enabled);
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// fallthrough
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// MMU Check block (no fpu)
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// r0: vaddr, r1: addr
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checkBlockNoFpu = ass.GetCursorAddress<void (*)()>();
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loadSh4Reg(r2, reg_nextpc);
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ass.Cmp(r2, r0);
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ass.Mov(r0, r1);
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jump(ngen_blockcheckfail, ne);
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ass.Bx(lr);
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// Memory handlers
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for (int s=0;s<6;s++)
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{
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@ -62,6 +62,8 @@ struct DynaCode;
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static DynaCode *arm64_intc_sched;
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static DynaCode *arm64_no_update;
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static DynaCode *blockCheckFail;
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static DynaCode *checkBlockNoFpu;
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static DynaCode *checkBlockFpu;
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static DynaCode *linkBlockGenericStub;
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static DynaCode *linkBlockBranchStub;
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static DynaCode *linkBlockNextStub;
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@ -294,27 +296,18 @@ public:
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regalloc.DoAlloc(block);
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// scheduler
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if (mmu_enabled())
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{
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Ldr(w0, sh4_context_mem_operand(&Sh4cntx.cycle_counter));
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Subs(w0, w0, block->guest_cycles);
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Str(w0, sh4_context_mem_operand(&Sh4cntx.cycle_counter));
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}
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else
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{
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Subs(w27, w27, block->guest_cycles);
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}
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Ldr(w1, sh4_context_mem_operand(&Sh4cntx.cycle_counter));
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Cmp(w1, 0);
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Label cycles_remaining;
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B(&cycles_remaining, pl);
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Mov(w0, block->vaddr);
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GenCall(arm64_intc_sched);
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Label cpu_running;
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Cbnz(w0, &cpu_running);
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Mov(w29, block->vaddr);
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Str(w29, sh4_context_mem_operand(&next_pc));
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GenBranch(arm64_no_update);
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Bind(&cpu_running);
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Mov(w1, w0);
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Bind(&cycles_remaining);
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Sub(w1, w1, block->guest_cycles);
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Str(w1, sh4_context_mem_operand(&Sh4cntx.cycle_counter));
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for (size_t i = 0; i < block->oplist.size(); i++)
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{
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shil_opcode& op = block->oplist[i];
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@ -1359,7 +1352,7 @@ public:
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Label intc_sched;
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Label end_mainloop;
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// int intc_sched()
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// int intc_sched(int pc, int cycle_counter)
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arm64_intc_sched = GetCursorAddress<DynaCode *>();
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verify((void *)arm64_intc_sched == (void *)CodeCache);
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B(&intc_sched);
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@ -1461,8 +1454,6 @@ public:
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{
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// Use x28 as sh4 context pointer
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Mov(x28, x0);
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// Use x27 as cycle_counter
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Ldr(w27, sh4_context_mem_operand(&Sh4cntx.cycle_counter));
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}
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Label do_interrupts;
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@ -1470,40 +1461,29 @@ public:
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Ldr(w29, MemOperand(x28, offsetof(Sh4Context, pc)));
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B(&no_update);
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Bind(&intc_sched);
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Bind(&intc_sched); // w0 is pc, w1 is cycle_counter
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Str(w0, sh4_context_mem_operand(&Sh4cntx.pc));
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// Add timeslice to cycle counter
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if (!mmu_enabled())
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{
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Add(w27, w27, SH4_TIMESLICE);
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}
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else
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{
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Ldr(w0, sh4_context_mem_operand(&Sh4cntx.cycle_counter));
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Add(w0, w0, SH4_TIMESLICE);
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Str(w0, sh4_context_mem_operand(&Sh4cntx.cycle_counter));
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}
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Mov(x29, lr); // Trashing pc here but it will be reset at the end of the block or in DoInterrupts
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GenCallRuntime(UpdateSystem);
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Mov(lr, x29);
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Add(w1, w1, SH4_TIMESLICE);
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Str(w1, sh4_context_mem_operand(&Sh4cntx.cycle_counter));
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Ldr(w0, sh4_context_mem_operand(&Sh4cntx.CpuRunning));
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Cbz(w0, &end_mainloop);
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Mov(x29, lr); // Save link register in case we return
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GenCallRuntime(UpdateSystem_INTC);
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Cbnz(w0, &do_interrupts);
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Ldr(w0, MemOperand(x28, offsetof(Sh4Context, CpuRunning)));
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Mov(lr, x29);
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Ldr(w0, sh4_context_mem_operand(&Sh4cntx.cycle_counter));
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Ret();
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Bind(&do_interrupts);
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Mov(x0, x29);
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GenCallRuntime(rdv_DoInterrupts); // Updates next_pc based on host pc
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Mov(w29, w0);
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Ldr(w29, sh4_context_mem_operand(&Sh4cntx.pc));
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B(&no_update);
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Bind(&end_mainloop);
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if (mmu_enabled())
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// Pop context
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Add(sp, sp, 16);
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else
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// save cycle counter
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Str(w27, sh4_context_mem_operand(&Sh4cntx.cycle_counter));
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// Restore registers
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Ldp(x29, x30, MemOperand(sp, 144));
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Ldp(d12, d13, MemOperand(sp, 128));
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@ -1528,8 +1508,33 @@ public:
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B(&reenterLabel);
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}
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// MMU Block check (with fpu)
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// w0: vaddr, w1: addr
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checkBlockFpu = GetCursorAddress<DynaCode *>();
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Label fpu_enabled;
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Ldr(w10, sh4_context_mem_operand(&sr));
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Tbz(w10, 15, &fpu_enabled); // test SR.FD bit
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Mov(w1, Sh4Ex_FpuDisabled); // exception code
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GenCallRuntime(Do_Exception);
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Ldr(w29, sh4_context_mem_operand(&next_pc));
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B(&no_update);
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Bind(&fpu_enabled);
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// fallthrough
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Label blockCheckFailLabel;
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// MMU Block check (no fpu)
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// w0: vaddr, w1: addr
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checkBlockNoFpu = GetCursorAddress<DynaCode *>();
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Ldr(w2, sh4_context_mem_operand(&Sh4cntx.pc));
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Cmp(w2, w0);
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Mov(w0, w1);
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B(&blockCheckFailLabel, ne);
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Ret();
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// Block check fail
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blockCheckFail = GetCursorAddress<DynaCode *>();
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// w0: addr
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Bind(&blockCheckFailLabel);
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GenCallRuntime(rdv_BlockCheckFail);
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if (mmu_enabled())
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{
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@ -1588,6 +1593,7 @@ public:
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arm64_no_update = GetLabelAddress<DynaCode *>(&no_update);
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handleException = (void (*)())CC_RW2RX(GetLabelAddress<uintptr_t>(&handleExceptionLabel));
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blockCheckFail = GetLabelAddress<DynaCode *>(&blockCheckFailLabel);
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writeStoreQueue32 = GetLabelAddress<DynaCode *>(&writeStoreQueue32Label);
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writeStoreQueue64 = GetLabelAddress<DynaCode *>(&writeStoreQueue64Label);
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@ -2037,56 +2043,56 @@ private:
|
|||
|
||||
void CheckBlock(bool force_checks, RuntimeBlockInfo* block)
|
||||
{
|
||||
if (!mmu_enabled() && !force_checks)
|
||||
if (mmu_enabled())
|
||||
{
|
||||
Mov(w0, block->vaddr);
|
||||
Mov(w1, block->addr);
|
||||
if (block->has_fpu_op)
|
||||
GenCall(checkBlockFpu);
|
||||
else
|
||||
GenCall(checkBlockNoFpu);
|
||||
}
|
||||
|
||||
if (!force_checks)
|
||||
return;
|
||||
|
||||
Label blockcheck_fail;
|
||||
s32 sz = block->sh4_code_size;
|
||||
u8* ptr = GetMemPtr(block->addr, sz);
|
||||
if (ptr != NULL)
|
||||
{
|
||||
Ldr(x9, reinterpret_cast<uintptr_t>(ptr));
|
||||
|
||||
if (mmu_enabled())
|
||||
{
|
||||
Ldr(w10, sh4_context_mem_operand(&next_pc));
|
||||
Ldr(w11, block->vaddr);
|
||||
Cmp(w10, w11);
|
||||
B(ne, &blockcheck_fail);
|
||||
}
|
||||
if (force_checks)
|
||||
{
|
||||
s32 sz = block->sh4_code_size;
|
||||
u8* ptr = GetMemPtr(block->addr, sz);
|
||||
if (ptr != NULL)
|
||||
while (sz > 0)
|
||||
{
|
||||
Ldr(x9, reinterpret_cast<uintptr_t>(ptr));
|
||||
|
||||
while (sz > 0)
|
||||
if (sz >= 8)
|
||||
{
|
||||
if (sz >= 8)
|
||||
{
|
||||
Ldr(x10, MemOperand(x9, 8, PostIndex));
|
||||
Ldr(x11, *(u64*)ptr);
|
||||
Cmp(x10, x11);
|
||||
sz -= 8;
|
||||
ptr += 8;
|
||||
}
|
||||
else if (sz >= 4)
|
||||
{
|
||||
Ldr(w10, MemOperand(x9, 4, PostIndex));
|
||||
Ldr(w11, *(u32*)ptr);
|
||||
Cmp(w10, w11);
|
||||
sz -= 4;
|
||||
ptr += 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
Ldrh(w10, MemOperand(x9, 2, PostIndex));
|
||||
Mov(w11, *(u16*)ptr);
|
||||
Cmp(w10, w11);
|
||||
sz -= 2;
|
||||
ptr += 2;
|
||||
}
|
||||
B(ne, &blockcheck_fail);
|
||||
Ldr(x10, MemOperand(x9, 8, PostIndex));
|
||||
Ldr(x11, *(u64*)ptr);
|
||||
Cmp(x10, x11);
|
||||
sz -= 8;
|
||||
ptr += 8;
|
||||
}
|
||||
else if (sz >= 4)
|
||||
{
|
||||
Ldr(w10, MemOperand(x9, 4, PostIndex));
|
||||
Ldr(w11, *(u32*)ptr);
|
||||
Cmp(w10, w11);
|
||||
sz -= 4;
|
||||
ptr += 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
Ldrh(w10, MemOperand(x9, 2, PostIndex));
|
||||
Mov(w11, *(u16*)ptr);
|
||||
Cmp(w10, w11);
|
||||
sz -= 2;
|
||||
ptr += 2;
|
||||
}
|
||||
B(ne, &blockcheck_fail);
|
||||
}
|
||||
}
|
||||
|
||||
Label blockcheck_success;
|
||||
B(&blockcheck_success);
|
||||
Bind(&blockcheck_fail);
|
||||
|
|
@ -2094,21 +2100,6 @@ private:
|
|||
GenBranch(blockCheckFail);
|
||||
|
||||
Bind(&blockcheck_success);
|
||||
|
||||
if (mmu_enabled() && block->has_fpu_op)
|
||||
{
|
||||
Label fpu_enabled;
|
||||
Ldr(w10, sh4_context_mem_operand(&sr));
|
||||
Tbz(w10, 15, &fpu_enabled); // test SR.FD bit
|
||||
|
||||
Mov(w0, block->vaddr); // pc
|
||||
Mov(w1, Sh4Ex_FpuDisabled);// exception code
|
||||
CallRuntime(Do_Exception);
|
||||
Ldr(w29, sh4_context_mem_operand(&next_pc));
|
||||
GenBranch(arm64_no_update);
|
||||
|
||||
Bind(&fpu_enabled);
|
||||
}
|
||||
}
|
||||
|
||||
void shil_param_to_host_reg(const shil_param& param, const Register& reg)
|
||||
|
|
|
|||
|
|
@ -126,11 +126,13 @@ void X86Compiler::compile(RuntimeBlockInfo* block, bool force_checks, bool optim
|
|||
L(fpu_enabled);
|
||||
}
|
||||
|
||||
sub(dword[&Sh4cntx.cycle_counter], block->guest_cycles);
|
||||
mov(eax, dword[&Sh4cntx.cycle_counter]);
|
||||
test(eax, eax);
|
||||
Xbyak::Label no_up;
|
||||
jns(no_up);
|
||||
jg(no_up);
|
||||
call((const void *)intc_sched);
|
||||
L(no_up);
|
||||
sub(dword[&Sh4cntx.cycle_counter], block->guest_cycles);
|
||||
|
||||
regalloc.doAlloc(block);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue