aica: use log scale for attack phase
Change AEG starting envelope value from 3ff to 280 Use log scale instead of linear during attack phase
This commit is contained in:
Flyinghead
parent
0bd95cbba8
commit
08d7cc68fd
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@ -52,26 +52,43 @@ static const u32 SendLevel[16] =
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s32 tl_lut[256 + 768]; //xx.15 format. >=255 is muted
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//in ms :)
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static const double AEG_Attack_Time[]=
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static const double AEG_Attack_Time[64] =
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{
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-1,-1,8100.0,6900.0,6000.0,4800.0,4000.0,3400.0,3000.0,2400.0,2000.0,1700.0,1500.0,
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1200.0,1000.0,860.0,760.0,600.0,500.0,430.0,380.0,300.0,250.0,220.0,190.0,150.0,130.0,110.0,95.0,
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76.0,63.0,55.0,47.0,38.0,31.0,27.0,24.0,19.0,15.0,13.0,12.0,9.4,7.9,6.8,6.0,4.7,3.8,3.4,3.0,2.4,
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2.0,1.8,1.6,1.3,1.1,0.93,0.85,0.65,0.53,0.44,0.40,0.35,0.0,0.0
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};
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static const double AEG_DSR_Time[]=
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{ -1,-1,118200.0,101300.0,88600.0,70900.0,59100.0,50700.0,44300.0,35500.0,29600.0,25300.0,22200.0,17700.0,
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static const double AEG_DSR_Time[64] =
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{
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-1,-1,118200.0,101300.0,88600.0,70900.0,59100.0,50700.0,44300.0,35500.0,29600.0,25300.0,22200.0,17700.0,
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14800.0,12700.0,11100.0,8900.0,7400.0,6300.0,5500.0,4400.0,3700.0,3200.0,2800.0,2200.0,1800.0,1600.0,1400.0,1100.0,
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920.0,790.0,690.0,550.0,460.0,390.0,340.0,270.0,230.0,200.0,170.0,140.0,110.0,98.0,85.0,68.0,57.0,49.0,43.0,34.0,
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28.0,25.0,22.0,18.0,14.0,12.0,11.0,8.5,7.1,6.1,5.4,4.3,3.6,3.1
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};
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// These times come from the documentation but don't sound correct.
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// HT uses the AEG decay times instead and it sounds better.
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static const double FEG_Time[] =
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{
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-1, -1, 472800.0, 405200.0, 354400.0, 283600.0, 236400.0, 202800.0,
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177200.0, 142000.0, 118400.0, 101200.0, 88800.0, 70800.0, 59200.0, 50800.0,
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44400.0, 35600.0, 29600.0, 25200.0, 22000.0, 17600.0, 14800.0, 12800.0,
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11200.0, 8800.0, 7200.0, 6400.0, 5600.0, 4400.0, 3680.0, 3160.0,
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2760.0, 2220.0, 1840.0, 1560.0, 1360.0, 1080.0, 920.0, 800.0,
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680.0, 560.0, 440.0, 392.0, 340.0, 272.0, 228.0, 196.0,
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172.0, 158.0, 136.0, 100.0, 88.0, 72.0, 56.0, 48.0,
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44.0, 34.0, 28.0, 24.0, 22.0, 17.0, 14.0, 12.0
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};
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static const float PLFOS_Scale[8] = { 0.f, 3.61f, 7.22f, 14.44f, 28.88f, 57.75f, 115.5f, 231.f };
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static int PLFO_Scales[8][256];
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#define AEG_STEP_BITS (16)
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#define EG_STEP_BITS (16)
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#define AEG_ATTACK_SHIFT 16
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//Steps per sample
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u32 AEG_ATT_SPS[64];
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u32 AEG_DSR_SPS[64];
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u32 FEG_SPS[64];
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static const char* stream_names[]=
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{
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@ -364,8 +381,8 @@ struct ChannelEx
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struct
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{
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s32 val;
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__forceinline s32 GetValue() { return val>>AEG_STEP_BITS;}
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void SetValue(u32 aegb) { val=aegb<<AEG_STEP_BITS; }
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__forceinline s32 GetValue() { return val >> EG_STEP_BITS;}
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void SetValue(u32 aegb) { val = aegb << EG_STEP_BITS; }
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_EG_state state=EG_Attack;
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@ -379,8 +396,8 @@ struct ChannelEx
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struct
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{
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u32 value;
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__forceinline u32 GetValue() { return value >> AEG_STEP_BITS;}
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void SetValue(u32 fegb) { value = fegb << AEG_STEP_BITS; }
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__forceinline u32 GetValue() { return value >> EG_STEP_BITS;}
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void SetValue(u32 fegb) { value = fegb << EG_STEP_BITS; }
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_EG_state state = EG_Attack;
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@ -554,7 +571,7 @@ struct ChannelEx
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// reset AEG
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SetAegState(EG_Attack);
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AEG.SetValue(0x3FF);//start from 0x3FF ? .. it seems so !
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AEG.SetValue(0x280); // start value taken from HT
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//reset FEG
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SetFegState(EG_Attack);
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@ -621,19 +638,20 @@ struct ChannelEx
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loop.LEA=ccd->LEA;
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}
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u32 EG_BaseRate()
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s32 EG_BaseRate()
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{
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s32 rv=ccd->KRS+(ccd->FNS>>9);
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if (ccd->KRS==0xF)
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rv-=0xF;
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if (ccd->OCT&8)
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rv-=(16-ccd->OCT)*2;
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else
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rv+=ccd->OCT*2;
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return rv;
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s32 effrate = 0;
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if (ccd->KRS < 0xF)
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{
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effrate += (ccd->FNS >> 9) & 1;
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effrate += ccd->KRS * 2;
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effrate += (ccd->OCT ^ 8) - 8;
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}
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return effrate;
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}
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u32 EG_EffRate(u32 base_rate, u32 rate)
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u32 EG_EffRate(s32 base_rate, u32 rate)
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{
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s32 rv = base_rate + rate * 2;
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@ -740,10 +758,10 @@ struct ChannelEx
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ccd->FAR, ccd->FD1R, ccd->FD2R, ccd->FRR);
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FEG.q = qtable[ccd->Q];
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s32 base_rate = EG_BaseRate();
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FEG.AttackRate = AEG_DSR_SPS[EG_EffRate(base_rate, ccd->FAR)];
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FEG.Decay1Rate = AEG_DSR_SPS[EG_EffRate(base_rate, ccd->FD1R)];
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FEG.Decay2Rate = AEG_DSR_SPS[EG_EffRate(base_rate, ccd->FD2R)];
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FEG.ReleaseRate = AEG_DSR_SPS[EG_EffRate(base_rate, ccd->FRR)];
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FEG.AttackRate = FEG_SPS[EG_EffRate(base_rate, ccd->FAR)];
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FEG.Decay1Rate = FEG_SPS[EG_EffRate(base_rate, ccd->FD1R)];
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FEG.Decay2Rate = FEG_SPS[EG_EffRate(base_rate, ccd->FD2R)];
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FEG.ReleaseRate = FEG_SPS[EG_EffRate(base_rate, ccd->FRR)];
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}
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//WHEE :D!
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@ -842,13 +860,13 @@ struct ChannelEx
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}
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};
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__forceinline SampleType DecodeADPCM(u32 sample,s32 prev,s32& quant)
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static __forceinline SampleType DecodeADPCM(u32 sample,s32 prev,s32& quant)
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{
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s32 sign=1-2*(sample/8);
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u32 data=sample&7;
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/*(1 - 2 * L4) * (L3 + L2/2 +L1/4 + 1/8) * quantized width (ƒΆn) + decode value (Xn - 1) */
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/*(1 - 2 * L4) * (L3 + L2/2 +L1/4 + 1/8) * quantized width (Dn) + decode value (Xn - 1) */
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SampleType rv = (quant * adpcm_scale[data]) >> 3;
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if (rv > 0x7FFF)
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rv = 0x7FFF;
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@ -993,7 +1011,7 @@ void StreamStep(ChannelEx* ch)
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if (LPCTL == 0)
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ch->disable();
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else
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step_printf("[%d]LPCTL : Looping LSA %x LEA %x", ch->ChannelNumber, ch->loop.LSA, ch->loop.LEA);
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key_printf("[%d]LPCTL : Looping LSA %x LEA %x", ch->ChannelNumber, ch->loop.LSA, ch->loop.LEA);
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}
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ch->CA=CA;
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@ -1066,14 +1084,14 @@ void AegStep(ChannelEx* ch)
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switch(state)
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{
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case EG_Attack:
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if (ch->AEG.AttackRate != 0)
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{
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//wii
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ch->AEG.val-=ch->AEG.AttackRate;
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if (ch->AEG.GetValue()<=0)
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ch->AEG.val -= (((u64)ch->AEG.val << AEG_ATTACK_SHIFT) / ch->AEG.AttackRate) + 1;
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if (ch->AEG.GetValue() <= 0)
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{
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if (!ch->ccd->LPSLNK)
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{
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aeg_printf("[%d]AEG_step : Switching to EG_Decay1 %d", ch->ChannelNumber, ch->AEG.GetValue());
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aeg_printf("[%d]AEG_step : Switching to EG_Decay1", ch->ChannelNumber);
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ch->SetAegState(EG_Decay1);
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}
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ch->AEG.SetValue(0);
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@ -1081,38 +1099,29 @@ void AegStep(ChannelEx* ch)
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}
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break;
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case EG_Decay1:
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ch->AEG.val += ch->AEG.Decay1Rate;
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if (((u32)ch->AEG.GetValue()) >= ch->AEG.Decay2Value)
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{
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//x2
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ch->AEG.val+=ch->AEG.Decay1Rate;
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if (((u32)ch->AEG.GetValue())>=ch->AEG.Decay2Value)
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{
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aeg_printf("[%d]AEG_step : Switching to EG_Decay2 @ %x", ch->ChannelNumber, ch->AEG.GetValue());
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ch->SetAegState(EG_Decay2);
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}
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aeg_printf("[%d]AEG_step : Switching to EG_Decay2", ch->ChannelNumber);
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ch->SetAegState(EG_Decay2);
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}
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break;
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case EG_Decay2:
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ch->AEG.val += ch->AEG.Decay2Rate;
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if (ch->AEG.GetValue() >= 0x3FF)
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{
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//x3
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ch->AEG.val+=ch->AEG.Decay2Rate;
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if (ch->AEG.GetValue()>=0x3FF)
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{
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aeg_printf("[%d]AEG_step : Switching to EG_Release @ %x", ch->ChannelNumber, ch->AEG.GetValue());
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ch->AEG.SetValue(0x3FF);
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ch->SetAegState(EG_Release);
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}
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aeg_printf("[%d]AEG_step : Switching to EG_Release", ch->ChannelNumber);
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ch->AEG.SetValue(0x3FF);
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ch->SetAegState(EG_Release);
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}
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break;
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case EG_Release: //only on key_off ?
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case EG_Release: //only on key_off
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ch->AEG.val += ch->AEG.ReleaseRate;
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if (ch->AEG.GetValue() >= 0x3FF)
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{
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ch->AEG.val+=ch->AEG.ReleaseRate;
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if (ch->AEG.GetValue()>=0x3FF)
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{
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aeg_printf("[%d]AEG_step : EG_Release End @ %x", ch->ChannelNumber, ch->AEG.GetValue());
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ch->AEG.SetValue(0x3FF); // TODO: mnn, should we do anything about it running wild ?
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ch->disable(); // TODO: Is this ok here? It's a speed optimisation (since the channel is muted)
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}
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aeg_printf("[%d]AEG_step : EG_Release End @ %x", ch->ChannelNumber, ch->AEG.GetValue());
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ch->AEG.SetValue(0x3FF); // TODO: mnn, should we do anything about it running wild ?
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ch->disable(); // TODO: Is this ok here? It's a speed optimisation (since the channel is muted)
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}
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break;
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}
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@ -1143,7 +1152,7 @@ void FegStep(ChannelEx* ch)
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target = ch->ccd->FLV4;
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break;
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}
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target <<= AEG_STEP_BITS;
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target <<= EG_STEP_BITS;
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if (ch->FEG.value < target)
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{
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u32 maxd = target - ch->FEG.value;
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@ -1162,13 +1171,13 @@ void FegStep(ChannelEx* ch)
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{
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if (ch->FEG.state < EG_Decay2)
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{
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feg_printf("[%d]FEG_step : Switching to next state: %d Freq %x", ch->ChannelNumber, (int)ch->FEG.state + 1, target >> AEG_STEP_BITS);
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feg_printf("[%d]FEG_step : Switching to next state: %d Freq %x", ch->ChannelNumber, (int)ch->FEG.state + 1, target >> EG_STEP_BITS);
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ch->SetFegState((_EG_state)((int)ch->FEG.state + 1));
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}
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}
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}
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void staticinitialise()
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static void staticinitialise()
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{
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STREAM_STEP_LUT[0][0][0]=&StreamStep<0,0,0>;
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STREAM_STEP_LUT[1][0][0]=&StreamStep<1,0,0>;
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@ -1220,30 +1229,39 @@ void staticinitialise()
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PLFOWS_CALC[2]=&CalcPlfo<2>;
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PLFOWS_CALC[3]=&CalcPlfo<3>;
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}
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#define AicaChannel ChannelEx
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ChannelEx ChannelEx::Chans[64];
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AicaChannel AicaChannel::Chans[64];
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#define Chans ChannelEx::Chans
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#define Chans AicaChannel::Chans
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double dbToval(double db)
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static u32 CalcEgSteps(float t)
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{
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return pow(10,db/20.0);
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}
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u32 CalcAegSteps(float t)
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{
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const double aeg_allsteps=1024*(1<<AEG_STEP_BITS)-1;
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const double eg_allsteps = 1024 * (1 << EG_STEP_BITS) - 1;
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if (t<0)
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if (t < 0)
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return 0;
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if (t==0)
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return (u32)aeg_allsteps;
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if (t == 0)
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return (u32)eg_allsteps;
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//44.1*ms = samples
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double scnt=44.1*t;
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double steps=aeg_allsteps/scnt;
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double scnt = 44.1 * t;
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double steps = eg_allsteps / scnt;
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return (u32)lround(steps);
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}
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static u32 CalcAttackEgSteps(float t)
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{
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if (t < 0)
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return 0;
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if (t == 0)
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return 1 << AEG_ATTACK_SHIFT;
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//44.1*ms = samples
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double scnt = 44.1 * t;
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double factor = (1.0 / (1.0 - 1.0 / pow(0x280, 1.0 / scnt))) * (1 << AEG_ATTACK_SHIFT);
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return (u32)lround(factor);
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}
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void sgc_Init()
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{
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staticinitialise();
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@ -1266,8 +1284,10 @@ void sgc_Init()
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for (int i=0;i<64;i++)
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{
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AEG_ATT_SPS[i]=CalcAegSteps(AEG_Attack_Time[i]);
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AEG_DSR_SPS[i]=CalcAegSteps(AEG_DSR_Time[i]);
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AEG_ATT_SPS[i] = CalcAttackEgSteps(AEG_Attack_Time[i]);
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AEG_DSR_SPS[i]=CalcEgSteps(AEG_DSR_Time[i]);
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FEG_SPS[i] = CalcEgSteps(AEG_DSR_Time[i]);
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//FEG_SPS[i] = CalcEgSteps(FEG_Time[i]);
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}
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for (int i=0;i<64;i++)
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Chans[i].Init(i,aica_reg);
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@ -1345,8 +1365,6 @@ void WriteCommonReg8(u32 reg,u32 data)
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s16 cdda_sector[CDDA_SIZE]={0};
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u32 cdda_index=CDDA_SIZE<<1;
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u32 samples_gen;
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//no DSP for now in this version
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void AICA_Sample32()
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{
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@ -1381,9 +1399,6 @@ void AICA_Sample32()
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mxlr[i*2+1] += oRight;
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}
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}
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#ifdef _WIN32
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samples_gen += sg;
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#endif
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//OK , generated all Channels , now DSP/ect + final mix ;p
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//CDDA EXTS input
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