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dynarec: ssa missing changes

This commit is contained in:
Flyinghead 2019-06-04 21:27:45 +02:00
parent 681c423e66
commit 0890150dda
1 changed files with 90 additions and 54 deletions
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134
core/hw/sh4/dyna/shil.cpp
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@ -3,6 +3,8 @@
*/ */
#include <sstream> #include <sstream>
#include <set>
#include <math.h>
#include "types.h" #include "types.h"
#include "shil.h" #include "shil.h"
@ -488,11 +490,11 @@ void constprop(RuntimeBlockInfo* blk)
if (op->rs2.is_imm()) if (op->rs2.is_imm())
{ {
op->rs1.type=1; op->rs1.type = FMT_IMM;
op->rs1._imm= op->op==shop_add ? op->rs1._imm= op->op==shop_add ?
(rv[op->rs1._reg]+op->rs2._imm): (rv[op->rs1._reg]+op->rs2._imm):
(rv[op->rs1._reg]-op->rs2._imm); (rv[op->rs1._reg]-op->rs2._imm);
op->rs2.type=0; op->rs2.type = FMT_NULL;
printf("%s -> mov32!\n",op->op==shop_add?"shop_add":"shop_sub"); printf("%s -> mov32!\n",op->op==shop_add?"shop_add":"shop_sub");
op->op=shop_mov32; op->op=shop_mov32;
} }
@ -501,7 +503,7 @@ void constprop(RuntimeBlockInfo* blk)
{ {
u32 immy=rv[op->rs1._reg]; u32 immy=rv[op->rs1._reg];
op->rs1=op->rs2; op->rs1=op->rs2;
op->rs2.type=1; op->rs2.type = FMT_IMM;
op->rs2._imm=immy; op->rs2._imm=immy;
printf("%s -> imm prm (%08X)!\n",op->op==shop_add?"shop_add":"shop_sub",immy); printf("%s -> imm prm (%08X)!\n",op->op==shop_add?"shop_add":"shop_sub",immy);
} }
@ -523,7 +525,7 @@ void constprop(RuntimeBlockInfo* blk)
//NOT WORKING //NOT WORKING
//WE NEED PROPER PAGELOCKS //WE NEED PROPER PAGELOCKS
if (op->op==shop_readm && op->rs1.is_imm() && op->rd.is_r32i() && op->rd._reg<16 && op->flags==0x4 && op->rs3.is_null()) if (false && op->op==shop_readm && op->rs1.is_imm() && op->rd.is_r32i() && op->rd._reg<16 && op->flags==0x4 && op->rs3.is_null())
{ {
u32 baddr=blk->addr&0x0FFFFFFF; u32 baddr=blk->addr&0x0FFFFFFF;
@ -864,10 +866,34 @@ void srt_waw(RuntimeBlockInfo* blk)
} }
#include "hw/sh4/modules/ccn.h"
#include "ngen.h"
#include "hw/sh4/sh4_core.h"
#include "hw/sh4/sh4_mmr.h"
#define SHIL_MODE 1
#include "shil_canonical.h"
#define SHIL_MODE 4
#include "shil_canonical.h"
//#define SHIL_MODE 2
//#include "shil_canonical.h"
#if FEAT_SHREC != DYNAREC_NONE
#define SHIL_MODE 3
#include "shil_canonical.h"
#endif
#include "ssa.h"
//Simplistic Write after Write without read pass to remove (a few) dead opcodes //Simplistic Write after Write without read pass to remove (a few) dead opcodes
//Seems to be working //Seems to be working
void AnalyseBlock(RuntimeBlockInfo* blk) void AnalyseBlock(RuntimeBlockInfo* blk)
{ {
//SSAOptimizer optim(blk);
//optim.Optimize();
u32 st[sh4_reg_count]={0}; u32 st[sh4_reg_count]={0};
/* /*
@ -1000,47 +1026,68 @@ void AnalyseBlock(RuntimeBlockInfo* blk)
//printf("\nBlock: %d affecter regs %d c\n",affregs,blk->guest_cycles); //printf("\nBlock: %d affecter regs %d c\n",affregs,blk->guest_cycles);
} }
void UpdateFPSCR(); string name_reg(Sh4RegType reg)
bool UpdateSR();
#include "hw/sh4/modules/ccn.h"
#include "ngen.h"
#include "hw/sh4/sh4_core.h"
#include "hw/sh4/sh4_mmr.h"
#define SHIL_MODE 1
#include "shil_canonical.h"
#define SHIL_MODE 4
#include "shil_canonical.h"
//#define SHIL_MODE 2
//#include "shil_canonical.h"
#if FEAT_SHREC != DYNAREC_NONE
#define SHIL_MODE 3
#include "shil_canonical.h"
#endif
string name_reg(u32 reg)
{ {
stringstream ss; stringstream ss;
if (reg >= reg_fr_0 && reg <= reg_xf_15) if (reg >= reg_fr_0 && reg <= reg_xf_15)
ss << "f" << (reg-16); ss << "f" << (reg - reg_fr_0);
else if (reg <= reg_r15) else if (reg <= reg_r15)
ss << "r" << reg; ss << "r" << reg;
else if (reg == reg_sr_T) else if (reg <= reg_r7_Bank)
ss << "sr.T"; ss << "r" << (reg - reg_r0_Bank) << "b";
else if (reg == reg_fpscr)
ss << "fpscr";
else if (reg == reg_sr_status)
ss << "sr";
else else
{
switch (reg)
{
case reg_sr_T:
ss << "sr.T";
break;
case reg_fpscr:
ss << "fpscr";
break;
case reg_sr_status:
ss << "sr";
break;
case reg_pc_dyn:
ss << "pc_dyn";
break;
case reg_macl:
ss << "macl";
break;
case reg_mach:
ss << "mach";
break;
case reg_pr:
ss << "pr";
break;
case reg_gbr:
ss << "gbr";
break;
case reg_nextpc:
ss << "pc";
break;
case reg_fpul:
ss << "fpul";
break;
case reg_old_fpscr:
ss << "old_fpscr";
break;
case reg_old_sr_status:
ss << "old_sr_status";
break;
case reg_ssr:
ss << "ssr";
break;
default:
ss << "s" << reg; ss << "s" << reg;
break;
}
}
return ss.str(); return ss.str();
} }
string dissasm_param(const shil_param& prm, bool comma) string dissasm_param(const shil_param& prm, bool comma)
{ {
stringstream ss; stringstream ss;
@ -1057,33 +1104,22 @@ string dissasm_param(const shil_param& prm, bool comma)
} }
else if (prm.is_reg()) else if (prm.is_reg())
{ {
if (!prm.is_r32i()) ss << name_reg(prm._reg);
ss << "f" << (prm._reg-16);
else if (prm._reg<=reg_r15)
ss << "r" << prm._reg;
else if (prm._reg == reg_sr_T)
ss << "sr.T";
else if (prm._reg == reg_fpscr)
ss << "fpscr";
else if (prm._reg == reg_sr_status)
ss << "sr";
else
ss << "s" << prm._reg;
if (prm.count() > 1) if (prm.count() > 1)
{ {
ss << "v" << prm.count(); ss << "v" << prm.count();
} }
ss << "." << prm.version[0];
} }
return ss.str(); return ss.str();
} }
string shil_opcode::dissasm() string shil_opcode::dissasm() const
{ {
stringstream ss; stringstream ss;
ss << shilop_str[op] << " " << dissasm_param(rd,false) << dissasm_param(rd2,true) << " <= " << dissasm_param(rs1,false) << dissasm_param(rs2,true) << dissasm_param(rs3,true); ss << shilop_str[op] << " " << dissasm_param(rd,false) << dissasm_param(rd2,true) << " <- " << dissasm_param(rs1,false) << dissasm_param(rs2,true) << dissasm_param(rs3,true);
return ss.str(); return ss.str();
} }