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more types.h clean up. better aica handler templates

This commit is contained in:
Flyinghead 2022-04-15 17:03:49 +02:00
parent ed5c24c281
commit 039c666247
17 changed files with 241 additions and 266 deletions
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1
CMakeLists.txt
View File

@ -595,6 +595,7 @@ if(NOT LIBRETRO)
endif()
target_sources(${PROJECT_NAME} PRIVATE
core/hw/hwreg.h
core/hw/aica/aica.cpp
core/hw/aica/aica.h
core/hw/aica/aica_if.cpp

27
core/hw/aica/aica.cpp
View File

@ -135,7 +135,7 @@ static void AicaInternalDMA()
// to regs
u32 addr = CommonData->DRGA << 2;
for (u32 i = 0; i < CommonData->DLG; i++, addr += 4)
WriteMem_aica_reg(addr, 0, 4);
WriteMem_aica_reg(addr, (u32)0);
}
}
else
@ -148,13 +148,13 @@ static void AicaInternalDMA()
{
// reg to wave mem
for (u32 i = 0; i < len; i++, waddr += 4, raddr += 4)
*(u32*)&aica_ram[waddr] = ReadMem_aica_reg(raddr, 4);
*(u32*)&aica_ram[waddr] = ReadMem_aica_reg<u32>(raddr);
}
else
{
// wave mem to regs
for (u32 i = 0; i < len; i++, waddr += 4, raddr += 4)
WriteMem_aica_reg(raddr, *(u32*)&aica_ram[waddr], 4);
WriteMem_aica_reg(raddr, *(u32*)&aica_ram[waddr]);
}
}
CommonData->DEXE = 0;
@ -165,9 +165,10 @@ static void AicaInternalDMA()
}
//Memory i/o
template<u32 sz>
void WriteAicaReg(u32 reg,u32 data)
template<typename T>
void WriteAicaReg(u32 reg, T data)
{
constexpr size_t sz = sizeof(T);
switch (reg)
{
case SCIPD_addr:
@ -204,36 +205,34 @@ void WriteAicaReg(u32 reg,u32 data)
break;
case TIMER_A:
WriteMemArr<sz>(aica_reg, reg, data);
WriteMemArr(aica_reg, reg, data);
timers[0].RegisterWrite();
break;
case TIMER_B:
WriteMemArr<sz>(aica_reg, reg, data);
WriteMemArr(aica_reg, reg, data);
timers[1].RegisterWrite();
break;
case TIMER_C:
WriteMemArr<sz>(aica_reg, reg, data);
WriteMemArr(aica_reg, reg, data);
timers[2].RegisterWrite();
break;
// DEXE, DDIR, DLG
case 0x288C:
WriteMemArr<sz>(aica_reg, reg, data);
WriteMemArr(aica_reg, reg, data);
AicaInternalDMA();
break;
default:
WriteMemArr<sz>(aica_reg, reg, data);
WriteMemArr(aica_reg, reg, data);
break;
}
}
template void WriteAicaReg<1>(u32 reg,u32 data);
template void WriteAicaReg<2>(u32 reg,u32 data);
template void WriteAicaReg<>(u32 reg, u8 data);
template void WriteAicaReg<>(u32 reg, u16 data);
//misc :p
s32 libAICA_Init()

4
core/hw/aica/aica.h
View File

@ -303,8 +303,8 @@ extern InterruptInfo* SCIRE;
extern CommonData_struct* CommonData;
extern DSPData_struct* DSPData;
template<u32 sz>
void WriteAicaReg(u32 reg,u32 data);
template<typename T>
void WriteAicaReg(u32 reg, T data);
class AicaTimer
{

52
core/hw/aica/aica_if.cpp
View File

@ -45,23 +45,28 @@ u32 GetRTC_now()
return (20 * 365 + 5) * 24 * 60 * 60 + rawtime + time_offset;
}
u32 ReadMem_aica_rtc(u32 addr, u32 sz)
template<typename T>
T ReadMem_aica_rtc(u32 addr)
{
switch (addr & 0xFF)
{
case 0:
return RealTimeClock >> 16;
return (T)(RealTimeClock >> 16);
case 4:
return RealTimeClock & 0xFFFF;
return (T)(RealTimeClock & 0xFFFF);
case 8:
return 0;
}
WARN_LOG(AICA, "ReadMem_aica_rtc: invalid address %x sz %d", addr, sz);
WARN_LOG(AICA, "ReadMem_aica_rtc: invalid address %x sz %d", addr, (int)sizeof(T));
return 0;
}
template u8 ReadMem_aica_rtc<>(u32 addr);
template u16 ReadMem_aica_rtc<>(u32 addr);
template u32 ReadMem_aica_rtc<>(u32 addr);
void WriteMem_aica_rtc(u32 addr, u32 data, u32 sz)
template<typename T>
void WriteMem_aica_rtc(u32 addr, T data)
{
switch (addr & 0xFF)
{
@ -86,31 +91,41 @@ void WriteMem_aica_rtc(u32 addr, u32 data, u32 sz)
break;
default:
WARN_LOG(AICA, "WriteMem_aica_rtc: invalid address %x sz %d data %x", addr, sz, data);
WARN_LOG(AICA, "WriteMem_aica_rtc: invalid address %x sz %d data %x", addr, (int)sizeof(T), data);
break;
}
}
template void WriteMem_aica_rtc<>(u32 addr, u8 data);
template void WriteMem_aica_rtc<>(u32 addr, u16 data);
template void WriteMem_aica_rtc<>(u32 addr, u32 data);
u32 ReadMem_aica_reg(u32 addr, u32 sz)
template<typename T>
T ReadMem_aica_reg(u32 addr)
{
addr &= 0x7FFF;
if (sz == 1)
if (sizeof(T) == 1)
{
switch (addr)
{
case 0x2C00:
return ARMRST;
return (T)ARMRST;
case 0x2C01:
return VREG;
return (T)VREG;
default:
break;
}
}
else if (addr == 0x2C00)
return (VREG << 8) | ARMRST;
return (T)((VREG << 8) | ARMRST);
return libAICA_ReadReg(addr, sz);
if (sizeof(T) == 4)
return aicaReadReg<u16>(addr);
else
return aicaReadReg<T>(addr);
}
template u8 ReadMem_aica_reg<>(u32 addr);
template u16 ReadMem_aica_reg<>(u32 addr);
template u32 ReadMem_aica_reg<>(u32 addr);
static void ArmSetRST()
{
@ -118,11 +133,12 @@ static void ArmSetRST()
aicaarm::enable(ARMRST == 0);
}
void WriteMem_aica_reg(u32 addr,u32 data,u32 sz)
template<typename T>
void WriteMem_aica_reg(u32 addr, T data)
{
addr &= 0x7FFF;
if (sz == 1)
if (sizeof(T) == 1)
{
switch (addr)
{
@ -147,8 +163,14 @@ void WriteMem_aica_reg(u32 addr,u32 data,u32 sz)
ArmSetRST();
return;
}
libAICA_WriteReg(addr, data, sz);
if (sizeof(T) == 4)
aicaWriteReg(addr, (u16)data);
else
aicaWriteReg(addr, data);
}
template void WriteMem_aica_reg<>(u32 addr, u8 data);
template void WriteMem_aica_reg<>(u32 addr, u16 data);
template void WriteMem_aica_reg<>(u32 addr, u32 data);
static int DreamcastSecond(int tag, int c, int j)
{

8
core/hw/aica/aica_if.h
View File

@ -5,10 +5,10 @@
extern u32 VREG;
extern VArray2 aica_ram;
u32 GetRTC_now();
u32 ReadMem_aica_rtc(u32 addr,u32 sz);
void WriteMem_aica_rtc(u32 addr,u32 data,u32 sz);
u32 ReadMem_aica_reg(u32 addr,u32 sz);
void WriteMem_aica_reg(u32 addr,u32 data,u32 sz);
template<typename T> T ReadMem_aica_rtc(u32 addr);
template<typename T> void WriteMem_aica_rtc(u32 addr, T data);
template<typename T> T ReadMem_aica_reg(u32 addr);
template<typename T> void WriteMem_aica_reg(u32 addr, T data);
void aica_Init();
void aica_Reset(bool hard);

107
core/hw/aica/aica_mem.cpp
View File

@ -3,22 +3,26 @@
#include "aica_if.h"
#include "dsp.h"
#include "sgc_if.h"
#include "hw/hwreg.h"
alignas(4) u8 aica_reg[0x8000];
static void (*midiReceiver)(u8 data);
//Aica read/write (both sh4 & arm)
//00000000~007FFFFF @DRAM_AREA*
//00800000~008027FF @CHANNEL_DATA
//00802800~00802FFF @COMMON_DATA
//00803000~00807FFF @DSP_DATA
template<u32 sz>
u32 ReadReg(u32 addr)
template<typename T>
T aicaReadReg(u32 addr)
{
addr &= 0x7FFF;
if (addr >= 0x2800 && addr < 0x2818)
{
if (sz == 1)
ReadCommonReg(addr, true);
else
ReadCommonReg(addr, false);
ReadCommonReg(addr, sizeof(T) == 1);
}
else if (addr >= 0x4000 && addr < 0x4580)
{
@ -47,7 +51,7 @@ u32 ReadReg(u32 addr)
else
v &= 0xf;
}
if (sz == 1)
if (sizeof(T) == 1)
{
if (addr & 1)
v >>= 8;
@ -56,42 +60,54 @@ u32 ReadReg(u32 addr)
}
return v;
}
return ReadMemArr<sz>(aica_reg, addr);
return ReadMemArr<T>(aica_reg, addr);
}
template u8 aicaReadReg<u8>(u32 addr);
template u16 aicaReadReg<u16>(u32 addr);
static void writeCommonReg8(u32 reg, u8 data)
{
WriteMemArr(aica_reg, reg, data);
if (reg == 0x2804 || reg == 0x2805)
{
using namespace dsp;
state.RBL = (8192 << CommonData->RBL) - 1;
state.RBP = (CommonData->RBP * 2048) & ARAM_MASK;
state.dirty = true;
}
else if (reg == 0x280c) { // MOBUF
if (midiReceiver != nullptr)
midiReceiver(data);
}
}
template<u32 sz>
void WriteReg(u32 addr,u32 data)
template<typename T>
void aicaWriteReg(u32 addr, T data)
{
constexpr size_t sz = sizeof(T);
addr &= 0x7FFF;
if (addr < 0x2000)
{
//Channel data
u32 chan = addr >> 7;
u32 reg = addr & 0x7F;
WriteMemArr<sz>(aica_reg, addr, data);
WriteMemArr(aica_reg, addr, data);
WriteChannelReg(chan, reg, sz);
return;
}
if (addr < 0x2800)
{
if (sz == 1)
WriteMemArr<1>(aica_reg, addr, data);
else
WriteMemArr<2>(aica_reg, addr, data);
WriteMemArr(aica_reg, addr, data);
return;
}
if (addr < 0x2818)
{
if (sz == 1)
{
WriteCommonReg8(addr, data);
}
else
{
WriteCommonReg8(addr, data & 0xFF);
WriteCommonReg8(addr + 1, data >> 8);
}
writeCommonReg8(addr, data & 0xFF);
if (sz == 2)
writeCommonReg8(addr + 1, data >> 8);
return;
}
@ -128,7 +144,7 @@ void WriteReg(u32 addr,u32 data)
v = (v & ~0xff) | (data & 0xff);
// else ignored
}
DEBUG_LOG(AICA, "DSP TEMP/MEMS register write<%d> @ %x = %d", sz, addr, v);
DEBUG_LOG(AICA, "DSP TEMP/MEMS register write<%d> @ %x = %d", (int)sz, addr, v);
}
// DSP MIXS
else
@ -154,55 +170,34 @@ void WriteReg(u32 addr,u32 data)
v = (v & ~0xf) | (data & 0xf);
// else ignored
}
DEBUG_LOG(AICA, "DSP MIXS register write<%d> @ %x = %d", sz, addr, v);
DEBUG_LOG(AICA, "DSP MIXS register write<%d> @ %x = %d", (int)sz, addr, v);
}
return;
}
if (sz == 1)
{
WriteMemArr<1>(aica_reg, addr, data);
dsp::writeProg(addr);
}
else
{
WriteMemArr<2>(aica_reg, addr, data);
WriteMemArr(aica_reg, addr, data);
dsp::writeProg(addr);
if (sz == 2)
dsp::writeProg(addr + 1);
}
return;
}
if (sz == 1)
WriteAicaReg<1>(addr, data);
else
WriteAicaReg<2>(addr, data);
}
//Aica reads (both sh4&arm)
u32 libAICA_ReadReg(u32 addr, u32 size)
{
if (size == 1)
return ReadReg<1>(addr & 0x7FFF);
else
return ReadReg<2>(addr & 0x7FFF);
}
void libAICA_WriteReg(u32 addr, u32 data, u32 size)
{
if (size == 1)
WriteReg<1>(addr & 0x7FFF, data);
else
WriteReg<2>(addr & 0x7FFF, data);
WriteAicaReg(addr, data);
}
template void aicaWriteReg<>(u32 addr, u8 data);
template void aicaWriteReg<>(u32 addr, u16 data);
void init_mem()
{
memset(aica_reg, 0, sizeof(aica_reg));
aica_ram.data[ARAM_SIZE - 1] = 1;
aica_ram.Zero();
midiReceiver = nullptr;
}
void term_mem()
{
}
void aica_setMidiReceiver(void (*handler)(u8 data)) {
midiReceiver = handler;
}

4
core/hw/aica/aica_mem.h
View File

@ -1,8 +1,8 @@
#pragma once
#include "types.h"
u32 libAICA_ReadReg(u32 addr,u32 size);
void libAICA_WriteReg(u32 addr,u32 data,u32 size);
template<typename T> T aicaReadReg(u32 addr);
template<typename T> void aicaWriteReg(u32 addr, T data);
void init_mem();
void term_mem();

24
core/hw/aica/sgc_if.cpp
View File

@ -27,6 +27,7 @@
#include "hw/gdrom/gdrom_if.h"
#include "cfg/option.h"
#include "serialize.h"
#include "hw/hwreg.h"
#include <algorithm>
#include <cmath>
@ -127,8 +128,6 @@ static const s32 qtable[32] = {
0x1C00,0x1D00,0x1E00,0x1F00
};
static void (*midiReceiver)(u8 data);
//Remove the fractional part by chopping..
static SampleType FPs(SampleType a, int bits) {
return a >> bits;
@ -1321,7 +1320,6 @@ void sgc_Init()
beepCounter = 0;
dsp::init();
midiReceiver = nullptr;
}
void sgc_Term()
@ -1375,22 +1373,6 @@ void ReadCommonReg(u32 reg,bool byte)
}
}
void WriteCommonReg8(u32 reg,u32 data)
{
WriteMemArr<1>(aica_reg, reg, data);
if (reg == 0x2804 || reg == 0x2805)
{
using namespace dsp;
state.RBL = (8192 << CommonData->RBL) - 1;
state.RBP = (CommonData->RBP * 2048) & ARAM_MASK;
state.dirty = true;
}
else if (reg == 0x280c) { // MOBUF
if (midiReceiver != nullptr)
midiReceiver(data);
}
}
void vmuBeep(int on, int period)
{
if (on == 0 || period == 0 || on < period)
@ -1780,7 +1762,3 @@ void channel_deserialize(Deserializer& deser)
deser.skip(4); // samples_gen
}
}
void aica_setMidiReceiver(void (*handler)(u8 data)) {
midiReceiver = handler;
}

3
core/hw/aica/sgc_if.h
View File

@ -52,8 +52,7 @@ struct DSP_OUT_VOL_REG
typedef s32 SampleType;
void ReadCommonReg(u32 reg,bool byte);
void WriteCommonReg8(u32 reg,u32 data);
void ReadCommonReg(u32 reg, bool byte);
void channel_serialize(Serializer& ctx);
void channel_deserialize(Deserializer& ctx);
void vmuBeep(int on, int period);

38
core/hw/arm7/arm_mem.cpp
View File

@ -41,19 +41,22 @@ void e68k_AcceptInterrupt()
}
//Reg reads from arm side ..
template <u32 sz,class T>
template <typename T>
T arm_ReadReg(u32 addr)
{
addr&=0x7FFF;
if (addr==REG_L)
return e68k_reg_L;
else if(addr==REG_M)
return e68k_reg_M; //shouldn't really happen
addr &= 0x7FFF;
if (addr == REG_L)
return (T)e68k_reg_L;
else if (addr == REG_M)
return (T)e68k_reg_M; //shouldn't really happen
else if (sizeof(T) == 4)
return aicaReadReg<u16>(addr);
else
return libAICA_ReadReg(addr,sz);
return aicaReadReg<T>(addr);
}
template <u32 sz,class T>
void arm_WriteReg(u32 addr,T data)
template <typename T>
void arm_WriteReg(u32 addr, T data)
{
addr &= 0x7FFF;
if (addr == REG_L)
@ -68,7 +71,10 @@ void arm_WriteReg(u32 addr,T data)
}
else
{
return libAICA_WriteReg(addr, data, sz);
if (sizeof(T) == 4)
aicaWriteReg(addr, (u16)data);
else
aicaWriteReg(addr, data);
}
}
@ -77,10 +83,10 @@ void arm_WriteReg(u32 addr,T data)
//00802800~00802FFF @COMMON_DATA
//00803000~00807FFF @DSP_DATA
template u8 arm_ReadReg<1,u8>(u32 adr);
template u16 arm_ReadReg<2,u16>(u32 adr);
template u32 arm_ReadReg<4,u32>(u32 adr);
template u8 arm_ReadReg<u8>(u32 adr);
template u16 arm_ReadReg<u16>(u32 adr);
template u32 arm_ReadReg<u32>(u32 adr);
template void arm_WriteReg<1>(u32 adr,u8 data);
template void arm_WriteReg<2>(u32 adr,u16 data);
template void arm_WriteReg<4>(u32 adr,u32 data);
template void arm_WriteReg<>(u32 adr,u8 data);
template void arm_WriteReg<>(u32 adr,u16 data);
template void arm_WriteReg<>(u32 adr,u32 data);

46
core/hw/arm7/arm_mem.h
View File

@ -2,54 +2,52 @@
#include "types.h"
#include "hw/aica/aica_if.h"
template <u32 sz,class T>
T arm_ReadReg(u32 addr);
template <u32 sz,class T>
void arm_WriteReg(u32 addr,T data);
template <typename T> T arm_ReadReg(u32 addr);
template <typename T> void arm_WriteReg(u32 addr, T data);
template<int sz,typename T>
template<typename T>
static inline T DYNACALL ReadMemArm(u32 addr)
{
addr&=0x00FFFFFF;
if (addr<0x800000)
addr &= 0x00FFFFFF;
if (addr < 0x800000)
{
T rv=*(T*)&aica_ram[addr&(ARAM_MASK-(sz-1))];
T rv = *(T *)&aica_ram[addr & (ARAM_MASK - (sizeof(T) - 1))];
if (unlikely(sz==4 && addr&3))
if (unlikely(sizeof(T) == 4 && (addr & 3) != 0))
{
u32 sf=(addr&3)*8;
return (rv>>sf) | (rv<<(32-sf));
u32 sf = (addr & 3) * 8;
return (rv >> sf) | (rv << (32 - sf));
}
else
return rv;
}
else
{
return arm_ReadReg<sz,T>(addr);
return arm_ReadReg<T>(addr);
}
}
template<int sz,typename T>
static inline void DYNACALL WriteMemArm(u32 addr,T data)
template<typename T>
static inline void DYNACALL WriteMemArm(u32 addr, T data)
{
addr&=0x00FFFFFF;
if (addr<0x800000)
addr &= 0x00FFFFFF;
if (addr < 0x800000)
{
*(T*)&aica_ram[addr&(ARAM_MASK-(sz-1))]=data;
*(T *)&aica_ram[addr & (ARAM_MASK - (sizeof(T) - 1))] = data;
}
else
{
arm_WriteReg<sz,T>(addr,data);
arm_WriteReg(addr, data);
}
}
#define arm_ReadMem8 ReadMemArm<1,u8>
#define arm_ReadMem16 ReadMemArm<2,u16>
#define arm_ReadMem32 ReadMemArm<4,u32>
#define arm_ReadMem8 ReadMemArm<u8>
#define arm_ReadMem16 ReadMemArm<u16>
#define arm_ReadMem32 ReadMemArm<u32>
#define arm_WriteMem8 WriteMemArm<1,u8>
#define arm_WriteMem16 WriteMemArm<2,u16>
#define arm_WriteMem32 WriteMemArm<4,u32>
#define arm_WriteMem8 WriteMemArm<u8>
#define arm_WriteMem16 WriteMemArm<u16>
#define arm_WriteMem32 WriteMemArm<u32>
extern bool aica_interr;
extern u32 aica_reg_L;

1
core/hw/holly/sb.h
View File

@ -4,6 +4,7 @@
#pragma once
#include "types.h"
#include "hw/hwreg.h"
#include <array>
u32 sb_ReadMem(u32 addr,u32 sz);

12
core/hw/holly/sb_mem.cpp
View File

@ -337,10 +337,10 @@ T DYNACALL ReadMem_area0(u32 paddr)
}
// AICA sound registers
if (addr >= 0x00700000 && addr <= 0x00707FFF)
return (T)ReadMem_aica_reg(addr, sz);
return ReadMem_aica_reg<T>(addr);
// AICA RTC registers
if (addr >= 0x00710000 && addr <= 0x0071000B)
return (T)ReadMem_aica_rtc(addr, sz);
return ReadMem_aica_rtc<T>(addr);
break;
case 4:
@ -348,7 +348,7 @@ T DYNACALL ReadMem_area0(u32 paddr)
case 6:
case 7:
// AICA ram
return (T)ReadMemArr<sz>(aica_ram.data, addr & ARAM_MASK);
return ReadMemArr<T>(aica_ram.data, addr & ARAM_MASK);
default:
// G2 Ext area
@ -448,13 +448,13 @@ void DYNACALL WriteMem_area0(u32 paddr, T data)
// AICA sound registers
if (addr >= 0x00700000 && addr <= 0x00707FFF)
{
WriteMem_aica_reg(addr, data, sz);
WriteMem_aica_reg(addr, data);
return;
}
// AICA RTC registers
if (addr >= 0x00710000 && addr <= 0x0071000B)
{
WriteMem_aica_rtc(addr, data, sz);
WriteMem_aica_rtc(addr, data);
return;
}
break;
@ -463,7 +463,7 @@ void DYNACALL WriteMem_area0(u32 paddr, T data)
case 6:
case 7:
// AICA ram
WriteMemArr<sz>(aica_ram.data, addr & ARAM_MASK, data);
WriteMemArr(aica_ram.data, addr & ARAM_MASK, data);
return;
default:

71
core/hw/hwreg.h Normal file
View File

@ -0,0 +1,71 @@
#pragma once
#include "types.h"
typedef u32 RegReadAddrFP(u32 addr);
typedef void RegWriteAddrFP(u32 addr, u32 data);
/*
Read Write Const
D D N -> 0 -> RIO_DATA
D F N -> WF -> RIO_WF
F F N -> RF|WF -> RIO_FUNC
D X N -> RO|WF -> RIO_RO
F X N -> RF|WF|RO -> RIO_RO_FUNC
D X Y -> CONST|RO|WF-> RIO_CONST
X F N -> RF|WF|WO -> RIO_WO_FUNC
*/
enum RegStructFlags
{
REG_RF = 8,
REG_WF = 16,
REG_RO = 32,
REG_WO = 64,
REG_NO_ACCESS = REG_RO | REG_WO,
};
enum RegIO
{
RIO_DATA = 0,
RIO_WF = REG_WF,
RIO_FUNC = REG_WF | REG_RF,
RIO_RO = REG_RO | REG_WF,
RIO_RO_FUNC = REG_RO | REG_RF | REG_WF,
RIO_CONST = REG_RO | REG_WF,
RIO_WO_FUNC = REG_WF | REG_RF | REG_WO,
RIO_NO_ACCESS = REG_WF | REG_RF | REG_NO_ACCESS
};
struct RegisterStruct
{
union
{
u32 data32; //stores data of reg variable [if used] 32b
u16 data16; //stores data of reg variable [if used] 16b
u8 data8; //stores data of reg variable [if used] 8b
RegReadAddrFP* readFunctionAddr; //stored pointer to reg read function
};
RegWriteAddrFP* writeFunctionAddr; //stored pointer to reg write function
u32 flags; //Access flags !
void reset()
{
if (!(flags & (REG_RO | REG_RF)))
data32 = 0;
}
};
template<typename T>
T ReadMemArr(const u8 *array, u32 addr)
{
return *(const T *)&array[addr];
}
template<typename T>
void WriteMemArr(u8 *array, u32 addr, T data)
{
*(T *)&array[addr] = data;
}

1
core/hw/sh4/sh4_mmr.h
View File

@ -2,6 +2,7 @@
#include <array>
#include "types.h"
#include "sh4_if.h"
#include "hw/hwreg.h"
//For mem mapping
void map_area7_init();

8
core/reios/reios.cpp
View File

@ -427,10 +427,10 @@ static void setup_syscall(u32 hook_addr, u32 syscall_addr) {
static void reios_setup_state(u32 boot_addr)
{
// Set up AICA interrupt masks
libAICA_WriteReg(SCIEB_addr, 0x48, 2);
libAICA_WriteReg(SCILV0_addr, 0x18, 1);
libAICA_WriteReg(SCILV1_addr, 0x50, 1);
libAICA_WriteReg(SCILV2_addr, 0x08, 1);
aicaWriteReg(SCIEB_addr, (u16)0x48);
aicaWriteReg(SCILV0_addr, (u8)0x18);
aicaWriteReg(SCILV1_addr, (u8)0x50);
aicaWriteReg(SCILV2_addr, (u8)0x08);
/*
Post Boot registers from actual bios boot

96
core/types.h
View File

@ -207,65 +207,6 @@ void fatal_error(const char* text, ...);
#define verify(x) do { if ((x) == false){ fatal_error("Verify Failed : " #x "\n in %s -> %s : %d", (__FUNCTION__), (__FILE__), __LINE__); dbgbreak;}} while (false)
#define die(reason) do { fatal_error("Fatal error : %s\n in %s -> %s : %d", (reason), (__FUNCTION__), (__FILE__), __LINE__); dbgbreak;} while (false)
//will be removed sometime soon
//This shit needs to be moved to proper headers
typedef u32 RegReadAddrFP(u32 addr);
typedef void RegWriteAddrFP(u32 addr, u32 data);
/*
Read Write Const
D D N -> 0 -> RIO_DATA
D F N -> WF -> RIO_WF
F F N -> RF|WF -> RIO_FUNC
D X N -> RO|WF -> RIO_RO
F X N -> RF|WF|RO -> RIO_RO_FUNC
D X Y -> CONST|RO|WF-> RIO_CONST
X F N -> RF|WF|WO -> RIO_WO_FUNC
*/
enum RegStructFlags
{
REG_RF=8,
REG_WF=16,
REG_RO=32,
REG_WO=64,
REG_NO_ACCESS=REG_RO|REG_WO,
};
enum RegIO
{
RIO_DATA = 0,
RIO_WF = REG_WF,
RIO_FUNC = REG_WF | REG_RF,
RIO_RO = REG_RO | REG_WF,
RIO_RO_FUNC = REG_RO | REG_RF | REG_WF,
RIO_CONST = REG_RO | REG_WF,
RIO_WO_FUNC = REG_WF | REG_RF | REG_WO,
RIO_NO_ACCESS = REG_WF | REG_RF | REG_NO_ACCESS
};
struct RegisterStruct
{
union
{
u32 data32; //stores data of reg variable [if used] 32b
u16 data16; //stores data of reg variable [if used] 16b
u8 data8; //stores data of reg variable [if used] 8b
RegReadAddrFP* readFunctionAddr; //stored pointer to reg read function
};
RegWriteAddrFP* writeFunctionAddr; //stored pointer to reg write function
u32 flags; //Access flags !
void reset()
{
if (!(flags & (REG_RO | REG_RF)))
data32 = 0;
}
};
enum class JVS {
Default,
FourPlayers,
@ -404,43 +345,6 @@ extern settings_t settings;
#define VRAM_MASK settings.platform.vram_mask
#define BIOS_SIZE settings.platform.bios_size
template<u32 sz>
u32 ReadMemArr(const u8 *array, u32 addr)
{
switch(sz)
{
case 1:
return array[addr];
case 2:
return *(const u16 *)&array[addr];
case 4:
return *(const u32 *)&array[addr];
default:
die("invalid size");
return 0;
}
}
template<u32 sz>
void WriteMemArr(u8 *array, u32 addr, u32 data)
{
switch(sz)
{
case 1:
array[addr] = data;
break;
case 2:
*(u16 *)&array[addr] = data;
break;
case 4:
*(u32 *)&array[addr] = data;
break;
default:
die("invalid size");
break;
}
}
struct OnLoad
{
typedef void OnLoadFP();