420 lines
13 KiB
C++
420 lines
13 KiB
C++
/* FCE Ultra - NES/Famicom Emulator
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*
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* Copyright notice for this file:
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* Copyright (C) 2018 CaH4e3, Cluster
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* SMD132 and SMD133 ASICs, MMC3 clones that can address up to 32 MiB of PRG-ROM, 256 KiB of CHR-RAM, and 8 KiB of WRAM.
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*
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* COOLBOY cartridges use registers at address $6xxx
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* MINDKIDS cartridges use a solder pad labelled "5/6K" to select between $5000 and $6000
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*
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* $xxx0
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* 7 bit 0
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* ---- ----
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* ABCC DEEE
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* |||| ||||
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* |||| |+++-- PRG offset (PRG A19, A18, A17)
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* |||| +----- Alternate CHR A17
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* ||++------- PRG offset (PRG A24, A23)
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* |+--------- PRG mask (PRG A17 from 0: MMC3; 1: offset)
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* +---------- CHR mask (CHR A17 from 0: MMC3; 1: alternate)
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*
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* $xxx1
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*
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* 7 bit 0
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* ---- ----
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* GHIJ KKLx
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* |||| |||
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* |||| ||+--- GNROM mode bank PRG size (1: 32 KiB bank, PRG A14=CPU A14; 0: 16 KiB bank, PRG A14=offset A14)
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* |||+-++---- PRG offset (in order: PRG A20, A22, A21)
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* ||+-------- PRG mask (PRG A20 from 0: offset; 1: MMC3)
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* |+--------- PRG mask (PRG A19 from 0: offset; 1: MMC3)
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* +---------- PRG mask (PRG A18 from 0: MMC3; 1: offset)
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*
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* $xxx2
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* 7 bit 0
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* ---- ----
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* xxxx MMMM
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* ||||
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* ++++-- CHR offset for GNROM mode (CHR A16, A15, A14, A13)
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*
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* $xxx3
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* 7 bit 0
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* ---- ----
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* NPxP QQRx
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* || | |||
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* || | +++--- PRG offset for GNROM mode (PRG A16, A15, A14)
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* || +------- 1: GNROM mode; 0: MMC3 mode
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* || | (1: PRG A16...13 from QQ, L, R, CPU A14, A13 + CHR A16...10 from MMMM, PPU A12...10;
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* || | 0: PRG A16...13 from MMC3 + CHR A16...A10 from MMC3 )
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* |+-+------- Banking mode
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* |+--------- "Weird MMC3 mode"
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* +---------- Lockout (prevent further writes to these four registers, only works in MMC3 mode)
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*
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* Also some new cartridges from MINDKIDS have /WE and /OE pins connected to mapper,
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* which allows you to rewrite flash memory without soldering.
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* This also allows console to write data to the cartridge.
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* This behavior is not emulated.
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* No cart has been discovered so far that makes use of this feature, but this can be used for homebrew.
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*
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*/
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#include "mapinc.h"
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#include "mmc3.h"
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const int ROM_CHIP = 0x00;
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const int WRAM_CHIP = 0x10;
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const int CFI_CHIP = 0x11;
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const int FLASH_CHIP = 0x12;
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const int FLASH_SECTOR_SIZE = 128 * 1024;
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extern uint8* WRAM;
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static uint8* CFI = NULL;
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static uint8* Flash = NULL;
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static uint8 flash_save = 0;
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static uint8 flash_state = 0;
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static uint16 flash_buffer_a[10];
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static uint8 flash_buffer_v[10];
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static uint8 cfi_mode = 0;
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static uint8 flag23 = 0;
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// Macronix 256-mbit memory CFI data
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const uint8 cfi_data[] =
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{
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0x51, 0x52, 0x59, 0x02, 0x00, 0x40, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x27, 0x36, 0x00, 0x00, 0x03,
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0x06, 0x09, 0x13, 0x03, 0x05, 0x03, 0x02, 0x19,
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0x02, 0x00, 0x06, 0x00, 0x01, 0xFF, 0x00, 0x00,
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0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF,
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0x50, 0x52, 0x49, 0x31, 0x33, 0x14, 0x02, 0x01,
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0x00, 0x08, 0x00, 0x00, 0x02, 0x95, 0xA5, 0x05,
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0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
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};
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static void COOLBOYCW(uint32 A, uint8 V) {
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uint32 mask = 0xFF ^ (EXPREGS[0] & 0x80);
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if (EXPREGS[3] & 0x10) {
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if (EXPREGS[3] & 0x40) { // Weird mode
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int cbase = (MMC3_cmd & 0x80) << 5;
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switch (cbase ^ A) { // Don't even try do understand
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case 0x0400:
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case 0x0C00: V &= 0x7F; break;
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}
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}
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// Highest bit goes from MMC3 registers when EXPREGS[3]&0x80==0 or from EXPREGS[0]&0x08 otherwise
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setchr1(A,
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(V & 0x80 & mask) | ((((EXPREGS[0] & 0x08) << 4) & ~mask)) // 7th bit
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| ((EXPREGS[2] & 0x0F) << 3) // 6-3 bits
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| ((A >> 10) & 7) // 2-0 bits
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);
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}
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else {
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if (EXPREGS[3] & 0x40) { // Weird mode, again
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int cbase = (MMC3_cmd & 0x80) << 5;
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switch (cbase ^ A) { // Don't even try do understand
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case 0x0000: V = DRegBuf[0]; break;
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case 0x0800: V = DRegBuf[1]; break;
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case 0x0400:
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case 0x0C00: V = 0; break;
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}
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}
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// Simple MMC3 mode
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// Highest bit goes from MMC3 registers when EXPREGS[3]&0x80==0 or from EXPREGS[0]&0x08 otherwise
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setchr1(A, (V & mask) | (((EXPREGS[0] & 0x08) << 4) & ~mask));
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}
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}
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static void COOLBOYPW(uint32 A, uint8 V) {
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uint32 mask = ((0x3F | (EXPREGS[1] & 0x40) | ((EXPREGS[1] & 0x20) << 2)) ^ ((EXPREGS[0] & 0x40) >> 2)) ^ ((EXPREGS[1] & 0x80) >> 2);
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uint32 base = ((EXPREGS[0] & 0x07) >> 0) | ((EXPREGS[1] & 0x10) >> 1) | ((EXPREGS[1] & 0x0C) << 2) | ((EXPREGS[0] & 0x30) << 2);
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if (cfi_mode)
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{
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setprg32r(CFI_CHIP, 0x8000, 0);
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}
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int chip = !flash_save ? ROM_CHIP : FLASH_CHIP;
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// Very weird mode
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// Last banks are first in this mode, ignored when MMC3_cmd&0x40
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if ((EXPREGS[3] & 0x40) && (V >= 0xFE) && !((MMC3_cmd & 0x40) != 0)) {
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switch (A & 0xE000) {
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case 0xC000:
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case 0xE000:
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V = 0;
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break;
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}
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}
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if (!(EXPREGS[3] & 0x10)) {
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// Regular MMC3 mode but can be extended to 2MByte
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setprg8r(chip, A, (((base << 4) & ~mask)) | (V & mask));
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}
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else {
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// NROM mode
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mask &= 0xF0;
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uint8 emask;
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if ((((EXPREGS[1] & 2) != 0))) // 32kb mode
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emask = (EXPREGS[3] & 0x0C) | ((A & 0x4000) >> 13);
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else // 16kb mode
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emask = EXPREGS[3] & 0x0E;
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setprg8r(chip, A, ((base << 4) & ~mask) // 7-4 bits are from base (see below)
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| (V & mask) // ... or from MM3 internal regs, depends on mask
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| emask // 3-1 (or 3-2 when (EXPREGS[3]&0x0C is set) from EXPREGS[3]
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| ((A & 0x2000) >> 13)); // 0th just as is
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}
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}
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static void Submapper23Flip() {
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EXPREGS[1] = (EXPREGS[1] & 0b11100000) | ((EXPREGS[1] & 0b11100) >> 1) | (((EXPREGS[1] & 0b10) ^ 0b10) << 3);
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}
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static DECLFW(COOLBOYWrite) {
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if (A001B & 0x80)
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CartBW(A, V);
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// Deny any further writes when 7th bit is 1 AND 4th is 0
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if ((EXPREGS[3] & 0x90) != 0x80) {
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EXPREGS[A & 3] = V;
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if (flag23 && (A & 3) == 1) Submapper23Flip();
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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}
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}
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static DECLFW(MINDKIDSWrite) {
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if (A >= 0x6000) {
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if (A001B & 0x80)
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CartBW(A, V);
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return;
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}
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// Deny any further writes when 7th bit is 1 AND 4th is 0
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if ((EXPREGS[3] & 0x90) != 0x80) {
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EXPREGS[A & 3] = V;
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if (flag23 && (A & 3) == 1) Submapper23Flip();
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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}
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}
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static DECLFR(COOLBOYFlashRead) {
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return CartBR(A);
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}
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static DECLFW(COOLBOYFlashWrite) {
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if (A < 0xC000)
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MMC3_CMDWrite(A, V);
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else
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MMC3_IRQWrite(A, V);
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if (flash_save) {
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if (flash_state < sizeof(flash_buffer_a) / sizeof(flash_buffer_a[0])) {
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flash_buffer_a[flash_state] = A & 0xFFF;
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flash_buffer_v[flash_state] = V;
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flash_state++;
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// enter CFI mode
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if ((flash_state == 1) &&
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(flash_buffer_a[0] == 0x0AAA) && (flash_buffer_v[0] == 0x98)) {
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cfi_mode = 1;
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flash_state = 0;
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FixMMC3PRG(MMC3_cmd);
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}
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// erase sector
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if ((flash_state == 6) &&
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(flash_buffer_a[0] == 0x0AAA) && (flash_buffer_v[0] == 0xAA) &&
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(flash_buffer_a[1] == 0x0555) && (flash_buffer_v[1] == 0x55) &&
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(flash_buffer_a[2] == 0x0AAA) && (flash_buffer_v[2] == 0x80) &&
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(flash_buffer_a[3] == 0x0AAA) && (flash_buffer_v[3] == 0xAA) &&
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(flash_buffer_a[4] == 0x0555) && (flash_buffer_v[4] == 0x55) &&
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(flash_buffer_v[5] == 0x30)) {
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int offset = &Page[A >> 11][A] - Flash;
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int sector = offset / FLASH_SECTOR_SIZE;
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for (uint32 i = sector * FLASH_SECTOR_SIZE; i < (sector + 1) * FLASH_SECTOR_SIZE; i++)
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Flash[i % PRGsize[ROM_CHIP]] = 0xFF;
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FCEU_printf("Flash sector #%d is erased (0x%08x - 0x%08x)\n", sector, offset, offset + FLASH_SECTOR_SIZE);
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}
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// erase chip, lol
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if ((flash_state == 6) &&
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(flash_buffer_a[0] == 0x0AAA) && (flash_buffer_v[0] == 0xAA) &&
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(flash_buffer_a[1] == 0x0555) && (flash_buffer_v[1] == 0x55) &&
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(flash_buffer_a[2] == 0x0AAA) && (flash_buffer_v[2] == 0x80) &&
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(flash_buffer_a[3] == 0x0AAA) && (flash_buffer_v[3] == 0xAA) &&
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(flash_buffer_a[4] == 0x0555) && (flash_buffer_v[4] == 0x55) &&
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(flash_buffer_v[5] == 0x10)) {
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memset(Flash, 0xFF, PRGsize[ROM_CHIP]);
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FCEU_printf("Flash chip erased.\n");
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}
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// write byte
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if ((flash_state == 4) &&
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(flash_buffer_a[0] == 0x0AAA) && (flash_buffer_v[0] == 0xAA) &&
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(flash_buffer_a[1] == 0x0555) && (flash_buffer_v[1] == 0x55) &&
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(flash_buffer_a[2] == 0x0AAA) && (flash_buffer_v[2] == 0xA0)) {
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int offset = &Page[A >> 11][A] - Flash;
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if (CartBR(A) != 0xFF) {
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FCEU_PrintError("Error: can't write to 0x%08x, flash sector is not erased\n", offset);
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}
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else {
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CartBW(A, V);
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}
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flash_state = 0;
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}
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}
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// not a command
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if (((A & 0xFFF) != 0x0AAA) && ((A & 0xFFF) != 0x0555)) {
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flash_state = 0;
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}
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// reset
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if (V == 0xF0) {
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flash_state = 0;
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cfi_mode = 0;
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FixMMC3PRG(MMC3_cmd);
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}
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}
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}
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static void CommonReset(void) {
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MMC3RegReset();
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EXPREGS[0] = EXPREGS[1] = EXPREGS[2] = EXPREGS[3] = 0;
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flash_state = 0;
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cfi_mode = 0;
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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}
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static void COOLBOYPower(void) {
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GenMMC3Power();
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EXPREGS[0] = EXPREGS[1] = EXPREGS[2] = EXPREGS[3] = 0;
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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SetWriteHandler(0x5000, 0x5fff, CartBW); // some games access random unmapped areas and crashes because of KT-008 PCB hack in MMC3 source lol
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SetWriteHandler(0x6000, 0x6fff, COOLBOYWrite);
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SetWriteHandler(0x8000, 0xFFFF, COOLBOYFlashWrite);
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SetReadHandler(0x8000, 0xFFFF, COOLBOYFlashRead);
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}
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static void MINDKIDSPower(void) {
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GenMMC3Power();
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EXPREGS[0] = EXPREGS[1] = EXPREGS[2] = EXPREGS[3] = 0;
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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SetWriteHandler(0x5000, 0x7fff, MINDKIDSWrite);
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SetWriteHandler(0x8000, 0xFFFF, COOLBOYFlashWrite);
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SetReadHandler(0x8000, 0xFFFF, COOLBOYFlashRead);
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}
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static void CommonClose(void) {
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if (WRAM)
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FCEU_gfree(WRAM);
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if (Flash)
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FCEU_gfree(Flash);
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if (CFI)
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FCEU_gfree(CFI);
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WRAM = Flash = CFI = NULL;
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}
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void CommonInit(CartInfo* info, int submapper)
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{
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GenMMC3_Init(info, 2048, info->vram_size / 1024, !info->ines2 ? 8 : (info->wram_size + info->battery_wram_size) / 1024, info->battery);
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pwrap = COOLBOYPW;
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cwrap = COOLBOYCW;
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switch (submapper)
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{
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case 0:
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info->Power = COOLBOYPower;
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break;
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case 1:
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info->Power = MINDKIDSPower;
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break;
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case 2:
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info->Power = COOLBOYPower;
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flag23 = 1;
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break;
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case 3:
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info->Power = MINDKIDSPower;
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flag23 = 1;
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break;
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default:
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FCEU_PrintError("Submapper #%d is not supported", submapper);
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}
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info->Reset = CommonReset;
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info->Close = CommonClose;
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flash_save = info->battery;
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if (flash_save) {
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CFI = (uint8*)FCEU_gmalloc(sizeof(cfi_data) * 2);
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for (int i = 0; i < sizeof(cfi_data); i++) {
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CFI[i * 2] = CFI[i * 2 + 1] = cfi_data[i];
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}
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SetupCartPRGMapping(CFI_CHIP, CFI, sizeof(cfi_data) * 2, 0);
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Flash = (uint8*)FCEU_gmalloc(PRGsize[ROM_CHIP]);
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for (int i = 0; i < PRGsize[ROM_CHIP]; i++) {
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Flash[i] = PRGptr[ROM_CHIP][i % PRGsize[ROM_CHIP]];
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}
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SetupCartPRGMapping(FLASH_CHIP, Flash, PRGsize[ROM_CHIP], 1);
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info->SaveGame[1] = Flash;
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info->SaveGameLen[1] = PRGsize[ROM_CHIP];
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}
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AddExState(EXPREGS, 4, 0, "EXPR");
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if (flash_save)
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{
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AddExState(&flash_state, sizeof(flash_state), 0, "FLST");
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AddExState(flash_buffer_a, sizeof(flash_buffer_a), 0, "FLBA");
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AddExState(flash_buffer_v, sizeof(flash_buffer_v), 0, "FLBV");
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AddExState(&cfi_mode, sizeof(cfi_mode), 0, "CFIM");
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AddExState(Flash, PRGsize[ROM_CHIP], 0, "FLAS");
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}
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}
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// Registers at $6xxx
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void COOLBOY_Init(CartInfo* info) {
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CommonInit(info, 0);
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}
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// Registers at $5xxx
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void MINDKIDS_Init(CartInfo* info) {
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CommonInit(info, 1);
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}
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// For NES 2.0 loader
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void SMD132_SMD133_Init(CartInfo* info) {
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CommonInit(info, info->submapper);
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}
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