Mapper 342 memory optimization
This commit is contained in:
Alexey 'Cluster' Avdyukhin
parent
201cb50d89
commit
f8b8e93eaf
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@ -103,13 +103,11 @@ const uint32 FLASH_SECTOR_SIZE = 128 * 1024;
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const int ROM_CHIP = 0x00;
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const int WRAM_CHIP = 0x10;
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const int FLASH_CHIP = 0x11;
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const int CHR_RAM_CHIP = 0x12;
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const int CFI_CHIP = 0x13;
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static int CHR_SIZE = 0;
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static uint32 WRAM_SIZE = 0;
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static uint8 *WRAM = NULL;
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static uint32 CHR_RAM_SIZE = 0;
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static uint8 *CHR_RAM;
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static uint8 *SAVE_FLASH = NULL;
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static uint8* CFI;
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@ -388,75 +386,75 @@ static void COOLGIRL_Sync_CHR(void) {
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int chr_shift_left = 0;
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// enable or disable writes to CHR RAM, setup CHR mask
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SetupCartCHRMapping(CHR_RAM_CHIP, CHR_RAM, ((((~(chr_mask >> 13) & 0x3F) + 1) * 0x2000 - 1) & (CHR_RAM_SIZE - 1)) + 1, can_write_chr);
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SetupCartCHRMapping(0, UNIFchrrama, ((((~(chr_mask >> 13) & 0x3F) + 1) * 0x2000 - 1) & (CHR_SIZE - 1)) + 1, can_write_chr);
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switch (chr_mode & 7)
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{
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default:
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case 0:
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setchr8r(0x12, chr_bank_a >> 3 >> chr_shift_right << chr_shift_left);
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setchr8(chr_bank_a >> 3 >> chr_shift_right << chr_shift_left);
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break;
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case 1:
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setchr4r(0x12, 0x0000, mapper_163_latch >> chr_shift_right << chr_shift_left);
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setchr4r(0x12, 0x1000, mapper_163_latch >> chr_shift_right << chr_shift_left);
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setchr4(0x0000, mapper_163_latch >> chr_shift_right << chr_shift_left);
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setchr4(0x1000, mapper_163_latch >> chr_shift_right << chr_shift_left);
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break;
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case 2:
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setchr2r(0x12, 0x0000, chr_bank_a >> 1 >> chr_shift_right << chr_shift_left);
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setchr2(0x0000, chr_bank_a >> 1 >> chr_shift_right << chr_shift_left);
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TKSMIR[0] = TKSMIR[1] = chr_bank_a;
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setchr2r(0x12, 0x0800, chr_bank_c >> 1 >> chr_shift_right << chr_shift_left);
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setchr2(0x0800, chr_bank_c >> 1 >> chr_shift_right << chr_shift_left);
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TKSMIR[2] = TKSMIR[3] = chr_bank_c;
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setchr1r(0x12, 0x1000, chr_bank_e >> chr_shift_right << chr_shift_left);
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setchr1(0x1000, chr_bank_e >> chr_shift_right << chr_shift_left);
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TKSMIR[4] = chr_bank_e;
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setchr1r(0x12, 0x1400, chr_bank_f >> chr_shift_right << chr_shift_left);
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setchr1(0x1400, chr_bank_f >> chr_shift_right << chr_shift_left);
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TKSMIR[5] = chr_bank_f;
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setchr1r(0x12, 0x1800, chr_bank_g >> chr_shift_right << chr_shift_left);
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setchr1(0x1800, chr_bank_g >> chr_shift_right << chr_shift_left);
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TKSMIR[6] = chr_bank_g;
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setchr1r(0x12, 0x1C00, chr_bank_h >> chr_shift_right << chr_shift_left);
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setchr1(0x1C00, chr_bank_h >> chr_shift_right << chr_shift_left);
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TKSMIR[7] = chr_bank_h;
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break;
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case 3:
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setchr1r(0x12, 0x0000, chr_bank_e >> chr_shift_right << chr_shift_left);
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setchr1(0x0000, chr_bank_e >> chr_shift_right << chr_shift_left);
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TKSMIR[0] = chr_bank_e;
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setchr1r(0x12, 0x0400, chr_bank_f >> chr_shift_right << chr_shift_left);
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setchr1(0x0400, chr_bank_f >> chr_shift_right << chr_shift_left);
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TKSMIR[1] = chr_bank_f;
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setchr1r(0x12, 0x0800, chr_bank_g >> chr_shift_right << chr_shift_left);
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setchr1(0x0800, chr_bank_g >> chr_shift_right << chr_shift_left);
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TKSMIR[2] = chr_bank_g;
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setchr1r(0x12, 0x0C00, chr_bank_h >> chr_shift_right << chr_shift_left);
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setchr1(0x0C00, chr_bank_h >> chr_shift_right << chr_shift_left);
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TKSMIR[3] = chr_bank_h;
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setchr2r(0x12, 0x1000, chr_bank_a >> 1 >> chr_shift_right << chr_shift_left);
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setchr2(0x1000, chr_bank_a >> 1 >> chr_shift_right << chr_shift_left);
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TKSMIR[4] = TKSMIR[5] = chr_bank_a;
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setchr2r(0x12, 0x1800, chr_bank_c >> 1 >> chr_shift_right << chr_shift_left);
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setchr2(0x1800, chr_bank_c >> 1 >> chr_shift_right << chr_shift_left);
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TKSMIR[6] = TKSMIR[7] = chr_bank_c;
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break;
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case 4:
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setchr4r(0x12, 0x0000, chr_bank_a >> 2 >> chr_shift_right << chr_shift_left);
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setchr4r(0x12, 0x1000, chr_bank_e >> 2 >> chr_shift_right << chr_shift_left);
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setchr4(0x0000, chr_bank_a >> 2 >> chr_shift_right << chr_shift_left);
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setchr4(0x1000, chr_bank_e >> 2 >> chr_shift_right << chr_shift_left);
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break;
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case 5:
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if (!ppu_latch0)
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setchr4r(0x12, 0x0000, chr_bank_a >> 2 >> chr_shift_right << chr_shift_left);
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setchr4(0x0000, chr_bank_a >> 2 >> chr_shift_right << chr_shift_left);
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else
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setchr4r(0x12, 0x0000, chr_bank_b >> 2 >> chr_shift_right << chr_shift_left);
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setchr4(0x0000, chr_bank_b >> 2 >> chr_shift_right << chr_shift_left);
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if (!ppu_latch1)
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setchr4r(0x12, 0x1000, chr_bank_e >> 2 >> chr_shift_right << chr_shift_left);
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setchr4(0x1000, chr_bank_e >> 2 >> chr_shift_right << chr_shift_left);
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else
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setchr4r(0x12, 0x1000, chr_bank_f >> 2 >> chr_shift_right << chr_shift_left);
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setchr4(0x1000, chr_bank_f >> 2 >> chr_shift_right << chr_shift_left);
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break;
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case 6:
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setchr2r(0x12, 0x0000, chr_bank_a >> 1 >> chr_shift_right << chr_shift_left);
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setchr2r(0x12, 0x0800, chr_bank_c >> 1 >> chr_shift_right << chr_shift_left);
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setchr2r(0x12, 0x1000, chr_bank_e >> 1 >> chr_shift_right << chr_shift_left);
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setchr2r(0x12, 0x1800, chr_bank_g >> 1 >> chr_shift_right << chr_shift_left);
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setchr2(0x0000, chr_bank_a >> 1 >> chr_shift_right << chr_shift_left);
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setchr2(0x0800, chr_bank_c >> 1 >> chr_shift_right << chr_shift_left);
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setchr2(0x1000, chr_bank_e >> 1 >> chr_shift_right << chr_shift_left);
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setchr2(0x1800, chr_bank_g >> 1 >> chr_shift_right << chr_shift_left);
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break;
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case 7:
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setchr1r(0x12, 0x0000, chr_bank_a >> chr_shift_right << chr_shift_left);
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setchr1r(0x12, 0x0400, chr_bank_b >> chr_shift_right << chr_shift_left);
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setchr1r(0x12, 0x0800, chr_bank_c >> chr_shift_right << chr_shift_left);
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setchr1r(0x12, 0x0C00, chr_bank_d >> chr_shift_right << chr_shift_left);
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setchr1r(0x12, 0x1000, chr_bank_e >> chr_shift_right << chr_shift_left);
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setchr1r(0x12, 0x1400, chr_bank_f >> chr_shift_right << chr_shift_left);
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setchr1r(0x12, 0x1800, chr_bank_g >> chr_shift_right << chr_shift_left);
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setchr1r(0x12, 0x1C00, chr_bank_h >> chr_shift_right << chr_shift_left);
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setchr1(0x0000, chr_bank_a >> chr_shift_right << chr_shift_left);
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setchr1(0x0400, chr_bank_b >> chr_shift_right << chr_shift_left);
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setchr1(0x0800, chr_bank_c >> chr_shift_right << chr_shift_left);
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setchr1(0x0C00, chr_bank_d >> chr_shift_right << chr_shift_left);
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setchr1(0x1000, chr_bank_e >> chr_shift_right << chr_shift_left);
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setchr1(0x1400, chr_bank_f >> chr_shift_right << chr_shift_left);
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setchr1(0x1800, chr_bank_g >> chr_shift_right << chr_shift_left);
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setchr1(0x1C00, chr_bank_h >> chr_shift_right << chr_shift_left);
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break;
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}
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}
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@ -468,10 +466,10 @@ static void COOLGIRL_Sync_Mirroring(void) {
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setmirror((mirroring < 2) ? (mirroring ^ 1) : mirroring);
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}
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else { // four screen mode
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vnapage[0] = CHR_RAM + 0x3F000;
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vnapage[1] = CHR_RAM + 0x3F400;
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vnapage[2] = CHR_RAM + 0x3F800;
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vnapage[3] = CHR_RAM + 0x3FC00;
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vnapage[0] = UNIFchrrama + 0x3F000;
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vnapage[1] = UNIFchrrama + 0x3F400;
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vnapage[2] = UNIFchrrama + 0x3F800;
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vnapage[3] = UNIFchrrama + 0x3FC00;
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}
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}
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@ -2238,15 +2236,13 @@ static void COOLGIRL_Power(void) {
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}
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static void COOLGIRL_Close(void) {
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if (CHR_RAM)
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FCEU_gfree(CHR_RAM);
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if (WRAM)
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FCEU_gfree(WRAM);
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if (SAVE_FLASH)
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FCEU_gfree(SAVE_FLASH);
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if (CFI)
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FCEU_gfree(CFI);
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CHR_RAM = WRAM = SAVE_FLASH = CFI = NULL;
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WRAM = SAVE_FLASH = CFI = NULL;
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}
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static void COOLGIRL_Restore(int version) {
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@ -2257,11 +2253,7 @@ static void COOLGIRL_Restore(int version) {
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#define ExState(var, varname) AddExState(&var, sizeof(var), 0, varname)
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void COOLGIRL_Init(CartInfo *info) {
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CHR_RAM_SIZE = info->ines2 ? (info->vram_size + info->battery_vram_size) : (512 * 1024);
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CHR_RAM = (uint8*)FCEU_gmalloc(CHR_RAM_SIZE);
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memset(CHR_RAM, 0, CHR_RAM_SIZE);
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SetupCartCHRMapping(CHR_RAM_CHIP, CHR_RAM, CHR_RAM_SIZE, 0);
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AddExState(CHR_RAM, sizeof(CHR_RAM_SIZE), 0, "CHR_");
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CHR_SIZE = info->vram_size ? info->vram_size /* NES 2.0 */ : 256 * 1024 /* UNIF, fixed */;
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WRAM_SIZE = info->ines2 ? (info->wram_size + info->battery_wram_size) : (32 * 1024);
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if (WRAM_SIZE > 0) {
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@ -475,7 +475,7 @@ static BMAPPING bmap[] = {
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{ "FNS", FNS_Init, BMCFLAG_16KCHRR },
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{ "BS-400R", BS400R_Init, 0 },
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{ "BS-4040R", BS4040R_Init, 0 },
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{ "COOLGIRL", COOLGIRL_Init, 0 },
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{ "COOLGIRL", COOLGIRL_Init, BMCFLAG_256KCHRR },
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{ "JC-016-2", Mapper205_Init, 0 },
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{ 0, 0, 0 }
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