Mapper 268, submappers 8,9
This commit is contained in:
Alexey 'Cluster' Avdyukhin
parent
a70bc4c72c
commit
b6bf83db7f
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@ -55,15 +55,16 @@
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* $xxx3
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* 7 bit 0
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* ---- ----
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* NPxP QQRx
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* || | |||
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* || | +++--- PRG offset for GNROM mode (PRG A16, A15, A14)
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* || +------- 1: GNROM mode; 0: MMC3 mode
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* || | (1: PRG A16...13 from QQ, L, R, CPU A14, A13 + CHR A16...10 from MMMM, PPU A12...10;
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* || | 0: PRG A16...13 from MMC3 + CHR A16...A10 from MMC3 )
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* NPZP QQRx
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* |||| |||
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* |||| +++--- PRG offset for GNROM mode (PRG A16, A15, A14)
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* |||+------- 1: GNROM mode; 0: MMC3 mode
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* |||| (1: PRG A16...13 from QQ, L, R, CPU A14, A13 + CHR A16...10 from MMMM, PPU A12...10;
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* |||| 0: PRG A16...13 from MMC3 + CHR A16...A10 from MMC3 )
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* ||+-------- 1: Also enable PRG RAM in $5000-$5FFF
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* |+-+------- Banking mode
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* |+--------- "Weird MMC3 mode"
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* +---------- Lockout (prevent further writes to these four registers, only works in MMC3 mode)
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* +---------- Lockout (prevent further writes to all registers but the one at $xxx2, only works in MMC3 mode)
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*
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* Also some new cartridges from MINDKIDS have /WE and /OE pins connected to mapper,
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* which allows you to rewrite flash memory without soldering.
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@ -95,6 +96,7 @@ static uint8 cfi_mode = 0;
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static uint8 flag23 = 0;
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static uint8 flag45 = 0;
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static uint8 flag89 = 0;
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// Macronix 256-mbit memory CFI data
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const uint8 cfi_data[] =
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@ -118,9 +120,9 @@ const uint8 cfi_data[] =
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};
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static void COOLBOYCW(uint32 A, uint8 V) {
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uint32 mask = 0xFF ^ (EXPREGS[0] & 0x80);
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if (EXPREGS[3] & 0x10) {
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if (EXPREGS[3] & 0x40) { // Weird mode
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uint32 mask = 0xFF ^ (EXPREGS[0] & 0b10000000);
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if (EXPREGS[3] & 0b00010000) {
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if (EXPREGS[3] & 0b01000000) { // Weird mode
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int cbase = (MMC3_cmd & 0x80) << 5;
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switch (cbase ^ A) { // Don't even try do understand
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case 0x0400:
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@ -129,13 +131,13 @@ static void COOLBOYCW(uint32 A, uint8 V) {
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}
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// Highest bit goes from MMC3 registers when EXPREGS[0]&0x80==0 or from EXPREGS[0]&0x08 otherwise
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setchr1(A,
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(V & 0x80 & mask) | ((((EXPREGS[0] & 0x08) << 4) & ~mask)) // 7th bit
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(V & 0x80 & mask) | ((((EXPREGS[0] & 0b00001000) << 4) & ~mask)) // 7th bit
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| ((EXPREGS[2] & 0x0F) << 3) // 6-3 bits
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| ((A >> 10) & 7) // 2-0 bits
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);
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}
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else {
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if (EXPREGS[3] & 0x40) { // Weird mode, again
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if (EXPREGS[3] & 0b01000000) { // Weird mode, again
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int cbase = (MMC3_cmd & 0x80) << 5;
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switch (cbase ^ A) { // Don't even try do understand
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case 0x0000: V = DRegBuf[0]; break;
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@ -152,16 +154,72 @@ static void COOLBOYCW(uint32 A, uint8 V) {
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static void COOLBOYPW(uint32 A, uint8 V) {
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uint8 CREGS[] = {EXPREGS[0], EXPREGS[1], EXPREGS[2], EXPREGS[3]};
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// Submappers has scrambled bits
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if (flag23) {
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CREGS[1] = (CREGS[1] & 0b11100000) | ((CREGS[1] & 0b11100) >> 1) | (((CREGS[1] & 0b10) ^ 0b10) << 3);
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/*
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$xxx1
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7 bit 0
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---- ----
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GHIL JKKx
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|||| |||
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|||| +++--- PRG offset (in order: PRG A20, A22, A21)
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|||+------- GNROM mode bank PRG size (0: 32 KiB bank, PRG A14=CPU A14; 1: 16 KiB bank, PRG A14=offset A14)
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||+-------- PRG mask (PRG A20 from 0: offset; 1: MMC3)
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|+--------- PRG mask (PRG A19 from 0: offset; 1: MMC3)
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+---------- PRG mask (PRG A18 from 0: MMC3; 1: offset)
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*/
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CREGS[1] = (CREGS[1] & 0b11100000)
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| ((CREGS[1] & 0b00001110) << 1) // PRG A20, A22, A21
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| (((CREGS[1] & 0b00010000) ^ 0b00010000) >> 3); // GNROM mode bank PRG size
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}
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if (flag45) {
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CREGS[1] = (CREGS[1] & 0b11101011) | ((CREGS[0] & 0b00100000) >> 3) | (CREGS[0] & 0b00010000);
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CREGS[0] &= 0b11001111;
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/*
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$xxx0
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7 bit 0
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---- ----
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ABCC DEEE
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|||| ||||
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|||| |+++-- PRG offset (PRG A19, A18, A17)
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|||| +----- Alternate CHR A17
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||++------- PRG offset (PRG A21, A20)
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|+--------- PRG mask (PRG A17 from 0: MMC3; 1: offset)
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+---------- CHR mask (CHR A17 from 0: MMC3; 1: alternate)
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$xxx1
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7 bit 0
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---- ----
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GHIx xxLx
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||| |
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||| +--- GNROM mode bank PRG size (1: 32 KiB bank, PRG A14=CPU A14; 0: 16 KiB bank, PRG A14=offset A14)
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||+-------- PRG mask (PRG A20 from 0: offset; 1: MMC3)
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|+--------- PRG mask (PRG A19 from 0: offset; 1: MMC3)
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+---------- PRG mask (PRG A18 from 0: MMC3; 1: offset)
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*/
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CREGS[1] = (CREGS[1] & 0b11101011)
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| ((CREGS[0] & 0b00100000) >> 3) // PRG A21
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| (CREGS[0] & 0b00010000); // PRG A20
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}
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if (flag89) {
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/*
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$xxx1
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7 bit 0
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---- ----
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GHIL JKKx
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|||| |||
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|||| +++--- PRG offset (in order: A20, A21, A22)
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|||+------- GNROM mode bank PRG size (0: 32 KiB bank, PRG A14=CPU A14; 1: 16 KiB bank, PRG A14=offset A14)
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||+-------- PRG mask (PRG A20 from 0: offset; 1: MMC3)
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|+--------- PRG mask (PRG A19 from 0: offset; 1: MMC3)
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+---------- PRG mask (PRG A18 from 0: MMC3; 1: offset)
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*/
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CREGS[1] = (CREGS[1] & 0b11100101)
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| ((CREGS[1] & 0b00001000) << 1) // PRG A20
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| ((CREGS[1] & 0b00000010) << 2) // PRG A22
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| ((((CREGS[1] ^ 0b00010000) & 0b00010000) >> 3)); // GNROM mode bank PRG size
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}
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uint32 mask = ((0x3F | (CREGS[1] & 0x40) | ((CREGS[1] & 0x20) << 2)) ^ ((CREGS[0] & 0x40) >> 2)) ^ ((CREGS[1] & 0x80) >> 2);
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uint32 base = ((CREGS[0] & 0x07) >> 0) | ((CREGS[1] & 0x10) >> 1) | ((CREGS[1] & 0x0C) << 2) | ((CREGS[0] & 0x30) << 2);
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uint32 mask = ((0b00111111 | (CREGS[1] & 0b01000000) | ((CREGS[1] & 0b00100000) << 2)) ^ ((CREGS[0] & 0b01000000) >> 2)) ^ ((CREGS[1] & 0b10000000) >> 2);
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uint32 base = ((CREGS[0] & 0b00000111) >> 0) | ((CREGS[1] & 0b00010000) >> 1) | ((CREGS[1] & 0b00001100) << 2) | ((CREGS[0] & 0b00110000) << 2);
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FCEU_printf("mask=%04x base=%04x r0=%02x r1=%02x r2=%02x r3=%02x\n", mask, base, CREGS[0], CREGS[1], CREGS[2], CREGS[3]);
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if (flash_save && cfi_mode) {
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setprg32r(CFI_CHIP, 0x8000, 0);
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@ -172,7 +230,7 @@ static void COOLBOYPW(uint32 A, uint8 V) {
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// Very weird mode
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// Last banks are first in this mode, ignored when MMC3_cmd&0x40
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if ((CREGS[3] & 0x40) && (V >= 0xFE) && !((MMC3_cmd & 0x40) != 0)) {
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if ((CREGS[3] & 0b01000000) && (V >= 0xFE) && !((MMC3_cmd & 0x40) != 0)) {
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switch (A & 0xE000) {
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case 0xC000:
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case 0xE000:
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@ -189,11 +247,11 @@ static void COOLBOYPW(uint32 A, uint8 V) {
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// NROM mode
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mask &= 0xF0;
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uint8 emask;
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if ((((CREGS[1] & 2) != 0))) // 32kb mode
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emask = (CREGS[3] & 0x0C) | ((A & 0x4000) >> 13);
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if (CREGS[1] & 0b00000010) // 32kb mode
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emask = (CREGS[3] & 0b00001100) | ((A & 0x4000) >> 13);
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else // 16kb mode
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emask = CREGS[3] & 0x0E;
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setprg8r(chip, A, ((base << 4) & ~mask) // 7-4 bits are from base (see below)
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emask = CREGS[3] & 0b00001110;
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setprg8r(chip, A, ((base << 4) & ~mask) // 7-4 bits are from base
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| (V & mask) // ... or from MM3 internal regs, depends on mask
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| emask // 3-1 (or 3-2 when (EXPREGS[3]&0x0C is set) from EXPREGS[3]
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| ((A & 0x2000) >> 13)); // 0th just as is
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@ -207,10 +265,10 @@ static DECLFW(COOLBOYWrite) {
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// Deny any further writes when 7th bit is 1 AND 4th is 0
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if ((EXPREGS[3] & 0x90) != 0x80) {
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EXPREGS[A & 3] = V;
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}
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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}
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}
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static DECLFW(MINDKIDSWrite) {
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if (A >= 0x6000) {
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@ -222,10 +280,10 @@ static DECLFW(MINDKIDSWrite) {
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// Deny any further writes when 7th bit is 1 AND 4th is 0
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if ((EXPREGS[3] & 0x90) != 0x80) {
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EXPREGS[A & 3] = V;
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}
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FixMMC3PRG(MMC3_cmd);
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FixMMC3CHR(MMC3_cmd);
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}
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}
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static DECLFR(COOLBOYFlashRead) {
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return CartBR(A);
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@ -359,38 +417,23 @@ void CommonInit(CartInfo* info, int submapper)
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switch (submapper)
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{
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case 0:
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case 2:
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case 4:
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case 8:
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info->Power = COOLBOYPower;
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flag23 = 0;
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flag45 = 0;
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break;
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case 1:
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info->Power = MINDKIDSPower;
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flag23 = 0;
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flag45 = 0;
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break;
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case 2:
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info->Power = COOLBOYPower;
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flag23 = 1;
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flag45 = 0;
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break;
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case 3:
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info->Power = MINDKIDSPower;
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flag23 = 1;
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flag45 = 0;
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break;
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case 4:
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info->Power = COOLBOYPower;
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flag23 = 0;
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flag45 = 1;
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break;
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case 5:
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case 9:
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info->Power = MINDKIDSPower;
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flag23 = 0;
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flag45 = 1;
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break;
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default:
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FCEU_PrintError("Submapper #%d is not supported", submapper);
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}
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flag23 = (submapper == 2) || (submapper == 3);
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flag45 = (submapper == 4) || (submapper == 5);
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flag89 = (submapper == 8) || (submapper == 9);
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info->Reset = CommonReset;
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info->Close = CommonClose;
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