fix vrc3 irq handling
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5f898848e6
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@ -20,41 +20,96 @@
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#include "mapinc.h"
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static uint8 IRQx; //autoenable
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static uint8 IRQm; //mode
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static uint16 IRQr; //reload
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static DECLFW(Mapper73_write)
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{
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//if(A>=0xd000 && A<=0xdfff)
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X6502_IRQEnd(FCEU_IQEXT); /* How are IRQs acknowledged on this chip? */
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//printf("$%04x:$%02x\n",A,V);
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switch(A&0xF000)
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{
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//default: printf("$%04x:$%02x\n",A,V);break;
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case 0x8000:IRQCount&=0xFFF0;IRQCount|=(V&0xF);break;
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case 0x9000:IRQCount&=0xFF0F;IRQCount|=(V&0xF)<<4;break;
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case 0xa000:IRQCount&=0xF0FF;IRQCount|=(V&0xF)<<8;break;
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case 0xb000:IRQCount&=0x0FFF;IRQCount|=(V&0xF)<<12;break;
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case 0xc000:IRQa=V&2;break;
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case 0x8000:
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IRQr&=0xFFF0;IRQr|=(V&0xF);
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break;
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case 0x9000:
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IRQr&=0xFF0F;IRQr|=(V&0xF)<<4;
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break;
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case 0xa000:
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IRQr&=0xF0FF;IRQr|=(V&0xF)<<8;
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break;
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case 0xb000:
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IRQr&=0x0FFF;IRQr|=(V&0xF)<<12;
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break;
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case 0xc000:
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IRQm=V&4;
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IRQx=V&1;
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IRQa=V&2;
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if(IRQa)
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{
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if(IRQm)
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{
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IRQCount&=0xFFFF;
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IRQCount|=(IRQr&0xFF);
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}
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else
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{
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IRQCount=IRQr;
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}
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}
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X6502_IRQEnd(FCEU_IQEXT);
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break;
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case 0xd000:
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X6502_IRQEnd(FCEU_IQEXT);
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IRQa=IRQx;
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break;
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case 0xf000:ROM_BANK16(0x8000,V);break;
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}
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}
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static void Mapper73IRQHook(int a)
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{
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if(IRQa)
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{
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IRQCount+=a;
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if(IRQCount>=0xFFFF)
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{
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IRQCount&=0xFFFF;
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IRQa=0;
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X6502_IRQBegin(FCEU_IQEXT);
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}
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}
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for(int i=0;i<a;i++)
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{
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if(!IRQa) return;
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if(IRQm)
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{
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uint16 temp = IRQCount;
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temp &= 0xFF;
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IRQCount &= 0xFF00;
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if (temp == 0xFF)
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{
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IRQCount = IRQr;
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IRQCount |= (uint16)(IRQr & 0xFF);
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X6502_IRQBegin(FCEU_IQEXT);
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}
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else
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{
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temp++;
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IRQCount |= temp;
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}
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}
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else
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{
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//16 bit mode
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if (IRQCount == 0xFFFF)
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{
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IRQCount = IRQr;
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X6502_IRQBegin(FCEU_IQEXT);
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}
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else
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IRQCount++;
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}
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}
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}
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void Mapper73_init(void)
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{
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SetWriteHandler(0x8000,0xffff,Mapper73_write);
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MapIRQHook=Mapper73IRQHook;
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IRQr = IRQm = IRQx = 0;
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}
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