diff --git a/download.html b/download.html index 207e2bc8..3002e481 100644 --- a/download.html +++ b/download.html @@ -77,8 +77,8 @@

Download

The latest win32 interim build is generally fresh within a day or two. If you are working with a developer to fix an issue affecting you then this is where you will find your fixed build.

@@ -101,6 +101,11 @@ Win32 BinarySRCDeb Binary + + FCEUX2.1.3 + FCEUX2.1.3 + + FCEUX2.1.2 FCEUX2.1.2 diff --git a/files/{022DC721-5306-4E84-93DC-7DA111D7752C}.htm b/files/{022DC721-5306-4E84-93DC-7DA111D7752C}.htm index 442f5ca5..2b8b6f27 100644 --- a/files/{022DC721-5306-4E84-93DC-7DA111D7752C}.htm +++ b/files/{022DC721-5306-4E84-93DC-7DA111D7752C}.htm @@ -80,24 +80,31 @@ a.rvts12, span.rvts12 text-decoration: underline; } a.rvts12:hover { color: #0000ff; } -span.rvts13 /* Font Style */ +a.rvts13, span.rvts13 +{ + font-size: 12pt; + color: #0000ff; + text-decoration: underline; +} +a.rvts13:hover { color: #0000ff; } +span.rvts14 /* Font Style */ { font-size: 16pt; font-family: 'Tahoma', 'Geneva', sans-serif; color: #ffffff; } -span.rvts14 /* Font Style */ +span.rvts15 /* Font Style */ { font-family: 'MS Sans Serif', 'Geneva', sans-serif; color: #808080; } -span.rvts15 /* Font Style */ +span.rvts16 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; color: #c0c0c0; } -a.rvts16, span.rvts16 /* Font Style */ +a.rvts17, span.rvts17 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; @@ -144,11 +151,15 @@ p,ul,ol /* Paragraph Style */ -

FAQ / Guides

+

FAQ / Guides

FAQ / Guides


Information regarding various concepts such as TAS, ROM Hacking, RAM Mapping.


+

Troubleshooting FAQ

+


+

A guide to common problems people experience, and what to do about them.

+



Tool Assisted Speedruns (TAS)


@@ -163,7 +174,14 @@ p,ul,ol /* Paragraph Style */

NES RAM Mapping


A guide to the layout of NES RAM, and how to interpret its contents.

-

2008

-

This help file has been generated by the freeware version of HelpNDoc

+


+


+

Debugger Usage Guide (Intermediate)

+


+

This is a guide that explains some of the debugging features in terms that someone

+

with previous experience with assembly can understand, and delves into the most

+

basic understanding to a degree as well. Likely won't help a beginner too much.

+

2008

+

This help file has been generated by the freeware version of HelpNDoc

diff --git a/files/{03E5715D-2A35-42A9-B4A9-E3D443C79FE2}.htm b/files/{03E5715D-2A35-42A9-B4A9-E3D443C79FE2}.htm index 9fa051de..68cb88ed 100644 --- a/files/{03E5715D-2A35-42A9-B4A9-E3D443C79FE2}.htm +++ b/files/{03E5715D-2A35-42A9-B4A9-E3D443C79FE2}.htm @@ -167,7 +167,7 @@ p,ul,ol /* Paragraph Style */

FCEUX provides a wealth of tools and resources to aid in hacking NES & FDS games.  It features the most current and cutting edge tools debugging and hacking games as well as making the process quicker an easier.


Debugging / Reverse engineering:

-

Debugger, Trace Logger, Code/Data Logger, Cheat Search, RAM Filter, Movie Making tools/Frame Advance

+

Debugger, Trace Logger, Code/Data Logger, Cheat Search, RAM Filter, Movie Making tools/Frame Advance


Memory & PPU Viewing:

Debugger, PPU Viewer, Hex Editor, Trace Logger, Code/Data Logger

diff --git a/files/{05FC9F4A-AB26-4164-A5F8-6824A3353760}.htm b/files/{05FC9F4A-AB26-4164-A5F8-6824A3353760}.htm index 257f9a3e..9790414e 100644 --- a/files/{05FC9F4A-AB26-4164-A5F8-6824A3353760}.htm +++ b/files/{05FC9F4A-AB26-4164-A5F8-6824A3353760}.htm @@ -150,7 +150,7 @@ p,ul,ol /* Paragraph Style */


The Code/Data Logger keeps track of every byte in the ROM and records whether it's code (is executed) or data (is read). In the future, I hope to combine this with a suitable disassembler that will disassemble only bytes marked as "code", in order to generate near-perfect source code (provided you play through the game several times, very thoroughly, to ensure everything gets logged). In order to get that feature to work, I need to get the Address Label Logger working, in order to create all the labels.


-

But right now, it is very useful for finding specific code and data by        using it with the Trace Logger (see above for instructions on doing this).  Furthermore, while it is running, the Hex Editor will color-code bytes depending on whether they were logged as code or data. And it can also be used to create a stripped NES ROM (see below).

+

But right now, it is very useful for finding specific code and data by using it with the Trace Logger (see above for instructions on doing this).  Furthermore, while it is running, the Hex Editor will color-code bytes depending on whether they were logged as code or data. And it can also be used to create a stripped NES ROM (see below).


Some notes: when you open another .cdl file, it does not clear the current log; instead, it combines it with the information in the file.  This can be useful if you're trying to obtain a complete log, as multiple people can play through the game and keep code/data logs, and then the results can be combined.  But if you would like to actually clear the code/data log, press the "Reset Log" button.


@@ -186,7 +186,7 @@ p,ul,ol /* Paragraph Style */

               P  = If logged as PCM audio data.

               x  = unused.


-

CDL files make possible a number of things never before done.  First, a PCM data ripper could be created that scans for data that has the 'P' bit set, in order to find/rip/play every PCM sample in a ROM.  Also, it is possible for someone to make a more intelligent ROM corruptor that only corrupts data (by checking the 'D' bit).  In any case, the Code/Data Logger opens many new possibilities for discovering useful things in games.  Another interesting possibility (which isn't supported yet) would be to use the Code/Data Logger on an NSF file to create a stripped NSF. Such an NSF would contain nothing but the relevant subroutines and data required by each tune played; this would be helpful to NSF rippers by removing irrelevant information. Thus, an NSF ripper could create a stripped NSF by listening to each track while the Code/Data Logger operates on it, and then saving the stripped NSF.  I might add this sometime, if I get any requests to do so.

+

CDL files make possible a number of things never before done.  First, a PCM data ripper could be created that scans for data that has the 'P' bit set, in order to find/rip/play every PCM sample in a ROM.  Also, it is possible for someone to make a more intelligent ROM corruptor that only corrupts data (by checking the 'D' bit).  In any case, the Code/Data Logger opens many new possibilities for discovering useful things in games.  Another interesting possibility (which is now partially supported) would be to use the Code/Data Logger on an NSF file to create a stripped NSF. Such an NSF would contain nothing but the relevant subroutines and data required by each tune played; this would be helpful to NSF rippers by removing irrelevant information. Thus, an NSF ripper could create a stripped NSF by listening to each track while the Code/Data Logger operates on it, and then saving the stripped NSF.  It should be noted that this capability, though tested and working on private builds, is detrimental to the process of fixing broken NSF files. For this reason, data logging is allowed for NSF files, but stripping NSF files of unused data is disabled.




diff --git a/files/{06F7BBD5-399E-4CA0-8E4E-75BE0ACC525A}.htm b/files/{06F7BBD5-399E-4CA0-8E4E-75BE0ACC525A}.htm index 0f5790ec..8887bdd5 100644 --- a/files/{06F7BBD5-399E-4CA0-8E4E-75BE0ACC525A}.htm +++ b/files/{06F7BBD5-399E-4CA0-8E4E-75BE0ACC525A}.htm @@ -77,24 +77,28 @@ span.rvts12 { font-size: 12pt; } -span.rvts13 /* Font Style */ +span.rvts13 +{ + font-weight: bold; +} +span.rvts14 /* Font Style */ { font-size: 16pt; font-family: 'Tahoma', 'Geneva', sans-serif; color: #ffffff; } -span.rvts14 /* Font Style */ +span.rvts15 /* Font Style */ { font-family: 'MS Sans Serif', 'Geneva', sans-serif; color: #808080; } -span.rvts15 /* Font Style */ +span.rvts16 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; color: #c0c0c0; } -a.rvts16, span.rvts16 /* Font Style */ +a.rvts17, span.rvts17 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; @@ -141,14 +145,14 @@ p,ul,ol /* Paragraph Style */ -

Hex Editor

+

Hex Editor

Hex Editor


Introduction


The Hex editor is a very powerful memory viewing/editing tool and obsoletes the Memory Viewer tool from the FCE Ultra and FCEU Rerecording branches.


-

It can do a wide range of things.  It allows you to view the entire RAM & ROM contents in an expandable dialog Window.  It makes it easy to edit the game's RAM, PPU memory, and even its currently-loaded ROM data. You can also "freeze" parts of RAM (to prevent the game from modifying the data there), search for data, and even copy and paste data to/from the clipboard.  Furthermore, table files are supported, so you can edit a game's text in real-time and see the result immediately.

+

It can do a wide range of things.  It allows you to view the entire RAM & ROM contents in an expandable dialog Window.  It makes it easy to edit the game's RAM, PPU memory, and even its currently-loaded ROM data by simply typing in values in the editor. You can also "freeze" parts of RAM (to prevent the game from modifying the data there), search for data, and even copy and paste data to/from the clipboard.  Furthermore, table files are supported, so you can edit a game's text in real-time and see the result immediately.


Basically, it lets you tinker with any part of a game's RAM or ROM while it is running.


@@ -157,14 +161,14 @@ p,ul,ol /* Paragraph Style */


The Hex Editor lets you edit three major areas:


-

1. NES MEMORY

+

1. NES MEMORY

This allows you to directly edit all of the NES address space ($0000-$FFFF). While you can easily modify RAM, or write directly to registers by typing in data, you cannot modify ROM data ($8000-$FFFF) itself.  This is because most mappers have registers which are located in this space; so writing there can trigger mapper operations that may cause the game to crash or glitch if you don't know what you're doing.  If you want to edit the ROM itself, right-click on the offset and select  "Go here in ROM file"; that will take you directly to where you need to be so you can start editing.  You can also freeze RAM by clicking on it with the middle mouse button, or by using the right-click menu. This works by adding it directly to the Cheat List, which you can see from the Cheat Console.  Finally, the right-click menu can be used to quickly add a read or write breakpoint to the debugger.


-

2. PPU MEMORY

+

2. PPU MEMORY

This allows you to directly view and write to PPU memory (VRAM).


-

3. THE ROM FILE

-

This is possibly the coolest part of FCEUXD: it allows you to edit the ROM file in real-time, i.e. while the game is running. If you make a mistake, press Ctrl+Z or Edit->Undo to undo your change (then load a save-state if the game crashed).  If you have the Code/Data Logger running, then bytes that were logged as code will be colored yellow, while bytes logged as data will be colored blue. Bytes that have been logged as code *and* data will be colored green.

+

3. THE ROM FILE

+

This is possibly the coolest part of FCEUXD:  It allows you to edit the ROM file in real-time, i.e. while the game is running. If you make a mistake, press Ctrl+Z or Edit->Undo to undo your change (then load a save-state if the game crashed).  If you have the Code/Data Logger running, then bytes that were logged as code will be colored yellow, while bytes logged as data will be colored blue. Bytes that have been logged as code *and* data will be colored green.


The Hex Editor also has support for table files (*.tbl) to map bytes to text. Each line consists of four characters of the form "xx=y", where "xx" is the hex value, and "y" is the character that that value represents.  I have also added an extension to represent the Return key:  xx=ret whereby pressing the Return key will enter that value into the ROM.  You can copy/paste data or text by selecting it and using Ctrl+Z (to copy) and Ctrl+V (to paste). Plus, there is an Edit->Find feature that you can use to search for data. This feature should be fairly intuitive, so I won't bother to explain it.


@@ -172,11 +176,11 @@ p,ul,ol /* Paragraph Style */


Why can't I edit NES memory beyond $8000?


-

NES memory from $8000-$FFFF is where the game's PRG-ROM code is mapped.  Whenever you type in a value in the NES memory editor, it effectively writes that value to that address. Many games use mappers, which are usually accessed by writing to $8000-$FFFF (which is read-only)... and if *you* were to do so, it may trigger a bankswitch, which could easily        make the game crash. In any event, doing so will not modify the ROM itself.  What you *can* do, though, is edit the PRG-ROM itself by right-clicking on the offset you wish to edit, and selecting "Go here in the ROM file", which should take you to that spot in the ROM, from which you can then.

+

NES memory from $8000-$FFFF is where the game's PRG-ROM code is mapped.  Whenever you type in a value in the NES memory editor, it effectively writes that value to that address. Many games use mappers, which are usually accessed by writing to $8000-$FFFF (which is read-only)... and if *you* were to do so, it may trigger a bankswitch, which could easily make the game crash. In any event, doing so will not modify the ROM itself.  What you *can* do, though, is edit the PRG-ROM itself by right-clicking on the offset you wish to edit, and selecting "Go here in the ROM file", which should take you to that spot in the ROM instead, where you can change the data at instead.


.


-

2008

-

This help file has been generated by the freeware version of HelpNDoc

+

2008

+

This help file has been generated by the freeware version of HelpNDoc

diff --git a/files/{10AC9AD4-75EE-41A9-A67E-8136B6746C2E}.htm b/files/{10AC9AD4-75EE-41A9-A67E-8136B6746C2E}.htm index a4417e9f..85154d7e 100644 --- a/files/{10AC9AD4-75EE-41A9-A67E-8136B6746C2E}.htm +++ b/files/{10AC9AD4-75EE-41A9-A67E-8136B6746C2E}.htm @@ -148,7 +148,7 @@ p,ul,ol /* Paragraph Style */


LuaBot employs a new concept in FCEUX Tool creation.  It is an external lua script that creates the Basic bot GUI.  The GUI then uses lua scripting to perform botting tasks.


-

To run it you must have lua scripting enabled (see Getting Started).  LuaBot is included the lua pack under /examplelua.  to get started run  luabot_framework.lua.

+

To run it you must have lua scripting enabled (see Getting Started).  LuaBot is included in the lua pack under /luaScripts.  to get started run  luabot_framework.lua.


What is Lua Bot?

LuaBot is...well, a bot. It uses a combination of probability, scripting and RAM monitoring to play games.  Specifically  basic bot is used to create portions of Tool Assisted Speedrun.   It is most powerful for finding solutions in highly random situations, or highly improbably events (such as manipulating a critical hit in an RPG).  Basic bot comes with a rather powerful scripting language in order to be "programmed" to handle these specific situations.  LuaBot in its most extreme application can even be "taught" to play video games!

diff --git a/files/{150E3DC4-306A-4C19-A790-C45427CABB2F}.htm b/files/{150E3DC4-306A-4C19-A790-C45427CABB2F}.htm index 668a25c3..7b405d1f 100644 --- a/files/{150E3DC4-306A-4C19-A790-C45427CABB2F}.htm +++ b/files/{150E3DC4-306A-4C19-A790-C45427CABB2F}.htm @@ -158,31 +158,39 @@ p,ul,ol /* Paragraph Style */


Debugger


-

A tool for looking at game instructions in assembly language.

+

A tool for looking at game instructions in assembly language. With experience,

+

one can use it to fix game patching errors, or find RAM and Game Genie codes.


PPU Viewer


-

A tool that displays the current PPU contents and related information.

+

A tool that displays the current PPU contents and related information. The PPU

+

viewer allows you to view the graphic squares that make up what's displayed.


Name Table Viewer


-

A tool for displaying the current Name Table contents.

+

A tool for displaying the current Name Table contents. Helps to isolate PPU

+

and tile information, which allows the debugger to be used to check PPU coding.


Hex Editor


-

A tool for displaying the games ram contents and for memory poking.

+

A tool for displaying a game's RAM contents and for memory poking. Also allows

+

for reading in the raw PPU data, copy/paste-ing RAM, and visually debugging RAM.


Trace Logger


-

Captures assembly code instructions and outputs them to a file or the window.

+

Captures assembly code instructions and outputs them to a file or the window. Very

+

useful for modifying code, finding crash addresses, fixing transferred routines, and

+

for comparing routine function between a game and a persistently buggy NSF.


Code/Data Logger


-

blurb

+

Allows you to extract the data used by a game. Make patch demos, find data

+

loaded by a game around a certain point, or just map out a single routine run.


Game Genie Encoder/Decoder


-

blurb

+

Allows you to add Game Genie codes to the Cheats menu, decode existing

+

ones to their component information, and (re)create a code with desired values.


2008

This help file has been generated by the freeware version of HelpNDoc

diff --git a/files/{1DB6043F-35B9-4909-A413-5B6216E7F320}.htm b/files/{1DB6043F-35B9-4909-A413-5B6216E7F320}.htm index c0e7e936..1fcb25cd 100644 --- a/files/{1DB6043F-35B9-4909-A413-5B6216E7F320}.htm +++ b/files/{1DB6043F-35B9-4909-A413-5B6216E7F320}.htm @@ -246,6 +246,8 @@ p,ul,ol /* Paragraph Style */


The input display will display 1-4 pictures of a NES controller at the bottom of the screen.  When playing/recording a movie, these controllers will display the input that is captured in the file. 


+

When input comes from a movie file rather than then user, it is displayed in a different color (silver)

+


The input display can also be toggled by hotkey/  The default key for toggling the Input display is the "," (comma) key.  (This can be re-mapped in the Map Hotkeys Menu).



diff --git a/files/{1E4DB333-D92D-4E6F-8843-A69CC227763F}.htm b/files/{1E4DB333-D92D-4E6F-8843-A69CC227763F}.htm index c8f249aa..b0bb6070 100644 --- a/files/{1E4DB333-D92D-4E6F-8843-A69CC227763F}.htm +++ b/files/{1E4DB333-D92D-4E6F-8843-A69CC227763F}.htm @@ -75,24 +75,29 @@ a.rvts11, span.rvts11 text-decoration: underline; } a.rvts11:hover { color: #0000ff; } -span.rvts12 /* Font Style */ +span.rvts12 +{ + font-size: 12pt; + font-weight: bold; +} +span.rvts13 /* Font Style */ { font-size: 16pt; font-family: 'Tahoma', 'Geneva', sans-serif; color: #ffffff; } -span.rvts13 /* Font Style */ +span.rvts14 /* Font Style */ { font-family: 'MS Sans Serif', 'Geneva', sans-serif; color: #808080; } -span.rvts14 /* Font Style */ +span.rvts15 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; color: #c0c0c0; } -a.rvts15, span.rvts15 /* Font Style */ +a.rvts16, span.rvts16 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; @@ -139,17 +144,20 @@ p,ul,ol /* Paragraph Style */ -

RAM Search

+

RAM Search

Ram Search


-

Ram Search is a tool originally written for GENS rerecording.  It was ported to FCEUX in version 2.1.2.  This dialog has also been ported to SNES9x-rr, Desmume, PCEjin, VBA-rr, PCSX-rr, Yabause, and FBA-rr.

+

Ram Search is a tool originally written for GENS rerecording.  It was ported to FCEUX in version 2.1.2.  This dialog has also been ported to SNES9x-rr, Desmume, PCEjin, VBA-rr, PCSX-rr, Yabause, VBjin, and FBA-rr.



It is designed to filter ram values just like in the Cheat Search dialog.  However, it features many options that are lacking in the Cheat Search dialog.  Among these are search undo, search preview, a modulus filter, a data size option, signed/unsigned/hex options, autosearch, and several more compare by options.


Documentation on this dialog can be found on TASVideos here.


-

2008

-

This help file has been generated by the freeware version of HelpNDoc

+

Hotkeys

+


+

Hotkeys can be assigned to common search commands so they can be easily selected while in the main window.

+

2008

+

This help file has been generated by the freeware version of HelpNDoc

diff --git a/files/{26F9812A-A0FB-4F3F-8514-5E6A7984F327}.htm b/files/{26F9812A-A0FB-4F3F-8514-5E6A7984F327}.htm index 63c6729d..8c33894c 100644 --- a/files/{26F9812A-A0FB-4F3F-8514-5E6A7984F327}.htm +++ b/files/{26F9812A-A0FB-4F3F-8514-5E6A7984F327}.htm @@ -146,7 +146,9 @@ p,ul,ol /* Paragraph Style */

Getting Started

Using Lua scripting


-

To run lua scripts you will need the lua pack which can be found here.  The .dll files must be unzipped in the same folder as fceux.exe.

+

Lua is built into FCEUX as of 2.1.2, and luapack DLL files are no longer needed in this and later versions.

+


+

To run lua scripts in older versions of FCEUX, you will need the lua pack which can be found here. The .dll files must be unzipped in the same folder as fceux.exe.


Core Lua Documentation


diff --git a/files/{3BB85A6B-4C1E-4136-A7FF-A8A6E4894F80}.htm b/files/{3BB85A6B-4C1E-4136-A7FF-A8A6E4894F80}.htm index 58d345e1..8d996c65 100644 --- a/files/{3BB85A6B-4C1E-4136-A7FF-A8A6E4894F80}.htm +++ b/files/{3BB85A6B-4C1E-4136-A7FF-A8A6E4894F80}.htm @@ -270,6 +270,13 @@ p,ul,ol /* Paragraph Style */

Unhide menu

If the main FCEUX menu is hidden this option is available. Restores the main menu.


+

Subtitles

+


+

If a movie is loaded and has subtitles,

+

a toggle subtitles option will be in the menu

+

a Dump to SRT file option will be available.  This dumps the subtitles to a standard subtitle file compatible with A/V containers such as .mkv

+


+


2008

This help file has been generated by the freeware version of HelpNDoc

diff --git a/files/{414E8900-7ECB-4E7A-96FE-13F095EDF1DE}.htm b/files/{414E8900-7ECB-4E7A-96FE-13F095EDF1DE}.htm index 693a6bb0..de2fe06c 100644 --- a/files/{414E8900-7ECB-4E7A-96FE-13F095EDF1DE}.htm +++ b/files/{414E8900-7ECB-4E7A-96FE-13F095EDF1DE}.htm @@ -148,7 +148,7 @@ p,ul,ol /* Paragraph Style */


Introduction


-

The Trace Logger logs every executed instruction either to a file or to the window.  Logging to a file is useful if you just want to dump everything that was executed and then search through it later.  Logging to the window is useful when you wish to see the instructions that were executed prior to a breakpoint being hit.

+

The Trace Logger logs every executed instruction and every byte of ROM accessed to the window, or a file if you prefer.  Logging to a file is useful if you just want to dump everything that was executed and then search through it later.  Logging to the window is useful when you wish to see the instructions that were executed prior to a breakpoint being hit.  Both options produce the same data, but the desire to keep that data for a short amount of time or a long amount of time will determine which is best for you.



Using the Trace Logger

diff --git a/files/{607BB21A-0839-47E9-AF33-9F631D541D9D}.htm b/files/{607BB21A-0839-47E9-AF33-9F631D541D9D}.htm index 4d6c85e8..dcb76c3f 100644 --- a/files/{607BB21A-0839-47E9-AF33-9F631D541D9D}.htm +++ b/files/{607BB21A-0839-47E9-AF33-9F631D541D9D}.htm @@ -163,14 +163,14 @@ p,ul,ol /* Paragraph Style */


A note on on the format of external palettes; Palette files are expected to contain 64 8-bit RGB triplets(each in that order; red comes first in the triplet in the file, then green, then blue). Each 8-bit value represents brightness for that particular color. 0 is minimum, 255 is maximum.


-

Palettes can be set on a per-game basis. To do this, put a palette file in the "gameinfo" directory with the same base filename as the game you wish to associate with and add the extension "pal". Examples:

+

Palettes can be set on a per-game basis. To do this, put a palette file in the same directory the game is in, and add the extension "pal". Examples:


       

                File name:              Palette file name:

                 BigBad.nes             BigBad.pal

                 BigBad.zip              BigBad.pal

                 BigBad.Better.nes   BigBad.Better.pal

-

       

+



With so many ways to choose a palette, figuring out which one will be active may be difficult. Here's a list of what palettes will be used, in order from highest priority to least priority(if a condition doesn't exist for a higher priority palette, the emulator will continue down its list of palettes).


diff --git a/files/{7375BEB7-A588-45AB-8BC4-F7840D87DADD}.htm b/files/{7375BEB7-A588-45AB-8BC4-F7840D87DADD}.htm index bec57440..faba8d75 100644 --- a/files/{7375BEB7-A588-45AB-8BC4-F7840D87DADD}.htm +++ b/files/{7375BEB7-A588-45AB-8BC4-F7840D87DADD}.htm @@ -68,24 +68,30 @@ span.rvts10 { font-size: 16pt; } -span.rvts11 /* Font Style */ +a.rvts11, span.rvts11 +{ + color: #0000ff; + text-decoration: underline; +} +a.rvts11:hover { color: #0000ff; } +span.rvts12 /* Font Style */ { font-size: 16pt; font-family: 'Tahoma', 'Geneva', sans-serif; color: #ffffff; } -span.rvts12 /* Font Style */ +span.rvts13 /* Font Style */ { font-family: 'MS Sans Serif', 'Geneva', sans-serif; color: #808080; } -span.rvts13 /* Font Style */ +span.rvts14 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; color: #c0c0c0; } -a.rvts14, span.rvts14 /* Font Style */ +a.rvts15, span.rvts15 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; @@ -132,7 +138,7 @@ p,ul,ol /* Paragraph Style */ -

Commands

+

Commands

(written by qFox)


Introduction

@@ -325,8 +331,8 @@ p,ul,ol /* Paragraph Style */

savestate.load(state); -- load the given savestate

savestate.save(state); -- save the given savestate


-


-

2008

-

This help file has been generated by the freeware version of HelpNDoc

+

For an up-to-date list of functions, see the Lua Functions List.

+

2008

+

This help file has been generated by the freeware version of HelpNDoc

diff --git a/files/{752A1A8F-39AE-4D95-B04E-23FD9D43338F}.htm b/files/{752A1A8F-39AE-4D95-B04E-23FD9D43338F}.htm index 640613a7..9be19de3 100644 --- a/files/{752A1A8F-39AE-4D95-B04E-23FD9D43338F}.htm +++ b/files/{752A1A8F-39AE-4D95-B04E-23FD9D43338F}.htm @@ -154,7 +154,7 @@ p,ul,ol /* Paragraph Style */


FCE Ultra Version History


-

What's New?

+

What's Combined In FCEUX?

2008

This help file has been generated by the freeware version of HelpNDoc

diff --git a/files/{7EEBAD0B-2126-4A8A-864F-61D603111A68}.htm b/files/{7EEBAD0B-2126-4A8A-864F-61D603111A68}.htm index f2bfd5eb..1745c4cf 100644 --- a/files/{7EEBAD0B-2126-4A8A-864F-61D603111A68}.htm +++ b/files/{7EEBAD0B-2126-4A8A-864F-61D603111A68}.htm @@ -164,6 +164,8 @@ p,ul,ol /* Paragraph Style */


Version Releases


+

Look at the Side Bar navigation for changelog information on FCEUX 2.1 and newer.

+


FCEUX 2.0.3 - Released November 02, 2008 (see changelog)


FCEUX 2.0.2 - Released August 14, 2008 (see changelog)

@@ -213,7 +215,7 @@ p,ul,ol /* Paragraph Style */

FCEUXDSP stands for FCEUXD "SP" version and is a branch of FCEUXD 1.0a.

It was created in 2006 by sp.  The project extends the debugging tools even further compared to FCEUXD by adding new tools, functions, and usability of debugging tools. 


-

The last version of FCEUXDSP was 1.07 which adds a feature known as the RAM Filter.

+

The last version of FCEUXDSP was 1.07 which adds a feature known as the RAM Filter. This has since been removed, due to functional redundancy.


FCEUXDSP homepage


diff --git a/files/{88A0A828-FEF6-4230-AECD-9A5315C384D2}.htm b/files/{88A0A828-FEF6-4230-AECD-9A5315C384D2}.htm index 6a0f9a76..db856761 100644 --- a/files/{88A0A828-FEF6-4230-AECD-9A5315C384D2}.htm +++ b/files/{88A0A828-FEF6-4230-AECD-9A5315C384D2}.htm @@ -156,7 +156,7 @@ p,ul,ol /* Paragraph Style */


Note that the Name Table Viewer will display the name tables using whatever CHR is present at the time the "Display on Scanline" scanline is reached. So for example if it does not correctly display a game's status bar, try setting it to update on a scanline in which the status bar is displayed.


-

The same applies to the Scroll Lines: they display the state of the PPU scroll registers when the "Display on Scanline" scanline is reached. So for example if said scanline is within the game's status bar, it will not display level scrolling because the horizontal scroll is always zero at the time that scanline is drawn. To display the        level scrolling, set it to update on a scanline in which the level is displayed.

+

The same applies to the Scroll Lines: they display the state of the PPU scroll registers when the "Display on Scanline" scanline is reached. So for example if said scanline is within the game's status bar, it will not display level scrolling because the horizontal scroll is always zero at the time that scanline is drawn. To display the level scrolling, set it to update on a scanline in which the level is displayed.


Display on scanline

This will show what it looks like when the NES has finished drawing that many scanlines to screen including any PPU data scroll line movement

diff --git a/files/{8A78E5FE-C7EB-418D-A921-F9A6782663F0}.htm b/files/{8A78E5FE-C7EB-418D-A921-F9A6782663F0}.htm index 2ce17400..c5f4b7ae 100644 --- a/files/{8A78E5FE-C7EB-418D-A921-F9A6782663F0}.htm +++ b/files/{8A78E5FE-C7EB-418D-A921-F9A6782663F0}.htm @@ -77,24 +77,30 @@ span.rvts12 { font-size: 14pt; } -span.rvts13 /* Font Style */ +a.rvts13, span.rvts13 +{ + color: #0000ff; + text-decoration: underline; +} +a.rvts13:hover { color: #0000ff; } +span.rvts14 /* Font Style */ { font-size: 16pt; font-family: 'Tahoma', 'Geneva', sans-serif; color: #ffffff; } -span.rvts14 /* Font Style */ +span.rvts15 /* Font Style */ { font-family: 'MS Sans Serif', 'Geneva', sans-serif; color: #808080; } -span.rvts15 /* Font Style */ +span.rvts16 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; color: #c0c0c0; } -a.rvts16, span.rvts16 /* Font Style */ +a.rvts17, span.rvts17 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; @@ -141,10 +147,10 @@ p,ul,ol /* Paragraph Style */ -

Debugger

+

Debugger

Debugger


-

Taken from the FCEUXDSP1.07 documentation.

+

Taken from the FCEUXDSP 1.07 documentation.


Introduction


@@ -152,10 +158,10 @@ p,ul,ol /* Paragraph Style */


Debugger Features


-

-When you hold the mouse over the left pane in the debugger, you can now see the ROM file address of the data loaded there.  -Right-click in that pane, it will bring up the Hex Editor at that address so you can immediately begin editing.

+

-When you hold the mouse over the left pane in the debugger, you can now see the ROM file address of the data loaded there.

+

-Right-click in that pane, it will bring up the Hex Editor at that address so you can immediately begin editing.

-Left-clicking in that pane brings up the inline assembler.

-

-"Break on bad opcode" feature; this can help you figure out where your game is crashing. Middle-clicking on a byte will bring up the

-

       Game Genie Encoder at that address, so you can easily make Game Genie codes.

+

-"Break on bad opcode" feature; this can help you figure out where your game is crashing. Middle-clicking on a byte will bring up the Game Genie Encoder at that address, so you can easily make Game Genie codes.

-Debugging data like breakpoints or bookmarks are automatically saved and restored when games are closed / opened.

-Ability to give breakpoints a brief description/name.

-All debugging information for addresses < $8000 into the name list file romname.nes.ram.nl.

@@ -172,7 +178,7 @@ p,ul,ol /* Paragraph Style */


The most important feature (at least for me) that was introduced in FCEUXD SP is symbolic debugging.  With this new feature it's possible to rename addresses in the disassembly window (like $C022) to easily understandable names (like AddHealthpoints). It's also possible to add comments to lines in the disassembly window.


-

To be able to use this feature it's necessary to create so called name list files (*.nl) which contain all names and comments you wish to display in the disassembly window. These files are plain ASCII files of the following format (example follows):

+

To be able to use this feature it's necessary to create so called name list files (*.(bank).nl/*.ram.nl, Ex: NES Test Cart (PD).nes.0.nl, NES Test Cart (PD).nes.ram.nl) which contain all names and comments you wish to display in the disassembly window. These files are plain ASCII files of the following format (example follows):


$C000#NewName1#Comment1

$C002##Comment2

@@ -200,6 +206,10 @@ p,ul,ol /* Paragraph Style */

ROM bank 15. As 15 is 0x0F in hex the name of the nl file would be "Faxanadu (U).nes.F.nl". All

nl files go into the same directory as the ROM file itself.


+

There is also the *.ram.nl file specification, which allows you to substitute RAM addresses for

+

execution addresses, and have those named as well. In this case, you could use lines of this type:

+

$00A5#Mic Test OK#00=Not Passed, 01=Passed

+


You can enable and disable symbolic debugging by clicking the checkbox "Symbolic Debugging" in

the debugger window. To forcibly reload the nl files of the currently active ROM file press the

button with the text "Reload Symbols".

@@ -219,7 +229,7 @@ p,ul,ol /* Paragraph Style */

Inline Assembler


The debugger an Inline Assembler designed by Parasyte.  To activate it, left-click in the left pane of the debugger, beside the assembly display.  To use it, type in some code and press Enter to add it to the patch list. If you make a mistake, press "Undo".  Once the patch is set up the way you want it, press "Apply". Be aware that this cannot be undone unless you reload the ROM.  Parasyte implemented this feature before I had the Hex Editor working, otherwise I would have implemented a way to undo it from there.  Press "Save" to write to the ROM file on disk; note that this will also save any changes you may have done in the Hex Editor.

-

2008

-

This help file has been generated by the freeware version of HelpNDoc

+

2008

+

This help file has been generated by the freeware version of HelpNDoc

diff --git a/files/{8C035D09-D641-451D-ADEC-7226AE495EDD}.htm b/files/{8C035D09-D641-451D-ADEC-7226AE495EDD}.htm index c17bc17e..cfc55cec 100644 --- a/files/{8C035D09-D641-451D-ADEC-7226AE495EDD}.htm +++ b/files/{8C035D09-D641-451D-ADEC-7226AE495EDD}.htm @@ -204,7 +204,7 @@ p,ul,ol /* Paragraph Style */


---- Section "CPUC" (emulator specific)


-

        Name:   Type:           Description:

+

       Name:        Type:                Description:


       JAMM        uint8                Non-zero value if CPU in a "jammed" state

       IRQL        uint8                Non-zero value if IRQs are to be generated constantly

@@ -213,7 +213,7 @@ p,ul,ol /* Paragraph Style */


---- Section "PPU"


-

        Name:   Type:           Description:

+

       Name:        Type:                Description:


       NTAR        uint8[0x800]        2 KB of name/attribute table RAM

       PRAM        uint8[32]        32 bytes of palette index RAM

@@ -231,7 +231,7 @@ p,ul,ol /* Paragraph Style */


---- Section "CTLR" (somewhat emulator specific)


-

        Name:   Type:           Description:

+

       Name:        Type:                Description:


       J1RB        uint8                Bit to be returned when first joystick is read.

       J2RB        uint8                Bit to be returned when second joystick is read.

@@ -251,7 +251,7 @@ p,ul,ol /* Paragraph Style */


       For iNES-format games(incomplete, and doesn't apply to every game):


-

        Name:   Type:           Description:

+

       Name:        Type:                Description:


       WRAM        uint8[0x2000]        8KB of WRAM at $6000-$7fff

       MEXR        uint8[0x8000]        (very emulator specific)

@@ -267,23 +267,23 @@ p,ul,ol /* Paragraph Style */

       IQL1        uint32                Generic IRQ latch

       IQL2        uint32                Generic IRQ latch

       IRQA        uint8                Generic IRQ on/off register.

-

       PBL        uint8[4]        List of 4 8KB ROM banks paged in at $8000-$FFFF

-

       CBL        uint8[8]        List of 8 1KB VROM banks page in at $0000-$1FFF(PPU).

+

       PBL        uint8[4]                List of 4 8KB ROM banks paged in at $8000-$FFFF

+

       CBL        uint8[8]                List of 8 1KB VROM banks page in at $0000-$1FFF(PPU).


       For FDS games(incomplete):


-

        Name:   Type:           Description:

+

       Name:        Type:                Description:


-

        DDT<x>  uint8[65500]    Disk data for side x(0-3).

+

       DDT<x>  uint8[65500]    Disk data for side x(0-3).

       FDSR        uint8[0x8000]        32 KB of work RAM

       CHRR        uint8[0x2000]        8 KB of CHR RAM

-

        IRQC    uint32          IRQ counter

-

        IQL1    uint32          IRQ latch

-

        IRQA    uint8           IRQ on/off.

+

       IRQC        uint32                IRQ counter

+

       IQL1        uint32                IRQ latch

+

       IRQA        uint8                IRQ on/off.


       WAVE        uint8[64]        Carrier waveform data.

       MWAV        uint8[32]        Modulator waveform data.

-

       AMPL        uint8[2]        Amplitude data.

+

       AMPL        uint8[2]                Amplitude data.


2008

This help file has been generated by the freeware version of HelpNDoc

diff --git a/files/{9A81FAEB-3CF8-4A11-8805-76EAD7C67F58}.htm b/files/{9A81FAEB-3CF8-4A11-8805-76EAD7C67F58}.htm index 0afc9621..431b6581 100644 --- a/files/{9A81FAEB-3CF8-4A11-8805-76EAD7C67F58}.htm +++ b/files/{9A81FAEB-3CF8-4A11-8805-76EAD7C67F58}.htm @@ -64,24 +64,28 @@ span.rvts9 /* Font Hint Italic */ font-style: italic; color: #808080; } -span.rvts10 /* Font Style */ +span.rvts10 +{ + font-family: 'Courier New', 'Courier', monospace; +} +span.rvts11 /* Font Style */ { font-size: 16pt; font-family: 'Tahoma', 'Geneva', sans-serif; color: #ffffff; } -span.rvts11 /* Font Style */ +span.rvts12 /* Font Style */ { font-family: 'MS Sans Serif', 'Geneva', sans-serif; color: #808080; } -span.rvts12 /* Font Style */ +span.rvts13 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; color: #c0c0c0; } -a.rvts13, span.rvts13 /* Font Style */ +a.rvts14, span.rvts14 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; @@ -128,7 +132,7 @@ p,ul,ol /* Paragraph Style */ -

NES Sound

+

NES Sound

*******************************************

*2A03 sound channel hardware documentation*

*******************************************

@@ -233,8 +237,8 @@ p,ul,ol /* Paragraph Style */

$4004-$4007        Square wave 2 (identical to the first, except for upward frequency sweeps (see "sweep unit" section))

$4008-$400B        Triangle

$400C-$400F        Noise

-

$4015             Channel enable / length/frame counter status

-

$4017             frame counter control

+

$4015                Channel enable / length/frame counter status

+

$4017                frame counter control


Note that $4015 (and $4017, but is unrelated to sound hardware) are the only R/W registers. All others are write only (attempt to read them will most likely return the last byte on the bus (usually 040H), due to heavy capacitance on the NES's data bus). Reading a "write only" register, will have no effect on the specific register, or channel.


@@ -332,18 +336,18 @@ p,ul,ol /* Paragraph Style */

************************

This section will describe the internal components making up each individual channel. Each component will then be described in full detail.


-

Device                        Triangle Noise  Square

-

------                        -------- ------ ------

-

triangle step generator              X

-

linear counter                       X

-

programmable timer                   X      X      X

-

length counter                       X      X      X

-

4-bit DAC                            X      X      X

-

volume/envelope decay unit                  X      X

-

sweep unit                                         X

-

duty cycle generator                               X

-

wavelength converter                        X

-

random number generator                     X

+

Device                                 Triangle Noise  Square

+

------                                 -------- ------ ------

+

triangle step generator                        X

+

linear counter                                X

+

programmable timer                        X      X      X

+

length counter                                X      X      X

+

4-bit DAC                                        X      X      X

+

volume/envelope decay unit                         X      X

+

sweep unit                                                          X

+

duty cycle generator                                          X

+

wavelength converter                                 X

+

random number generator                                 X



+-------------------------+

@@ -442,7 +446,7 @@ p,ul,ol /* Paragraph Style */

The 5-bit length value written, determines what 7-bit value the length counter will start counting from. A conversion table here will show how the values are translated.


       +-----------------------+

-

       |        bit3=0                |

+

       |        bit3=0        |

       +-------+---------------+

       |        |frames                |

       |bits        +-------+-------+

@@ -680,7 +684,7 @@ p,ul,ol /* Paragraph Style */



EOF

-

2008

-

This help file has been generated by the freeware version of HelpNDoc

+

2008

+

This help file has been generated by the freeware version of HelpNDoc

diff --git a/files/{ACA99B5B-9CA3-4E69-B7F7-106D70CF76BF}.htm b/files/{ACA99B5B-9CA3-4E69-B7F7-106D70CF76BF}.htm index aea41581..81986e64 100644 --- a/files/{ACA99B5B-9CA3-4E69-B7F7-106D70CF76BF}.htm +++ b/files/{ACA99B5B-9CA3-4E69-B7F7-106D70CF76BF}.htm @@ -159,7 +159,7 @@ p,ul,ol /* Paragraph Style */


Making Game Genie codes permanent


-

Using the Game Genie Code Decoder/Encoder, enter in your code in the "Game Genie Code" box, and under "Possible Affected ROM File Addresses", a list of possible matches (usually from 1 to 5) is displayed. Using the built-in Hex Editor, go to the first listed address in the ROM, and        change its value to the value given in the "Value" box (of the GG code Decoder/Encoder window). If the desired effect isn't achieved, undo the change (Ctrl+Z) and try the next address. Repeat until the desired        effect is achieved, and then save the ROM.

+

Using the Game Genie Code Decoder/Encoder, enter in your code in the "Game Genie Code" box, and under "Possible Affected ROM File Addresses", a list of possible matches (usually from 1 to 5) is displayed. Using the built-in Hex Editor, go to the first listed address in the ROM, and change its value to the value given in the "Value" box (of the GG code Decoder/Encoder window). If the desired effect isn't achieved, undo the change (Ctrl+Z) and try the next address. Repeat until the desired effect is achieved, and then save the ROM.



How do I make my own Game Genie codes?

@@ -170,7 +170,7 @@ p,ul,ol /* Paragraph Style */

* know how to use the debugger;

* understand NES PRG-ROM bank switching.


-

Once you've found a part of PRG-ROM you want to change to create a code effect, snap the Debugger (if it's not so already) and find the code's location in the PRG-ROM's address space ($8000-$FFFF) (you'll want the        debugger snapped so the game won't swap banks out from under you).        Then, using the built-in Hex Editor, view the NES memory and go to the PRG-ROM address you wish to modify, then right-click the byte and choose "Create Game Genie Code at this Address". The Game Genie Code Decoder/Encoder will appear, with the Address and Compare boxes filled in (the Compare box represents the address's original value). Enter the new value into the "Value" box.

+

Once you've found a part of PRG-ROM you want to change to create a code effect, snap the Debugger (if it's not so already) and find the code's location in the PRG-ROM's address space ($8000-$FFFF) (you'll want the debugger snapped so the game won't swap banks out from under you). Then, using the built-in Hex Editor, view the NES memory and go to the PRG-ROM address you wish to modify, then right-click the byte and choose "Create Game Genie Code at this Address". The Game Genie Code Decoder/Encoder will appear, with the Address and Compare boxes filled in (the Compare box represents the address's original value). Enter the new value into the "Value" box.


An alternative way to enter the code is to locate the desired address in the debugger, and then middle-click on it, which will summon the GG Code Decoder/Encoder. Then enter the code as described above

2008

diff --git a/files/{B37E7A47-E65F-4544-BDDF-39BE708BA68F}.htm b/files/{B37E7A47-E65F-4544-BDDF-39BE708BA68F}.htm index 74de2733..7b8c53c7 100644 --- a/files/{B37E7A47-E65F-4544-BDDF-39BE708BA68F}.htm +++ b/files/{B37E7A47-E65F-4544-BDDF-39BE708BA68F}.htm @@ -87,24 +87,28 @@ span.rvts14 font-size: 24pt; text-decoration: underline; } -span.rvts15 /* Font Style */ +span.rvts15 +{ + font-weight: bold; +} +span.rvts16 /* Font Style */ { font-size: 16pt; font-family: 'Tahoma', 'Geneva', sans-serif; color: #ffffff; } -span.rvts16 /* Font Style */ +span.rvts17 /* Font Style */ { font-family: 'MS Sans Serif', 'Geneva', sans-serif; color: #808080; } -span.rvts17 /* Font Style */ +span.rvts18 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; color: #c0c0c0; } -a.rvts18, span.rvts18 /* Font Style */ +a.rvts19, span.rvts19 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; @@ -151,7 +155,7 @@ p,ul,ol /* Paragraph Style */ -

Cheat Search

+

Cheat Search

FCE Ultra Cheat Guide


Introduction

@@ -195,6 +199,12 @@ p,ul,ol /* Paragraph Style */

You can add, delete, and update cheats in the active cheats window with the boxes below.

To find an address use the cheat search portion of the window.


+

There is also a right-click menu with the options Toggle Cheat, Poke Cheat Value, and Goto In Hex Editor.

+


+

Toggle Cheat is like Double Clicking. It enables or disables the cheat code.

+

Poke Cheat Value is like turning the cheat on, but in this case there's no off switch. If the code is on when you use this, then when the code is turned off, it will revert to the value last used. Good for one time life refills, if you want that sort of thing.

+

Goto in Hex Editor opens the Hex Editor window, and puts the cursor on the address shown. It's somewhat similar to how Bookmarks work in the Hex Editor.

+


Cheat Search


The cheat search is used to find a specific value in the games RAM by process of elimination.

@@ -223,7 +233,7 @@ p,ul,ol /* Paragraph Style */


Any value in the possibilities list can be sent to memory watch by double clicking it. 

Highlighting it and hitting the "Add" button under the Active cheats window will automatically activate it as a cheat with the value set to its current value.

-


+


Example


Here is an example of cheat search in action.

@@ -231,8 +241,17 @@ p,ul,ol /* Paragraph Style */

Let's say I am playing Mega man 3 and I want to find Mega man's energy level in the game's ram.  I will start by opening the ROM and selecting a level.  At this point, I know Mega man's energy address is active.  So I will pause the game and open the cheat search and hit the reset button.  The game uses SRAM so the possibilities window will say 10240 "possibilities". 

Next I will frame advance (or briefly unpause) the game.  At this point I know Mega man's energy level is still the same as it was.  So I click the "equal" button.   Next I want to take damage.  I know for sure now that the energy level has decreased so after the "ouch" animation, I click the "Less than button".  This will cut the possibilities down significantly.  Next I will advance some more and click the "Equal" button since I know the value is still the previous value.  I will repeat this cycle until I am down to 1 or just a few values.  From there I can double click the values to send them to memory watch to monitor them more closely to weed them out.  (Note:  Mega man's energy is located in $00A2).


+

Context Menu


-

2008

-

This help file has been generated by the freeware version of HelpNDoc

+

Right-clicking in the active cheats list brings up the context menu.

+


+

Toggle Cheat - does the same thing as double clicking

+


+

Poke cheat value - has a different affect that normal freezing, this makes a one time write of that value as opposed to freezing it temporarily to that value and having it restored later.  It has the same affect as typing in values in the Hex Editor.

+


+

Goto In Hex Editor - Opens the Hex editor dialog to the position of the selected RAM value.

+


+

2008

+

This help file has been generated by the freeware version of HelpNDoc

diff --git a/files/{BA48F691-421D-453C-A04B-F73440BE0263}.htm b/files/{BA48F691-421D-453C-A04B-F73440BE0263}.htm index 09d1b576..8fe7c5a8 100644 --- a/files/{BA48F691-421D-453C-A04B-F73440BE0263}.htm +++ b/files/{BA48F691-421D-453C-A04B-F73440BE0263}.htm @@ -152,7 +152,7 @@ p,ul,ol /* Paragraph Style */

Slow emulation / Sound crackle


FCEUX may not run well on slower CPU's.  You can improve performance by setting sound to low quality in the Sound Dialog.  In addition, for windowed mode try enabling hardware acceleration in the Video config dialog may also help.

-

       

+


Slow savestates when recording movies


On slower computers, savestates can be slow with long movies.  A small speedup can be done by disabling config > enable > Backup savestates.

@@ -178,7 +178,7 @@ p,ul,ol /* Paragraph Style */


Double check you have the Lua .dll files that came packaged with FCEUX 2.1.  They must be in the /dll folder from the root directory (where fceux.exe is stored).


-

               

+

"Directdraw: Error creating secondary surface"


Currently this error will happen when attempting to do Full screen mode on Windows Vista.  In addition, there has been one reported case of this happening on the 32-bit version of Windows XP.  This is a known issue with FCEUX that has not yet been resolved.

diff --git a/files/{C652C305-E5FC-4C80-BCCD-721D9B6235EF}.htm b/files/{C652C305-E5FC-4C80-BCCD-721D9B6235EF}.htm index ac6fcd3e..3d4b2bfb 100644 --- a/files/{C652C305-E5FC-4C80-BCCD-721D9B6235EF}.htm +++ b/files/{C652C305-E5FC-4C80-BCCD-721D9B6235EF}.htm @@ -312,7 +312,7 @@ p,ul,ol /* Paragraph Style */


There are always the following blocks:


-

Sprite Data                Block 2        

+

Sprite Data                Block 2


I've yet to see map a game that does not use this block solely for sprite data.  It will contain the "ID" numbers for all the items currently on the screen.  Simply put, this data is precisely the data you see on the screen.  For making TAS movies this is not useful data.  If you are using cheat search and have narrowed it down your search to a few values, you can immediately discard any $02xx values.


diff --git a/files/{CE13161D-517E-4E30-8502-F98D92F44C8E}.htm b/files/{CE13161D-517E-4E30-8502-F98D92F44C8E}.htm index 37b9d5cc..54cb5ffa 100644 --- a/files/{CE13161D-517E-4E30-8502-F98D92F44C8E}.htm +++ b/files/{CE13161D-517E-4E30-8502-F98D92F44C8E}.htm @@ -157,14 +157,14 @@ p,ul,ol /* Paragraph Style */


Setting up controllers


-

On the pull down menus, you can select the device you want to be emulated on input ports 1 and 2 (game pad, zapper, pad, paddle).

-

The device currently being emulated on each port is listed above the drop down list; loading certain games will override your settings, but only temporarily. 

+

On the pull down menus, you can select the device you want to be emulated on input ports 1 and 2 (game pad, zapper, pad, paddle). If you check the box labeled "Attach four-score(implies four gamepads)", you won't be able to select any of these options, because the four-score allowed someone to use 2 extra controllers.

+

The device currently being emulated on each port is listed above the drop down list; loading certain games will override your settings, but only temporarily.


To bind these controls to specific keys/joystick controls use the  "configure" the device listed above each drop-down list.


Zapper / Arkanoid Paddle


-

Most Zapper NES games expect the Zapper to be plugged into port 2. and most VS Unisystem games expect the Zapper to be plugged into port 1.

+

Most Zapper NES games expect the Zapper to be plugged into port 2. and most VS Unisystem games expect the Zapper to be plugged into port 1.


The left mouse button is the emulated trigger button for the Zapper. The right mouse button is also emulated as the trigger, but as long as you have the right mouse button held down, no color detection will take place, which is effectively like pulling the trigger while the Zapper is pointed away from the television screen. Note that you must hold the right button down for a short time to have the desired effect.


@@ -180,9 +180,13 @@ p,ul,ol /* Paragraph Style */


In addition to the traditional famicom controller, FCEUX can emulate the Famicom version of the Arkanoid controller, the "Space Shadow" gun, the Famicom 4-player adapter, the Family Keyboard, the HyperShot controller, the Mahjong controller, the Oeka Kids tablet, the Quiz King buzzers, the Family Trainer, and the Barcode World barcode reader.


+

Replace Port 2 Start With Microphone

+


+

Checking this box will replace the Start button used by controller 2 with the microphone option found on the famicom. Pressing the Microphone button is like blowing or yelling into it on the console equipment. The Port 2 controller used for the Famicom included a microphone and a volume control in place of the Start and Select buttons. This option isn't automatically detected, so it has to be manually enabled by the user. Movie files may also enable and use this feature. Both Famicom Cartridges and Famicom Disks have made use of this feature, such as both the cartridge and disk version of Zelda 1, Hikari Shinwa, and Takeshi no Chosenjo. Games other than those listed here use this feature.

+


Input Presets


-

This feature allow you to set the current input configuration to one of three presets.  This gives you the option to quickly change from one input configuration to another (such as toggling between 1  or 2 controllers and/or toggling from controller 2 being bound to controller 1 or having its own controls).

+

This feature allow you to set the current input configuration to one of three presets.  This gives you the option to quickly change from one input configuration to another (such as toggling between 1 or 2 controllers and/or toggling from controller 2 being bound to controller 1 or having its own controls).


To assign the current input configuration to a preset press the down arrow next to one of the presets.  To assign the preset as the current input configuration press the up arrow or use the hotkey assigned to that specific preset.  Preset hotkeys can be assigned in the Map Hotkeys menu.


diff --git a/files/{D3F1816D-0770-4257-98D2-A21456B07D28}.htm b/files/{D3F1816D-0770-4257-98D2-A21456B07D28}.htm index d8b726f2..9b9dcb40 100644 --- a/files/{D3F1816D-0770-4257-98D2-A21456B07D28}.htm +++ b/files/{D3F1816D-0770-4257-98D2-A21456B07D28}.htm @@ -208,7 +208,7 @@ p,ul,ol /* Paragraph Style */

Lua Functions List

Lua Functions


-

The following functions are available in FCEUX:

+

The following functions are available in FCEUX, in addition to standard LUA capabilities:



Emu library

@@ -275,13 +275,15 @@ p,ul,ol /* Paragraph Style */


Returns true if emulation has started, or false otherwise. Certain operations such as using savestates are invalid to attempt before emulation has started. You probably won't need to use this function unless you want to make your script extra-robust to being started too early.


-

bool emu.getreadonly()

+

bool emu.readonly()

+

Alias: movie.readonly


Returns whether the emulator is in read-only state. 


While this variable only applies to movies, it is stored as a global variable and can be modified even without a movie loaded.  Hence, it is in the emu library rather than the movie library.


emu.setreadonly(bool state)

+

Alias: movie.setreadonly


Sets the read-only status to read-only if argument is true and read+write if false.

Note: This might result in an error if the medium of the movie file is not writeable (such as in an archive file).

@@ -308,6 +310,36 @@ p,ul,ol /* Paragraph Style */


Note that restarting a script counts as stopping it and then starting it again, so doing so (either by clicking "Restart" or by editing the script while it is running) will trigger the callback. Note also that returning from a script generally does NOT count as stopping (because your script is still running or waiting to run its callback functions and thus does not stop... see here for more information), even if the exit callback is the only one you have registered.


+

bool emu.addgamegenie(string str)

+


+

Adds a Game Genie code to the Cheats menu. Returns false and an error message if the code can't be decoded. Returns false if the code couldn't be added. Returns true if the code already existed, or if it was added.

+


+

Usage: emu.addgamegenie("NUTANT")

+


+

Note that the Cheats Dialog Box won't show the code unless you close and reopen it.

+


+

bool emu.delgamegenie(string str)

+


+

Removes a Game Genie code from the Cheats menu. Returns false and an error message if the code can't be decoded. Returns false if the code couldn't be deleted. Returns true if the code didn't exist, or if it was deleted.

+


+

Usage: emu.delgamegenie("NUTANT")

+


+

Note that the Cheats Dialog Box won't show the code unless you close and reopen it.

+


+

emu.print(string str)

+


+

Puts a message into the Output Console area of the Lua Script control window. Useful for displaying usage instructions to the user when a script gets run.

+


+

emu.getscreenpixel(int x, int y, bool getemuscreen)

+


+

Returns the separate RGB components of the given screen pixel, and the palette. Can be 0-255 by 0-239, but NTSC only displays 0-255 x 8-231 of it. If getemuscreen is false, this gets background colors from either the screen pixel or the LUA pixels set, but LUA data may not match the information used to put the data to the screen. If getemuscreen is true, this gets background colors from anything behind an LUA screen element.

+


+

Usage is local r,g,b,palette = emu.getscreenpixel(5, 5, false) to retrieve the current red/green/blue colors and palette value of the pixel at 5x5.

+


+

Palette value can be 0-63, or 254 if there was an error.

+


+

You can avoid getting LUA data by putting the data into a function, and feeding the function name to emu.registerbefore.

+


FCEU library


The FCEU library is the same as the emu library. It is left in for backwards compatibility. However, the emu library is preferred.

@@ -315,6 +347,7 @@ p,ul,ol /* Paragraph Style */

ROM Library


rom.readbyte(int address)

+

rom.readbyteunsigned(int address)


Get an unsigned byte from the actual ROM file at the given address. 


@@ -322,19 +355,14 @@ p,ul,ol /* Paragraph Style */


rom.readbytesigned(int address)


-

Get a signed byte from the actual ROM failed at the given address. Returns a byte that is signed.

-


-

This includes the header! It's the same as opening the file in a hex-editor.

-


-

rom.readbyteunsigned(int address)

-


-

Get a signed byte from the actual ROM failed at the given address. Returns a byte that is signed.

+

Get a signed byte from the actual ROM file at the given address. Returns a byte that is signed.


This includes the header! It's the same as opening the file in a hex-editor.


Memory Library


memory.readbyte(int address)

+

memory.readbyteunsigned(int address)


Get an unsigned byte from the RAM at the given address. Returns a byte regardless of emulator. The byte will always be positive.


@@ -346,10 +374,6 @@ p,ul,ol /* Paragraph Style */


Get a signed byte from the RAM at the given address. Returns a byte regardless of emulator. The most significant bit will serve as the sign.


-

memory.readbyteunsigned(int address)

-


-

Get an unsigned byte from the RAM at the given address. Returns a byte regardless of emulator. The byte will always be positive.

-


memory.writebyte(int address, int value)


Write the value to the RAM at the given address. The value is modded with 256 before writing (so writing 257 will actually write 1). Negative values allowed.

@@ -394,6 +418,7 @@ p,ul,ol /* Paragraph Style */

Joypad Library


table joypad.get(int player)

+

table joypad.read(int player)


Returns a table of every game button, where each entry is true if that button is currently held (as of the last time the emulation checked), or false if it is not held. This takes keyboard inputs, not Lua. The table keys look like this (case sensitive):


@@ -401,15 +426,20 @@ p,ul,ol /* Paragraph Style */


Where a Lua truthvalue true means that the button is set, false means the button is unset. Note that only "false" and "nil" are considered a false value by Lua.  Anything else is true, even the number 0.


+

joypad.read left in for backwards compatibility with older versions of FCEU/FCEUX.

+


table joypad.getdown(int player)

+

table joypad.readdown(int player)


Returns a table of only the game buttons that are currently held. Each entry is true if that button is currently held (as of the last time the emulation checked), or nil if it is not held.


table joypad.getup(int player)

+

table joypad.readup(int player)


Returns a table of only the game buttons that are not currently held. Each entry is nil if that button is currently held (as of the last time the emulation checked), or false if it is not held.


joypad.set(int player, table input)

+

joypad.write(int player, table input)


Set the inputs for the given player. Table keys look like this (case sensitive):


@@ -425,13 +455,7 @@ p,ul,ol /* Paragraph Style */


nil and "invert" exists so the script can control individual buttons of the controller without entirely blocking the user from having any control. Perhaps there is a process which can be automated by the script, like an optimal firing pattern, but the user still needs some manual control, such as moving the character around.


-

table joypad.read()

-


-

A alias of joypad.get().  Left in for backwards compatibility with older versions of FCEU/FCEUX.

-


-

joypad.write()

-


-

A alias of joypad.set().  Left in for backwards compatibility with older versions of FCEU/FCEUX.

+

joypad.write left in for backwards compatibility with older versions of FCEU/FCEUX.



Zapper Library

@@ -452,19 +476,29 @@ p,ul,ol /* Paragraph Style */

Input Library


table input.get()

+

table input.read()


Reads input from keyboard and mouse. Returns pressed keys and the position of mouse in pixels on game screen.  The function returns a table with at least two properties; table.xmouse and table.ymouse.  Additionally any of these keys will be set to true if they were held at the time of executing this function:

leftclick, rightclick, middleclick, capslock, numlock, scrolllock, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, Z, F1, F2, F3, F4, F5, F6,  F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, backspace, tab, enter, shift, control, alt, pause, escape, space, pageup, pagedown, end, home, left, up, right, down, numpad0, numpad1, numpad2, numpad3, numpad4, numpad5, numpad6, numpad7, numpad8, numpad9, numpad*, insert, delete, numpad+, numpad-, numpad., numpad/, semicolon, plus, minus, comma, period, slash, backslash, tilde, quote, leftbracket, rightbracket.


+

string input.popup

+

Alias: gui.popup

+


+

Requests input from the user using a multiple-option message box. See gui.popup for complete usage and returns.

+


Savestate Library


-

object savestate.create(int slot = nil)

+

object savestate.object(int slot = nil)


-

Create a new savestate object. Optionally you can save the current state to one of the predefined slots (0...9), otherwise you'll create an "anonymous" savestate.

+

Create a new savestate object. Optionally you can save the current state to one of the predefined slots(1-10) using the range 1-9 for slots 1-9, and 10 for 0, QWERTY style. Using no number will create an "anonymous" savestate.

Note that this does not actually save the current state! You need to create this value and pass it on to the load and save functions in order to save it.


Anonymous savestates are temporary, memory only states. You can make them persistent by calling memory.persistent(state). Persistent anonymous states are deleted from disk once the script exits.


+

object savestate.create(int slot = nil)

+


+

savestate.create is identical to savestate.object, except for the numbering for predefined slots(1-10, 1 refers to slot 0, 2-10 refer to 1-9). It's being left in for compatibility with older scripts, and potentially for platforms with different internal predefined slot numbering.

+


savestate.save(object savestate)


Save the current state object to the given savestate. The argument is the result of savestate.create(). You can load this state back up by calling savestate.load(savestate) on the same object.

@@ -493,9 +527,12 @@ p,ul,ol /* Paragraph Style */


savestate.loadscriptdata(int location)


+

Accuracy not yet confirmed.

+


+

Intended Function, according to snes9x LUA documentation:

+

Returns the data associated with the given savestate (data that was earlier returned by a registered save callback) without actually loading the rest of that savestate or calling any callbacks. location should be a save slot number.



-

       

Movie Library


bool movie.active()

@@ -512,6 +549,7 @@ p,ul,ol /* Paragraph Style */


- "record"

- "playback"

+

- "finished"

- nil


movie.rerecordcounting(bool counting)

@@ -528,14 +566,20 @@ p,ul,ol /* Paragraph Style */

Returns the total number of frames of the current movie. Throws a Lua error if no movie is loaded.


string movie.name()

+

string movie.getname()


-

Returns the filename of the current movie. Throws a Lua error if no movie is loaded.

+

Returns the filename of the current movie with path. Throws a Lua error if no movie is loaded.

+


+

movie.getfilename()

+


+

Returns the filename of the current movie with no path. Throws a Lua error if no movie is loaded.


movie.rerecordcount()


Returns the rerecord count of the current movie. Throws a Lua error if no movie is loaded.


movie.replay()

+

movie.playbeginning()


Performs the Play from Beginning function. Movie mode is switched to read-only and the movie loaded will begin playback from frame 1.


@@ -543,19 +587,17 @@ p,ul,ol /* Paragraph Style */


bool movie.readonly()

bool movie.getreadonly()

-


-

These have the same effect.

+

Alias: emu.getreadonly


-

Same as emu.getreadonly()

FCEUX keeps the read-only status even without a movie loaded.


Returns whether the emulator is in read-only state. 


-

While this variable only applies to movies, it is stored as a global variable and can be modified even without a        movie loaded.  Hence, it is in the emu library rather than the movie library.

+

While this variable only applies to movies, it is stored as a global variable and can be modified even without a movie loaded.  Hence, it is in the emu library rather than the movie library.


movie.setreadonly(bool state)

+

Alias: emu.setreadonly


-

Same as emu.setreadonly()

FCEUX keeps the read-only status even without a movie loaded.


Sets the read-only status to read-only if argument is true and read+write if false.

@@ -571,6 +613,18 @@ p,ul,ol /* Paragraph Style */


Returns true if there is a movie loaded and in play mode.


+

bool movie.ispoweron()

+


+

Returns true if the movie recording or loaded started from 'Start'.

+

Returns false if the movie uses a save state.

+

Opposite of movie.isfromsavestate()

+


+

bool movie.isfromsavestate()

+


+

Returns true if the movie recording or loaded started from 'Now'.

+

Returns false if the movie was recorded from a reset.

+

Opposite of movie.ispoweron()

+


string movie.name()


If a movie is loaded it returns the name of the movie, else it throws an error.

@@ -582,28 +636,47 @@ p,ul,ol /* Paragraph Style */

GUI Library


gui.pixel(int x, int y, type color)

+

gui.drawpixel(int x, int y, type color)

+

gui.setpixel(int x, int y, type color)

+

gui.writepixel(int x, int y, type color)


Draw one pixel of a given color at the given position on the screen. See drawing notes and color notes at the bottom of the page. 


+

gui.getpixel(int x, int y)

+


+

Returns the separate RGBA components of the given pixel set by gui.pixel. This only gets LUA pixels set, not background colors.

+


+

Usage is local r,g,b,a = gui.getpixel(5, 5) to retrieve the current red/green/blue/alpha values of the LUA pixel at 5x5.

+


+

See emu.getscreenpixel() for an emulator screen variant.

+


gui.line(int x1, int y1, int x2, int y2 [, color [, skipfirst]])

+

gui.drawline(int x1, int y1, int x2, int y2 [, color [, skipfirst]])


Draws a line between the two points. The x1,y1 coordinate specifies one end of the line segment, and the x2,y2 coordinate specifies the other end. If skipfirst is true then this function will not draw anything at the pixel x1,y1, otherwise it will. skipfirst is optional and defaults to false. The default color for the line is solid white, but you may optionally override that using a color of your choice. See also drawing notes and color notes at the bottom of the page.


gui.box(int x1, int y1, int x2, int y2 [, fillcolor [, outlinecolor]]))

+

gui.drawbox(int x1, int y1, int x2, int y2 [, fillcolor [, outlinecolor]]))

+

gui.rect(int x1, int y1, int x2, int y2 [, fillcolor [, outlinecolor]]))

+

gui.drawrect(int x1, int y1, int x2, int y2 [, fillcolor [, outlinecolor]]))


Draws a rectangle between the given coordinates of the emulator screen for one frame. The x1,y1 coordinate specifies any corner of the rectangle (preferably the top-left corner), and the x2,y2 coordinate specifies the opposite corner.


The default color for the box is transparent white with a solid white outline, but you may optionally override those using colors of your choice. Also see drawing notes and color notes.


-

gui.text(int x, int y, string str)

+

gui.text(int x, int y, string str [, textcolor [, backcolor]])

+

gui.drawtext(int x, int y, string str [, textcolor [, backcolor]])


-

Draws a given string at the given position.

+

Draws a given string at the given position. textcolor and backcolor are optional. See 'on colors' at the end of this page for information. Using nil as the input or not including an optional field will make it use the default.


gui.parsecolor(color)


Returns the separate RGBA components of the given color.

For example, you can say local r,g,b,a = gui.parsecolor('orange') to retrieve the red/green/blue values of the preset color orange. (You could also omit the a in cases like this.) This uses the same conversion method that FCEUX uses internally to support the different representations of colors that the GUI library uses. Overriding this function will not change how FCEUX interprets color values, however.


+

gui.savescreenshot()

+

Makes a screenshot of the FCEUX emulated screen, and saves it to the appropriate folder. Performs identically to pressing the Screenshot hotkey.

+


string gui.gdscreenshot()


Takes a screen shot of the image and returns it in the form of a string which can be imported by the gd library using the gd.createFromGdStr() function.

@@ -613,6 +686,8 @@ p,ul,ol /* Paragraph Style */

Warning: Storing screen shots in memory is not recommended. Memory usage will blow up pretty quick. One screen shot string eats around 230 KB of RAM.


gui.gdoverlay([int dx=0, int dy=0,] string str [, sx=0, sy=0, sw, sh] [, float alphamul=1.0])

+

gui.image([int dx=0, int dy=0,] string str [, sx=0, sy=0, sw, sh] [, float alphamul=1.0])

+

gui.drawimage([int dx=0, int dy=0,] string str [, sx=0, sy=0, sw, sh] [, float alphamul=1.0])


Draws an image on the screen. gdimage must be in truecolor gd string format.


@@ -680,17 +755,19 @@ p,ul,ol /* Paragraph Style */

A general warning about drawing is that it is always one frame behind unless you use gui.register. This is because you tell the emulator to paint something but it will actually paint it when generating the image for the next frame. So you see your painting, except it will be on the image of the next frame. You can prevent this with gui.register because it gives you a quick chance to paint before blitting.


Dimensions & color depths you can paint in:

-

320x239, 8bit color (confirm?)

+

--320x239, 8bit color (confirm?)

+

256x224, 8bit color (confirm?)


On colors


Colors can be of a few types.

Int: use the a formula to compose the color as a number (depends on color depth)

-

String: Can either be a HTML color or simple colors.

+

String: Can either be a HTML colors, simple colors, or internal palette colors.

HTML string: "#rrggbb" ("#228844") or #rrggbbaa if alpha is supported.

Simple colors: "clear", "red", "green", "blue", "white", "black", "gray", "grey", "orange", "yellow", "green", "teal", "cyan", "purple", "magenta".

Array: Example: {255,112,48,96} means {red=255, green=112, blue=48, alpha=96}

Table: Example: {r=255,g=112,b=48,a=96} means {red=255, green=112, blue=48, alpha=96}

+

Palette: Example: "P00" for Palette 00. "P3F" for palette 3F. P40-P7F are for LUA.


For transparancy use "clear".


diff --git a/files/{D6DDB3DB-500D-4DCE-8D48-10A67F896057}.htm b/files/{D6DDB3DB-500D-4DCE-8D48-10A67F896057}.htm index bbcfef2c..644a4448 100644 --- a/files/{D6DDB3DB-500D-4DCE-8D48-10A67F896057}.htm +++ b/files/{D6DDB3DB-500D-4DCE-8D48-10A67F896057}.htm @@ -76,31 +76,27 @@ a.rvts11, span.rvts11 } a.rvts11:hover { color: #0000ff; } span.rvts12 -{ - font-size: 12pt; -} -span.rvts13 { font-size: 14pt; } -span.rvts14 /* Font Style */ +span.rvts13 /* Font Style */ { font-size: 16pt; font-family: 'Tahoma', 'Geneva', sans-serif; color: #ffffff; } -span.rvts15 /* Font Style */ +span.rvts14 /* Font Style */ { font-family: 'MS Sans Serif', 'Geneva', sans-serif; color: #808080; } -span.rvts16 /* Font Style */ +span.rvts15 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; color: #c0c0c0; } -a.rvts17, span.rvts17 /* Font Style */ +a.rvts16, span.rvts16 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; @@ -147,64 +143,63 @@ p,ul,ol /* Paragraph Style */ -

Directories

+

Directories

Directory Overrides



This menu sets a default directory override for various files relating to FCEU.


-

Base Directory

+

Base Directory

sets the default directory FCEU will use.  It will be the folder that FCEU creates all the sub folders (unless they are also overridden).



-

ROMS

+

ROMS

where FCEU will look for ROMS by default.  (What folder will appear when selecting the Files > Open...)



-

Battery Saves        

+

Battery Saves

where .sav files will stored and opened from.  These files contain the battery backed SRAM used in some games (such as Dragon Warrior).



-

Save States        

+

Save States

where .fcs (savestate) files will be stored.



-

FDS BIOS ROM

+

FDS BIOS ROM

where FCEU can find disksys.rom.  disksys.rom is a required file in order to load FDS (Famicom Disk System) games.  If not specified, FCEUX will default to the base directory.



-

Screenshots        

+

Screenshots

where screen captures (.png) files will be saved.



-

Save Screenshots as "<filebase>-<x>.png"

+

Save Screenshots as "<filebase>-<x>.png"

sets how the .png files will be named.  Left unchecked, the file names will simply be 0.png, 1.png etc.  Checked adds the ROM name into the file as well (such as Double Dragon 2 (U)-0.png)



-

Cheats                

+

Cheats

where .cht files will be stored.  .cht files store the active cheats set up in Cheat Search.



-

Movies                

+

Movies

where  .fm2 files will be saved/loaded.  These files are the input files used in movie recording.



-

Memory Watch

+

Memory Watch

where memory watch files are saved/loaded.  These are used by memory watch.



-

Input Presets        

+

Input Presets

where input presets will be saved/loaded.  These are used in the presets section on the input config window.



-

Lua Scripts        

+

Lua Scripts

where Lua scripts will be saved/loaded.  These are used when using the Lua Scripting tool.



-

AVI Output

-


+

AVI Output

overrides which directory FCEUX will default to when saving a .avi file.

-

2008

-

This help file has been generated by the freeware version of HelpNDoc

+

2008

+

This help file has been generated by the freeware version of HelpNDoc

diff --git a/files/{E3064992-D632-4845-8F38-20ED1A58E4D2}.htm b/files/{E3064992-D632-4845-8F38-20ED1A58E4D2}.htm index 00e85759..7c0a6a9c 100644 --- a/files/{E3064992-D632-4845-8F38-20ED1A58E4D2}.htm +++ b/files/{E3064992-D632-4845-8F38-20ED1A58E4D2}.htm @@ -165,7 +165,7 @@ p,ul,ol /* Paragraph Style */


FCE Ultra Version History


-

What's New?

+

What's Combined In FCEUX?



Additional Chapters

diff --git a/files/{F2D1DEB3-8F0A-4394-9211-D82D466F09CC}.htm b/files/{F2D1DEB3-8F0A-4394-9211-D82D466F09CC}.htm index 57735986..202d4b8c 100644 --- a/files/{F2D1DEB3-8F0A-4394-9211-D82D466F09CC}.htm +++ b/files/{F2D1DEB3-8F0A-4394-9211-D82D466F09CC}.htm @@ -64,24 +64,28 @@ span.rvts9 /* Font Hint Italic */ font-style: italic; color: #808080; } -span.rvts10 /* Font Style */ +span.rvts10 +{ + font-family: 'Courier New', 'Courier', monospace; +} +span.rvts11 /* Font Style */ { font-size: 16pt; font-family: 'Tahoma', 'Geneva', sans-serif; color: #ffffff; } -span.rvts11 /* Font Style */ +span.rvts12 /* Font Style */ { font-family: 'MS Sans Serif', 'Geneva', sans-serif; color: #808080; } -span.rvts12 /* Font Style */ +span.rvts13 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; color: #c0c0c0; } -a.rvts13, span.rvts13 /* Font Style */ +a.rvts14, span.rvts14 /* Font Style */ { font-family: 'Verdana', 'Geneva', sans-serif; font-style: italic; @@ -128,51 +132,51 @@ p,ul,ol /* Paragraph Style */ -

6502 CPU

-

#

-

# $Id: 6502_cpu.txt,v 1.1.1.1 2004/08/29 01:29:35 bryan Exp $

-

#

-

# This file is part of Commodore 64 emulator

-

#      and Program Development System.

-

#

-

# See README for copyright notice

-

#

-

# This file contains documentation for 6502/6510/8500/8502 instruction set.

-

#

-

#

-

# Written by

-

#   John West       (john@ucc.gu.uwa.edu.au)

-

#   Marko MŠkelŠ    (msmakela@kruuna.helsinki.fi)

-

#

-

#

-

# $Log: 6502_cpu.txt,v $

-

# Revision 1.1.1.1  2004/08/29 01:29:35  bryan

-

# no message

-

#

-

# Revision 1.1  2002/05/21 00:42:27  xodnizel

-

# updates

-

#

-

# Revision 1.8  1994/06/03  19:50:04  jopi

-

# Patchlevel 2

-

#

-

# Revision 1.7  1994/04/15  13:07:04  jopi

-

# 65xx Register descriptions added

-

#

-

# Revision 1.6  1994/02/18  16:09:36  jopi

-

#

-

# Revision 1.5  1994/01/26  16:08:37  jopi

-

# X64 version 0.2 PL 1

-

#

-

# Revision 1.4  1993/11/10  01:55:34  jopi

-

#

-

# Revision 1.3  93/06/21  13:37:18  jopi

-

#  X64 version 0.2 PL 0

-

#

-

# Revision 1.2  93/06/21  13:07:15  jopi

-

# *** empty log message ***

-

#

-

#

-


+

6502 CPU

+

#

+

# $Id: 6502_cpu.txt,v 1.1.1.1 2004/08/29 01:29:35 bryan Exp $

+

#

+

# This file is part of Commodore 64 emulator

+

#      and Program Development System.

+

#

+

# See README for copyright notice

+

#

+

# This file contains documentation for 6502/6510/8500/8502 instruction set.

+

#

+

#

+

# Written by

+

#   John West       (john@ucc.gu.uwa.edu.au)

+

#   Marko MŠkelŠ    (msmakela@kruuna.helsinki.fi)

+

#

+

#

+

# $Log: 6502_cpu.txt,v $

+

# Revision 1.1.1.1  2004/08/29 01:29:35  bryan

+

# no message

+

#

+

# Revision 1.1  2002/05/21 00:42:27  xodnizel

+

# updates

+

#

+

# Revision 1.8  1994/06/03  19:50:04  jopi

+

# Patchlevel 2

+

#

+

# Revision 1.7  1994/04/15  13:07:04  jopi

+

# 65xx Register descriptions added

+

#

+

# Revision 1.6  1994/02/18  16:09:36  jopi

+

#

+

# Revision 1.5  1994/01/26  16:08:37  jopi

+

# X64 version 0.2 PL 1

+

#

+

# Revision 1.4  1993/11/10  01:55:34  jopi

+

#

+

# Revision 1.3  93/06/21  13:37:18  jopi

+

#  X64 version 0.2 PL 0

+

#

+

# Revision 1.2  93/06/21  13:07:15  jopi

+

# *** empty log message ***

+

#

+

#

+


Note: To extract the uuencoded ML programs in this article most

       easily you may use e.g. "uud" by Edwin Kremer ,

       which extracts them all at once.

@@ -197,45 +201,45 @@ p,ul,ol /* Paragraph Style */


6510 Instructions by Addressing Modes


-

off- ++++++++++ Positive ++++++++++  ---------- Negative ----------

-

set  00      20      40      60      80      a0      c0      e0      mode

-


-

+00  BRK     JSR     RTI     RTS     NOP*    LDY     CPY     CPX     Impl/immed

-

+01  ORA     AND     EOR     ADC     STA     LDA     CMP     SBC     (indir,x)

-

+02   t       t       t       t      NOP*t   LDX     NOP*t   NOP*t     ? /immed

-

+03  SLO*    RLA*    SRE*    RRA*    SAX*    LAX*    DCP*    ISB*    (indir,x)

-

+04  NOP*    BIT     NOP*    NOP*    STY     LDY     CPY     CPX     Zeropage

-

+05  ORA     AND     EOR     ADC     STA     LDA     CMP     SBC     Zeropage

-

+06  ASL     ROL     LSR     ROR     STX     LDX     DEC     INC     Zeropage

-

+07  SLO*    RLA*    SRE*    RRA*    SAX*    LAX*    DCP*    ISB*    Zeropage

-


-

+08  PHP     PLP     PHA     PLA     DEY     TAY     INY     INX     Implied

-

+09  ORA     AND     EOR     ADC     NOP*    LDA     CMP     SBC     Immediate

-

+0a  ASL     ROL     LSR     ROR     TXA     TAX     DEX     NOP     Accu/impl

-

+0b  ANC**   ANC**   ASR**   ARR**   ANE**   LXA**   SBX**   SBC*    Immediate

-

+0c  NOP*    BIT     JMP     JMP ()  STY     LDY     CPY     CPX     Absolute

-

+0d  ORA     AND     EOR     ADC     STA     LDA     CMP     SBC     Absolute

-

+0e  ASL     ROL     LSR     ROR     STX     LDX     DEC     INC     Absolute

-

+0f  SLO*    RLA*    SRE*    RRA*    SAX*    LAX*    DCP*    ISB*    Absolute

-


-

+10  BPL     BMI     BVC     BVS     BCC     BCS     BNE     BEQ     Relative

-

+11  ORA     AND     EOR     ADC     STA     LDA     CMP     SBC     (indir),y

-

+12   t       t       t       t       t       t       t       t         ?

-

+13  SLO*    RLA*    SRE*    RRA*    SHA**   LAX*    DCP*    ISB*    (indir),y

-

+14  NOP*    NOP*    NOP*    NOP*    STY     LDY     NOP*    NOP*    Zeropage,x

-

+15  ORA     AND     EOR     ADC     STA     LDA     CMP     SBC     Zeropage,x

-

+16  ASL     ROL     LSR     ROR     STX  y) LDX  y) DEC     INC     Zeropage,x

-

+17  SLO*    RLA*    SRE*    RRA*    SAX* y) LAX* y) DCP*    ISB*    Zeropage,x

-


-

+18  CLC     SEC     CLI     SEI     TYA     CLV     CLD     SED     Implied

-

+19  ORA     AND     EOR     ADC     STA     LDA     CMP     SBC     Absolute,y

-

+1a  NOP*    NOP*    NOP*    NOP*    TXS     TSX     NOP*    NOP*    Implied

-

+1b  SLO*    RLA*    SRE*    RRA*    SHS**   LAS**   DCP*    ISB*    Absolute,y

-

+1c  NOP*    NOP*    NOP*    NOP*    SHY**   LDY     NOP*    NOP*    Absolute,x

-

+1d  ORA     AND     EOR     ADC     STA     LDA     CMP     SBC     Absolute,x

-

+1e  ASL     ROL     LSR     ROR     SHX**y) LDX  y) DEC     INC     Absolute,x

-

+1f  SLO*    RLA*    SRE*    RRA*    SHA**y) LAX* y) DCP*    ISB*    Absolute,x

-


+

off- ++++++++++ Positive ++++++++++  ---------- Negative ----------

+

set  00      20      40      60      80      a0      c0      e0      mode

+


+

+00  BRK     JSR     RTI     RTS     NOP*    LDY     CPY     CPX     Impl/immed

+

+01  ORA     AND     EOR     ADC     STA     LDA     CMP     SBC     (indir,x)

+

+02   t       t       t       t      NOP*t   LDX     NOP*t   NOP*t     ? /immed

+

+03  SLO*    RLA*    SRE*    RRA*    SAX*    LAX*    DCP*    ISB*    (indir,x)

+

+04  NOP*    BIT     NOP*    NOP*    STY     LDY     CPY     CPX     Zeropage

+

+05  ORA     AND     EOR     ADC     STA     LDA     CMP     SBC     Zeropage

+

+06  ASL     ROL     LSR     ROR     STX     LDX     DEC     INC     Zeropage

+

+07  SLO*    RLA*    SRE*    RRA*    SAX*    LAX*    DCP*    ISB*    Zeropage

+


+

+08  PHP     PLP     PHA     PLA     DEY     TAY     INY     INX     Implied

+

+09  ORA     AND     EOR     ADC     NOP*    LDA     CMP     SBC     Immediate

+

+0a  ASL     ROL     LSR     ROR     TXA     TAX     DEX     NOP     Accu/impl

+

+0b  ANC**   ANC**   ASR**   ARR**   ANE**   LXA**   SBX**   SBC*    Immediate

+

+0c  NOP*    BIT     JMP     JMP ()  STY     LDY     CPY     CPX     Absolute

+

+0d  ORA     AND     EOR     ADC     STA     LDA     CMP     SBC     Absolute

+

+0e  ASL     ROL     LSR     ROR     STX     LDX     DEC     INC     Absolute

+

+0f  SLO*    RLA*    SRE*    RRA*    SAX*    LAX*    DCP*    ISB*    Absolute

+


+

+10  BPL     BMI     BVC     BVS     BCC     BCS     BNE     BEQ     Relative

+

+11  ORA     AND     EOR     ADC     STA     LDA     CMP     SBC     (indir),y

+

+12   t       t       t       t       t       t       t       t         ?

+

+13  SLO*    RLA*    SRE*    RRA*    SHA**   LAX*    DCP*    ISB*    (indir),y

+

+14  NOP*    NOP*    NOP*    NOP*    STY     LDY     NOP*    NOP*    Zeropage,x

+

+15  ORA     AND     EOR     ADC     STA     LDA     CMP     SBC     Zeropage,x

+

+16  ASL     ROL     LSR     ROR     STX  y) LDX  y) DEC     INC     Zeropage,x

+

+17  SLO*    RLA*    SRE*    RRA*    SAX* y) LAX* y) DCP*    ISB*    Zeropage,x

+


+

+18  CLC     SEC     CLI     SEI     TYA     CLV     CLD     SED     Implied

+

+19  ORA     AND     EOR     ADC     STA     LDA     CMP     SBC     Absolute,y

+

+1a  NOP*    NOP*    NOP*    NOP*    TXS     TSX     NOP*    NOP*    Implied

+

+1b  SLO*    RLA*    SRE*    RRA*    SHS**   LAS**   DCP*    ISB*    Absolute,y

+

+1c  NOP*    NOP*    NOP*    NOP*    SHY**   LDY     NOP*    NOP*    Absolute,x

+

+1d  ORA     AND     EOR     ADC     STA     LDA     CMP     SBC     Absolute,x

+

+1e  ASL     ROL     LSR     ROR     SHX**y) LDX  y) DEC     INC     Absolute,x

+

+1f  SLO*    RLA*    SRE*    RRA*    SHA**y) LAX* y) DCP*    ISB*    Absolute,x

+


        ROR intruction is available on MC650x microprocessors after

        June, 1976.


@@ -410,9 +414,9 @@ p,ul,ol /* Paragraph Style */


-- A brief explanation about what may happen while using don't care states.


-

        ANE $8B         A = (A | #$EE) & X & #byte

-

                        same as

-

                        A = ((A & #$11 & X) | ( #$EE & X)) & #byte

+

        ANE $8B         A = (A | #$EE) & X & #byte

+

                        same as

+

                        A = ((A & #$11 & X) | ( #$EE & X)) & #byte


                        In real 6510/8502 the internal parameter #$11

                        may occasionally be #$10, #$01 or even #$00.

@@ -421,15 +425,15 @@ p,ul,ol /* Paragraph Style */

                        of the instruction.  The value probably depends

                        on the data that was left on the bus by the VIC-II.


-

        LXA $AB         C=Lehti:   A = X = ANE

-

                        Alternate: A = X = (A & #byte)

+

        LXA $AB         C=Lehti:   A = X = ANE

+

                        Alternate: A = X = (A & #byte)


                        TXA and TAX have to be responsible for these.


-

        SHA $93,$9F     Store (A & X & (ADDR_HI + 1))

-

        SHX $9E         Store (X & (ADDR_HI + 1))

-

        SHY $9C         Store (Y & (ADDR_HI + 1))

-

        SHS $9B         SHA and TXS, where X is replaced by (A & X).

+

        SHA $93,$9F     Store (A & X & (ADDR_HI + 1))

+

        SHX $9E         Store (X & (ADDR_HI + 1))

+

        SHY $9C         Store (Y & (ADDR_HI + 1))

+

        SHS $9B         SHA and TXS, where X is replaced by (A & X).


                        Note: The value to be stored is copied also

                        to ADDR_HI if page boundary is crossed.

@@ -454,7 +458,7 @@ p,ul,ol /* Paragraph Style */

More fortunate is its opposite, 'LAX' which just loads a byte

simultaneously into both A and X.


-

        $6B  ARR

+

        $6B  ARR


This instruction seems to be a harmless combination of AND and ROR at

first sight, but it turns out that it affects the V flag and also has

@@ -492,36 +496,36 @@ p,ul,ol /* Paragraph Style */

To help you understand this description, here is a C routine that

illustrates the ARR operation in Decimal mode:


-

        unsigned

-

           A,  /* Accumulator */

-

           AL, /* low nybble of accumulator */

-

           AH, /* high nybble of accumulator */

-


-

           C,  /* Carry flag */

-

           Z,  /* Zero flag */

-

           V,  /* oVerflow flag */

-

           N,  /* Negative flag */

-


-

           t,  /* temporary value */

-

           s;  /* value to be ARRed with Accumulator */

-


-

        t = A & s;                      /* Perform the AND. */

-


-

        AH = t >> 4;                    /* Separate the high */

-

        AL = t & 15;                    /* and low nybbles. */

-


-

        N = C;                          /* Set the N and */

-

        Z = !(A = (t >> 1) | (C << 7)); /* Z flags traditionally */

-

        V = (t ^ A) & 64;               /* and V flag in a weird way. */

-


-

        if (AL + (AL & 1) > 5)          /* BCD "fixup" for low nybble. */

-

          A = (A & 0xF0) | ((A + 6) & 0xF);

-


-

        if (C = AH + (AH & 1) > 5)      /* Set the Carry flag. */

-

          A = (A + 0x60) & 0xFF;        /* BCD "fixup" for high nybble. */

-


-

        $CB  SBX   X <- (A & X) - Immediate

-


+

        unsigned

+

           A,  /* Accumulator */

+

           AL, /* low nybble of accumulator */

+

           AH, /* high nybble of accumulator */

+


+

           C,  /* Carry flag */

+

           Z,  /* Zero flag */

+

           V,  /* oVerflow flag */

+

           N,  /* Negative flag */

+


+

           t,  /* temporary value */

+

           s;  /* value to be ARRed with Accumulator */

+


+

        t = A & s;                      /* Perform the AND. */

+


+

        AH = t >> 4;                    /* Separate the high */

+

        AL = t & 15;                    /* and low nybbles. */

+


+

        N = C;                          /* Set the N and */

+

        Z = !(A = (t >> 1) | (C << 7)); /* Z flags traditionally */

+

        V = (t ^ A) & 64;               /* and V flag in a weird way. */

+


+

        if (AL + (AL & 1) > 5)          /* BCD "fixup" for low nybble. */

+

          A = (A & 0xF0) | ((A + 6) & 0xF);

+


+

        if (C = AH + (AH & 1) > 5)      /* Set the Carry flag. */

+

          A = (A + 0x60) & 0xFF;        /* BCD "fixup" for high nybble. */

+


+

        $CB  SBX   X <- (A & X) - Immediate

+


The 'SBX' ($CB) may seem to be very complex operation, even though it

is a combination of the subtraction of accumulator and parameter, as

in the 'CMP' instruction, and the command 'DEX'. As a result, both A

@@ -534,23 +538,23 @@ p,ul,ol /* Paragraph Style */


Proof:


-

begin 644 vsbx

-

M`0@9$,D'GL(H-#,IJC(U-JS"*#0T*:HR-@```*D`H#V1*Z`_D2N@09$KJ0>%

-

M^QBE^VEZJ+$KH#F1*ZD`2"BI`*(`RP`(:-B@.5$K*4#P`E@`H#VQ*SAI`)$K

-

JD-Z@/[$K:0"1*Y#4J2X@TO\XH$&Q*VD`D2N0Q,;[$+188/_^]_:_OK>V

-

`

-

end

-


-

and

-


-

begin 644 sbx

-

M`0@9$,D'GL(H-#,IJC(U-JS"*#0T*:HR-@```'BI`*!-D2N@3Y$KH%&1*ZD#

-

MA?L8I?M*2)`#J1@LJ3B@29$K:$J0`ZGX+*G8R)$K&/BXJ?2B8\L)AOP(:(7]

-

MV#B@3;$KH$\Q*Z!1\2L(1?SP`0!H1?TIM]#XH$VQ*SAI`)$KD,N@3[$K:0"1

-

9*Y#!J2X@TO\XH%&Q*VD`D2N0L<;[$))88-#X

-

`

-

end

-


+

begin 644 vsbx

+

M`0@9$,D'GL(H-#,IJC(U-JS"*#0T*:HR-@```*D`H#V1*Z`_D2N@09$KJ0>%

+

M^QBE^VEZJ+$KH#F1*ZD`2"BI`*(`RP`(:-B@.5$K*4#P`E@`H#VQ*SAI`)$K

+

JD-Z@/[$K:0"1*Y#4J2X@TO\XH$&Q*VD`D2N0Q,;[$+188/_^]_:_OK>V

+

`

+

end

+


+

and

+


+

begin 644 sbx

+

M`0@9$,D'GL(H-#,IJC(U-JS"*#0T*:HR-@```'BI`*!-D2N@3Y$KH%&1*ZD#

+

MA?L8I?M*2)`#J1@LJ3B@29$K:$J0`ZGX+*G8R)$K&/BXJ?2B8\L)AOP(:(7]

+

MV#B@3;$KH$\Q*Z!1\2L(1?SP`0!H1?TIM]#XH$VQ*SAI`)$KD,N@3[$K:0"1

+

9*Y#!J2X@TO\XH%&Q*VD`D2N0L<;[$))88-#X

+

`

+

end

+


These test programs show if your machine is compatible with ours

regarding the opcode $CB. The first test, vsbx, proves that SBX does

not affect the V flag. The latter one, sbx, proves the rest of our

@@ -581,10 +585,10 @@ p,ul,ol /* Paragraph Style */

language monitor, as it makes use of the BRK instruction. The result

tables will be written on pages $C2 and $C3.


-

begin 644 sbx-c100

-

M`,%XH`",#L&,$,&,$L&XJ8*B@LL7AOL(:(7\N#BM#L$M$,'M$L$(Q?OP`B@`

-

M:$7\\`,@4,'N#L'0U.X0P=#/SB#0[A+!T,<``````````````)BJ\!>M#L$M

-

L$,'=_\'0":T2P=W_PM`!8,K0Z:T.P2T0P9D`PID`!*T2P9D`PYD`!

+

begin 644 sbx-c100

+

M`,%XH`",#L&,$,&,$L&XJ8*B@LL7AOL(:(7\N#BM#L$M$,'M$L$(Q?OP`B@`

+

M:$7\\`,@4,'N#L'0U.X0P=#/SB#0[A+!T,<``````````````)BJ\!>M#L$M

+

L$,'=_\'0":T2P=W_PM`!8,K0Z:T.P2T0P9D`PID`!*T2P9D`PYD`!


Other undocumented instructions usually cause two preceding opcodes

being executed. However 'NOP' seems to completely disappear from 'SBC'

@@ -676,11 +680,11 @@ p,ul,ol /* Paragraph Style */


Register selection for load and store


-

   bit1 bit0     A  X  Y

-

    0    0             x

-

    0    1          x

-

    1    0       x

-

    1    1       x  x

+

   bit1 bit0     A  X  Y

+

    0    0             x

+

    0    1          x

+

    1    0       x

+

    1    1       x  x


So, A and X are selected by bits 1 and 0 respectively, while

~(bit1|bit0) enables Y.

@@ -705,39 +709,39 @@ p,ul,ol /* Paragraph Style */

how it can do that all in a single cycle. Here's a C code version of

the instruction:


-

        unsigned

-

           A,  /* Accumulator */

-

           AL, /* low nybble of accumulator */

-

           AH, /* high nybble of accumulator */

-


-

           C,  /* Carry flag */

-

           Z,  /* Zero flag */

-

           V,  /* oVerflow flag */

-

           N,  /* Negative flag */

-


-

           s;  /* value to be added to Accumulator */

-


-

        AL = (A & 15) + (s & 15) + C;         /* Calculate the lower nybble. */

-


-

        AH = (A >> 4) + (s >> 4) + (AL > 15); /* Calculate the upper nybble. */

-


-

        if (AL > 9) AL += 6;                  /* BCD fixup for lower nybble. */

-


-

        Z = ((A + s + C) & 255 != 0);         /* Zero flag is set just

-

                                                 like in Binary mode. */

-


-

        /* Negative and Overflow flags are set with the same logic than in

-

           Binary mode, but after fixing the lower nybble. */

-


-

        N = (AH & 8 != 0);

-

        V = ((AH << 4) ^ A) & 128 && !((A ^ s) & 128);

-


-

        if (AH > 9) AH += 6;                  /* BCD fixup for upper nybble. */

-


-

        /* Carry is the only flag set after fixing the result. */

-


-

        C = (AH > 15);

-

        A = ((AH << 4) | (AL & 15)) & 255;

+

        unsigned

+

           A,  /* Accumulator */

+

           AL, /* low nybble of accumulator */

+

           AH, /* high nybble of accumulator */

+


+

           C,  /* Carry flag */

+

           Z,  /* Zero flag */

+

           V,  /* oVerflow flag */

+

           N,  /* Negative flag */

+


+

           s;  /* value to be added to Accumulator */

+


+

        AL = (A & 15) + (s & 15) + C;         /* Calculate the lower nybble. */

+


+

        AH = (A >> 4) + (s >> 4) + (AL > 15); /* Calculate the upper nybble. */

+


+

        if (AL > 9) AL += 6;                  /* BCD fixup for lower nybble. */

+


+

        Z = ((A + s + C) & 255 != 0);         /* Zero flag is set just

+

                                                 like in Binary mode. */

+


+

        /* Negative and Overflow flags are set with the same logic than in

+

           Binary mode, but after fixing the lower nybble. */

+


+

        N = (AH & 8 != 0);

+

        V = ((AH << 4) ^ A) & 128 && !((A ^ s) & 128);

+


+

        if (AH > 9) AH += 6;                  /* BCD fixup for upper nybble. */

+


+

        /* Carry is the only flag set after fixing the result. */

+


+

        C = (AH > 15);

+

        A = ((AH << 4) | (AL & 15)) & 255;


  The C flag is set as the quiche eaters expect, but the N and V flags

are set after fixing the lower nybble but before fixing the upper one.

@@ -748,14 +752,14 @@ p,ul,ol /* Paragraph Style */

       Decimal mode, and aborts with BRK if anything breaks this theory.

       If everything goes well, it ends in RTS.


-

begin 600 dadc

-

M 0@9",D'GL(H-#,IJC(U-JS"*#0T*:HR-@   'BI&*  A/N$_$B@+)$KH(V1

-

M*Q@(I?PI#X7]I?LI#V7]R0J0 FD%J"D/A?VE^RGP9?PI\ C $) ":0^JL @H

-

ML ?)H) &""@X:5\X!?V%_0AH*3W@ ! ""8"HBD7[$ JE^T7\, 28"4"H**7[

-

M9?S0!)@) J@8N/BE^V7\V A%_= G:(3]1?W0(.;[T(?F_-"#:$D8\ )88*D=

-

0&&4KA?NI &4LA?RI.&S[  A%

-


-

end

+

begin 600 dadc

+

M 0@9",D'GL(H-#,IJC(U-JS"*#0T*:HR-@   'BI&*  A/N$_$B@+)$KH(V1

+

M*Q@(I?PI#X7]I?LI#V7]R0J0 FD%J"D/A?VE^RGP9?PI\ C $) ":0^JL @H

+

ML ?)H) &""@X:5\X!?V%_0AH*3W@ ! ""8"HBD7[$ JE^T7\, 28"4"H**7[

+

M9?S0!)@) J@8N/BE^V7\V A%_= G:(3]1?W0(.;[T(?F_-"#:$D8\ )88*D=

+

0&&4KA?NI &4LA?RI.&S[  A%

+


+

end


  All programs in this chapter have been successfully tested on a Vic20

and a Commodore 64 and a Commodore 128D in C64 mode. They should run on

@@ -768,45 +772,45 @@ p,ul,ol /* Paragraph Style */


Proof:


-

begin 600 dsbc-cmp-flags

-

M 0@9",D'GL(H-#,IJC(U-JS"*#0T*:HR-@   'B@ (3[A/RB XH8:66HL2N@

-

M09$KH$R1*XII::BQ*Z!%D2N@4)$K^#BXI?OE_-@(:(7].+BE^^7\"&A%_? !

-

5 .;[T./F_-#?RA"_8!@X&#CEY<7%

-


-

end

+

begin 600 dsbc-cmp-flags

+

M 0@9",D'GL(H-#,IJC(U-JS"*#0T*:HR-@   'B@ (3[A/RB XH8:66HL2N@

+

M09$KH$R1*XII::BQ*Z!%D2N@4)$K^#BXI?OE_-@(:(7].+BE^^7\"&A%_? !

+

5 .;[T./F_-#?RA"_8!@X&#CEY<7%

+


+

end


  The only difference in SBC's operation in decimal mode from binary mode

is the result-fixup:


-

        unsigned

-

           A,  /* Accumulator */

-

           AL, /* low nybble of accumulator */

-

           AH, /* high nybble of accumulator */

-


-

           C,  /* Carry flag */

-

           Z,  /* Zero flag */

-

           V,  /* oVerflow flag */

-

           N,  /* Negative flag */

-


-

           s;  /* value to be added to Accumulator */

-


-

        AL = (A & 15) - (s & 15) - !C;        /* Calculate the lower nybble. */

-


-

        if (AL & 16) AL -= 6;                 /* BCD fixup for lower nybble. */

-


-

        AH = (A >> 4) - (s >> 4) - (AL & 16); /* Calculate the upper nybble. */

-


-

        if (AH & 16) AH -= 6;                 /* BCD fixup for upper nybble. */

-


-

        /* The flags are set just like in Binary mode. */

-


-

        C = (A - s - !C) & 256 != 0;

-

        Z = (A - s - !C) & 255 != 0;

-

        V = ((A - s - !C) ^ s) & 128 && (A ^ s) & 128;

-

        N = (A - s - !C) & 128 != 0;

-


-

        A = ((AH << 4) | (AL & 15)) & 255;

-


+

        unsigned

+

           A,  /* Accumulator */

+

           AL, /* low nybble of accumulator */

+

           AH, /* high nybble of accumulator */

+


+

           C,  /* Carry flag */

+

           Z,  /* Zero flag */

+

           V,  /* oVerflow flag */

+

           N,  /* Negative flag */

+


+

           s;  /* value to be added to Accumulator */

+


+

        AL = (A & 15) - (s & 15) - !C;        /* Calculate the lower nybble. */

+


+

        if (AL & 16) AL -= 6;                 /* BCD fixup for lower nybble. */

+


+

        AH = (A >> 4) - (s >> 4) - (AL & 16); /* Calculate the upper nybble. */

+


+

        if (AH & 16) AH -= 6;                 /* BCD fixup for upper nybble. */

+


+

        /* The flags are set just like in Binary mode. */

+


+

        C = (A - s - !C) & 256 != 0;

+

        Z = (A - s - !C) & 255 != 0;

+

        V = ((A - s - !C) ^ s) & 128 && (A ^ s) & 128;

+

        N = (A - s - !C) & 128 != 0;

+


+

        A = ((AH << 4) | (AL & 15)) & 255;

+


  Again Z flag is set before any BCD fixup. The N and V flags are set

at any time before fixing the high nybble. The C flag may be set in any

phase.

@@ -829,13 +833,13 @@ p,ul,ol /* Paragraph Style */

  The following program, which tests SBC's result and flags,

contains the 6502 version of the pseudo code example above.


-

begin 600 dsbc

-

M 0@9",D'GL(H-#,IJC(U-JS"*#0T*:HR-@   'BI&*  A/N$_$B@+)$KH':1

-

M*S@(I?PI#X7]I?LI#^7]L /I!1@I#ZBE_"GPA?VE^RGP"#CE_2GPL KI7RBP

-

M#ND/.+ )*+ &Z0^P NE?A/T%_87]*+BE^^7\"&BH.+CXI?OE_-@(1?W0FVB$

-

8_47]T)3F^]">YOS0FFA)&- $J3C0B%A@

-


-

end

+

begin 600 dsbc

+

M 0@9",D'GL(H-#,IJC(U-JS"*#0T*:HR-@   'BI&*  A/N$_$B@+)$KH':1

+

M*S@(I?PI#X7]I?LI#^7]L /I!1@I#ZBE_"GPA?VE^RGP"#CE_2GPL KI7RBP

+

M#ND/.+ )*+ &Z0^P NE?A/T%_87]*+BE^^7\"&BH.+CXI?OE_-@(1?W0FVB$

+

8_47]T)3F^]">YOS0FFA)&- $J3C0B%A@

+


+

end


  Obviously the undocumented instructions RRA (ROR+ADC) and ISB

(INC+SBC) have inherited also the decimal operation from the official

@@ -844,29 +848,29 @@ p,ul,ol /* Paragraph Style */

dincsbc-deccmp proves that ISB's and DCP's (DEC+CMP) flags are not

affected by the D flag.


-

begin 644 droradc

-

M`0@9",D'GL(H-#,IJC(U-JS"*#0T*:HR-@```'BI&*``A/N$_$B@+)$KH(V1

-

M*S@(I?PI#X7]I?LI#V7]R0J0`FD%J"D/A?VE^RGP9?PI\`C`$)`":0^JL`@H

-

ML`?)H)`&""@X:5\X!?V%_0AH*3W@`!`""8"HBD7[$`JE^T7\,`28"4"H**7[

-

M9?S0!)@)`J@XN/BE^R;\9_S8"$7]T"=HA/U%_=`@YOO0A>;\T(%H21CP`EA@

-

2J1T892N%^ZD`92R%_*DX;/L`

-

`

-

end

-


-

begin 644 dincsbc

-

M`0@9",D'GL(H-#,IJC(U-JS"*#0T*:HR-@```'BI&*``A/N$_$B@+)$KH':1

-

M*S@(I?PI#X7]I?LI#^7]L`/I!1@I#ZBE_"GPA?VE^RGP"#CE_2GPL`KI7RBP

-

M#ND/.+`)*+`&Z0^P`NE?A/T%_87]*+BE^^7\"&BH.+CXI?O&_.?\V`A%_="9

-

::(3]1?W0DN;[T)SF_-"8:$D8T`2I.-"&6&#\

-

`

-

end

-


-

begin 644 dincsbc-deccmp

-

M`0@9",D'GL(H-#,IJC(U-JS"*#0T*:HR-@```'B@`(3[A/RB`XH8:7>HL2N@

-

M3Y$KH%R1*XII>ZBQ*Z!3D2N@8)$KBFE_J+$KH%61*Z!BD2OX.+BE^^;\Q_S8

-

L"&B%_3BXI?OF_,?\"&A%_?`!`.;[T-_F_-#;RA"M8!@X&#CFYL;&Q\?GYP#8

-

`

-

end

+

begin 644 droradc

+

M`0@9",D'GL(H-#,IJC(U-JS"*#0T*:HR-@```'BI&*``A/N$_$B@+)$KH(V1

+

M*S@(I?PI#X7]I?LI#V7]R0J0`FD%J"D/A?VE^RGP9?PI\`C`$)`":0^JL`@H

+

ML`?)H)`&""@X:5\X!?V%_0AH*3W@`!`""8"HBD7[$`JE^T7\,`28"4"H**7[

+

M9?S0!)@)`J@XN/BE^R;\9_S8"$7]T"=HA/U%_=`@YOO0A>;\T(%H21CP`EA@

+

2J1T892N%^ZD`92R%_*DX;/L`

+

`

+

end

+


+

begin 644 dincsbc

+

M`0@9",D'GL(H-#,IJC(U-JS"*#0T*:HR-@```'BI&*``A/N$_$B@+)$KH':1

+

M*S@(I?PI#X7]I?LI#^7]L`/I!1@I#ZBE_"GPA?VE^RGP"#CE_2GPL`KI7RBP

+

M#ND/.+`)*+`&Z0^P`NE?A/T%_87]*+BE^^7\"&BH.+CXI?O&_.?\V`A%_="9

+

::(3]1?W0DN;[T)SF_-"8:$D8T`2I.-"&6&#\

+

`

+

end

+


+

begin 644 dincsbc-deccmp

+

M`0@9",D'GL(H-#,IJC(U-JS"*#0T*:HR-@```'B@`(3[A/RB`XH8:7>HL2N@

+

M3Y$KH%R1*XII>ZBQ*Z!3D2N@8)$KBFE_J+$KH%61*Z!BD2OX.+BE^^;\Q_S8

+

L"&B%_3BXI?OF_,?\"&A%_?`!`.;[T-_F_-#;RA"M8!@X&#CFYL;&Q\?GYP#8

+

`

+

end



6510 features

@@ -1027,617 +1031,617 @@ p,ul,ol /* Paragraph Style */


  Instructions accessing the stack


-

     BRK

-


-

        #  address R/W description

-

       --- ------- --- -----------------------------------------------

-

        1    PC     R  fetch opcode, increment PC

-

        2    PC     R  read next instruction byte (and throw it away),

-

                       increment PC

-

        3  $0100,S  W  push PCH on stack (with B flag set), decrement S

-

        4  $0100,S  W  push PCL on stack, decrement S

-

        5  $0100,S  W  push P on stack, decrement S

-

        6   $FFFE   R  fetch PCL

-

        7   $FFFF   R  fetch PCH

-


-

     RTI

-


-

        #  address R/W description

-

       --- ------- --- -----------------------------------------------

-

        1    PC     R  fetch opcode, increment PC

-

        2    PC     R  read next instruction byte (and throw it away)

-

        3  $0100,S  R  increment S

-

        4  $0100,S  R  pull P from stack, increment S

-

        5  $0100,S  R  pull PCL from stack, increment S

-

        6  $0100,S  R  pull PCH from stack

-


-

     RTS

-


-

        #  address R/W description

-

       --- ------- --- -----------------------------------------------

-

        1    PC     R  fetch opcode, increment PC

-

        2    PC     R  read next instruction byte (and throw it away)

-

        3  $0100,S  R  increment S

-

        4  $0100,S  R  pull PCL from stack, increment S

-

        5  $0100,S  R  pull PCH from stack

-

        6    PC     R  increment PC

-


-

     PHA, PHP

-


-

        #  address R/W description

-

       --- ------- --- -----------------------------------------------

-

        1    PC     R  fetch opcode, increment PC

-

        2    PC     R  read next instruction byte (and throw it away)

-

        3  $0100,S  W  push register on stack, decrement S

-


-

     PLA, PLP

-


-

        #  address R/W description

-

       --- ------- --- -----------------------------------------------

-

        1    PC     R  fetch opcode, increment PC

-

        2    PC     R  read next instruction byte (and throw it away)

-

        3  $0100,S  R  increment S

-

        4  $0100,S  R  pull register from stack

-


-

     JSR

-


-

        #  address R/W description

-

       --- ------- --- -------------------------------------------------

-

        1    PC     R  fetch opcode, increment PC

-

        2    PC     R  fetch low address byte, increment PC

-

        3  $0100,S  R  internal operation (predecrement S?)

-

        4  $0100,S  W  push PCH on stack, decrement S

-

        5  $0100,S  W  push PCL on stack, decrement S

-

        6    PC     R  copy low address byte to PCL, fetch high address

-

                       byte to PCH

-


-

  Accumulator or implied addressing

-


-

        #  address R/W description

-

       --- ------- --- -----------------------------------------------

-

        1    PC     R  fetch opcode, increment PC

-

        2    PC     R  read next instruction byte (and throw it away)

-


-

  Immediate addressing

-


-

        #  address R/W description

-

       --- ------- --- ------------------------------------------

-

        1    PC     R  fetch opcode, increment PC

-

        2    PC     R  fetch value, increment PC

-


-

  Absolute addressing

-


-

     JMP

-


-

        #  address R/W description

-

       --- ------- --- -------------------------------------------------

-

        1    PC     R  fetch opcode, increment PC

-

        2    PC     R  fetch low address byte, increment PC

-

        3    PC     R  copy low address byte to PCL, fetch high address

-

                       byte to PCH

-


-

     Read instructions (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT,

-

                        LAX, NOP)

-


-

        #  address R/W description

-

       --- ------- --- ------------------------------------------

-

        1    PC     R  fetch opcode, increment PC

-

        2    PC     R  fetch low byte of address, increment PC

-

        3    PC     R  fetch high byte of address, increment PC

-

        4  address  R  read from effective address

-


-

     Read-Modify-Write instructions (ASL, LSR, ROL, ROR, INC, DEC,

-

                                     SLO, SRE, RLA, RRA, ISB, DCP)

-


-

        #  address R/W description

-

       --- ------- --- ------------------------------------------

-

        1    PC     R  fetch opcode, increment PC

-

        2    PC     R  fetch low byte of address, increment PC

-

        3    PC     R  fetch high byte of address, increment PC

-

        4  address  R  read from effective address

-

        5  address  W  write the value back to effective address,

-

                       and do the operation on it

-

        6  address  W  write the new value to effective address

-


-

     Write instructions (STA, STX, STY, SAX)

-


-

        #  address R/W description

-

       --- ------- --- ------------------------------------------

-

        1    PC     R  fetch opcode, increment PC

-

        2    PC     R  fetch low byte of address, increment PC

-

        3    PC     R  fetch high byte of address, increment PC

-

        4  address  W  write register to effective address

-


-

  Zero page addressing

-


-

     Read instructions (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT,

-

                        LAX, NOP)

-


-

        #  address R/W description

-

       --- ------- --- ------------------------------------------

-

        1    PC     R  fetch opcode, increment PC

-

        2    PC     R  fetch address, increment PC

-

        3  address  R  read from effective address

-


-

     Read-Modify-Write instructions (ASL, LSR, ROL, ROR, INC, DEC,

-

                                     SLO, SRE, RLA, RRA, ISB, DCP)

-


-

        #  address R/W description

-

       --- ------- --- ------------------------------------------

-

        1    PC     R  fetch opcode, increment PC

-

        2    PC     R  fetch address, increment PC

-

        3  address  R  read from effective address

-

        4  address  W  write the value back to effective address,

-

                       and do the operation on it

-

        5  address  W  write the new value to effective address

-


-

     Write instructions (STA, STX, STY, SAX)

-


-

        #  address R/W description

-

       --- ------- --- ------------------------------------------

-

        1    PC     R  fetch opcode, increment PC

-

        2    PC     R  fetch address, increment PC

-

        3  address  W  write register to effective address

-


-

  Zero page indexed addressing

-


-

     Read instructions (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT,

-

                        LAX, NOP)

-


-

        #   address  R/W description

-

       --- --------- --- ------------------------------------------

-

        1     PC      R  fetch opcode, increment PC

-

        2     PC      R  fetch address, increment PC

-

        3   address   R  read from address, add index register to it

-

        4  address+I* R  read from effective address

-


-

       Notes: I denotes either index register (X or Y).

-


-

              * The high byte of the effective address is always zero,

-

                i.e. page boundary crossings are not handled.

-


-

     Read-Modify-Write instructions (ASL, LSR, ROL, ROR, INC, DEC,

-

                                     SLO, SRE, RLA, RRA, ISB, DCP)

-


-

        #   address  R/W description

-

       --- --------- --- ---------------------------------------------

-

        1     PC      R  fetch opcode, increment PC

-

        2     PC      R  fetch address, increment PC

-

        3   address   R  read from address, add index register X to it

-

        4  address+X* R  read from effective address

-

        5  address+X* W  write the value back to effective address,

-

                         and do the operation on it

-

        6  address+X* W  write the new value to effective address

-


-

       Note: * The high byte of the effective address is always zero,

-

               i.e. page boundary crossings are not handled.

-


-

     Write instructions (STA, STX, STY, SAX)

-


-

        #   address  R/W description

-

       --- --------- --- -------------------------------------------

-

        1     PC      R  fetch opcode, increment PC

-

        2     PC      R  fetch address, increment PC

-

        3   address   R  read from address, add index register to it

-

        4  address+I* W  write to effective address

-


-

       Notes: I denotes either index register (X or Y).

-


-

              * The high byte of the effective address is always zero,

-

                i.e. page boundary crossings are not handled.

-


-

  Absolute indexed addressing

-


-

     Read instructions (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT,

-

                        LAX, LAE, SHS, NOP)

-


-

        #   address  R/W description

-

       --- --------- --- ------------------------------------------

-

        1     PC      R  fetch opcode, increment PC

-

        2     PC      R  fetch low byte of address, increment PC

-

        3     PC      R  fetch high byte of address,

-

                         add index register to low address byte,

-

                         increment PC

-

        4  address+I* R  read from effective address,

-

                         fix the high byte of effective address

-

        5+ address+I  R  re-read from effective address

-


-

       Notes: I denotes either index register (X or Y).

-


-

              * The high byte of the effective address may be invalid

-

                at this time, i.e. it may be smaller by $100.

-


-

              + This cycle will be executed only if the effective address

-

                was invalid during cycle #4, i.e. page boundary was crossed.

-


-

     Read-Modify-Write instructions (ASL, LSR, ROL, ROR, INC, DEC,

-

                                     SLO, SRE, RLA, RRA, ISB, DCP)

-


-

        #   address  R/W description

-

       --- --------- --- ------------------------------------------

-

        1    PC       R  fetch opcode, increment PC

-

        2    PC       R  fetch low byte of address, increment PC

-

        3    PC       R  fetch high byte of address,

-

                         add index register X to low address byte,

-

                         increment PC

-

        4  address+X* R  read from effective address,

-

                         fix the high byte of effective address

-

        5  address+X  R  re-read from effective address

-

        6  address+X  W  write the value back to effective address,

-

                         and do the operation on it

-

        7  address+X  W  write the new value to effective address

-


-

       Notes: * The high byte of the effective address may be invalid

-

                at this time, i.e. it may be smaller by $100.

-


-

     Write instructions (STA, STX, STY, SHA, SHX, SHY)

-


-

        #   address  R/W description

-

       --- --------- --- ------------------------------------------

-

        1     PC      R  fetch opcode, increment PC

-

        2     PC      R  fetch low byte of address, increment PC

-

        3     PC      R  fetch high byte of address,

-

                         add index register to low address byte,

-

                         increment PC

-

        4  address+I* R  read from effective address,

-

                         fix the high byte of effective address

-

        5  address+I  W  write to effective address

-


-

       Notes: I denotes either index register (X or Y).

-


-

              * The high byte of the effective address may be invalid

-

                at this time, i.e. it may be smaller by $100. Because

-

                the processor cannot undo a write to an invalid

-

                address, it always reads from the address first.

-


-

  Relative addressing (BCC, BCS, BNE, BEQ, BPL, BMI, BVC, BVS)

-


-

        #   address  R/W description

-

       --- --------- --- ---------------------------------------------

-

        1     PC      R  fetch opcode, increment PC

-

        2     PC      R  fetch operand, increment PC

-

        3     PC      R  Fetch opcode of next instruction,

-

                         If branch is taken, add operand to PCL.

-

                         Otherwise increment PC.

-

        4+    PC*     R  Fetch opcode of next instruction.

-

                         Fix PCH. If it did not change, increment PC.

-

        5!    PC      R  Fetch opcode of next instruction,

-

                         increment PC.

-


-

       Notes: The opcode fetch of the next instruction is included to

-

              this diagram for illustration purposes. When determining

-

              real execution times, remember to subtract the last

-

              cycle.

-


-

              * The high byte of Program Counter (PCH) may be invalid

-

                at this time, i.e. it may be smaller or bigger by $100.

-


-

              + If branch is taken, this cycle will be executed.

-


-

              ! If branch occurs to different page, this cycle will be

-

                executed.

-


-

  Indexed indirect addressing

-


-

     Read instructions (LDA, ORA, EOR, AND, ADC, CMP, SBC, LAX)

-


-

        #    address   R/W description

-

       --- ----------- --- ------------------------------------------

-

        1      PC       R  fetch opcode, increment PC

-

        2      PC       R  fetch pointer address, increment PC

-

        3    pointer    R  read from the address, add X to it

-

        4   pointer+X   R  fetch effective address low

-

        5  pointer+X+1  R  fetch effective address high

-

        6    address    R  read from effective address

-


-

       Note: The effective address is always fetched from zero page,

-

             i.e. the zero page boundary crossing is not handled.

-


-

     Read-Modify-Write instructions (SLO, SRE, RLA, RRA, ISB, DCP)

-


-

        #    address   R/W description

-

       --- ----------- --- ------------------------------------------

-

        1      PC       R  fetch opcode, increment PC

-

        2      PC       R  fetch pointer address, increment PC

-

        3    pointer    R  read from the address, add X to it

-

        4   pointer+X   R  fetch effective address low

-

        5  pointer+X+1  R  fetch effective address high

-

        6    address    R  read from effective address

-

        7    address    W  write the value back to effective address,

-

                           and do the operation on it

-

        8    address    W  write the new value to effective address

-


-

       Note: The effective address is always fetched from zero page,

-

             i.e. the zero page boundary crossing is not handled.

-


-

     Write instructions (STA, SAX)

-


-

        #    address   R/W description

-

       --- ----------- --- ------------------------------------------

-

        1      PC       R  fetch opcode, increment PC

-

        2      PC       R  fetch pointer address, increment PC

-

        3    pointer    R  read from the address, add X to it

-

        4   pointer+X   R  fetch effective address low

-

        5  pointer+X+1  R  fetch effective address high

-

        6    address    W  write to effective address

-


-

       Note: The effective address is always fetched from zero page,

-

             i.e. the zero page boundary crossing is not handled.

-


-

  Indirect indexed addressing

-


-

     Read instructions (LDA, EOR, AND, ORA, ADC, SBC, CMP)

-


-

        #    address   R/W description

-

       --- ----------- --- ------------------------------------------

-

        1      PC       R  fetch opcode, increment PC

-

        2      PC       R  fetch pointer address, increment PC

-

        3    pointer    R  fetch effective address low

-

        4   pointer+1   R  fetch effective address high,

-

                           add Y to low byte of effective address

-

        5   address+Y*  R  read from effective address,

-

                           fix high byte of effective address

-

        6+  address+Y   R  read from effective address

-


-

       Notes: The effective address is always fetched from zero page,

-

              i.e. the zero page boundary crossing is not handled.

-


-

              * The high byte of the effective address may be invalid

-

                at this time, i.e. it may be smaller by $100.

-


-

              + This cycle will be executed only if the effective address

-

                was invalid during cycle #5, i.e. page boundary was crossed.

-


-

     Read-Modify-Write instructions (SLO, SRE, RLA, RRA, ISB, DCP)

-


-

        #    address   R/W description

-

       --- ----------- --- ------------------------------------------

-

        1      PC       R  fetch opcode, increment PC

-

        2      PC       R  fetch pointer address, increment PC

-

        3    pointer    R  fetch effective address low

-

        4   pointer+1   R  fetch effective address high,

-

                           add Y to low byte of effective address

-

        5   address+Y*  R  read from effective address,

-

                           fix high byte of effective address

-

        6   address+Y   R  read from effective address

-

        7   address+Y   W  write the value back to effective address,

-

                           and do the operation on it

-

        8   address+Y   W  write the new value to effective address

-


-

       Notes: The effective address is always fetched from zero page,

-

              i.e. the zero page boundary crossing is not handled.

-


-

              * The high byte of the effective address may be invalid

-

                at this time, i.e. it may be smaller by $100.

-


-

     Write instructions (STA, SHA)

-


-

        #    address   R/W description

-

       --- ----------- --- ------------------------------------------

-

        1      PC       R  fetch opcode, increment PC

-

        2      PC       R  fetch pointer address, increment PC

-

        3    pointer    R  fetch effective address low

-

        4   pointer+1   R  fetch effective address high,

-

                           add Y to low byte of effective address

-

        5   address+Y*  R  read from effective address,

-

                           fix high byte of effective address

-

        6   address+Y   W  write to effective address

-


-

       Notes: The effective address is always fetched from zero page,

-

              i.e. the zero page boundary crossing is not handled.

-


-

              * The high byte of the effective address may be invalid

-

                at this time, i.e. it may be smaller by $100.

-


-

  Absolute indirect addressing (JMP)

-


-

        #   address  R/W description

-

       --- --------- --- ------------------------------------------

-

        1     PC      R  fetch opcode, increment PC

-

        2     PC      R  fetch pointer address low, increment PC

-

        3     PC      R  fetch pointer address high, increment PC

-

        4   pointer   R  fetch low address to latch

-

        5  pointer+1* R  fetch PCH, copy latch to PCL

-


-

       Note: * The PCH will always be fetched from the same page

-

               than PCL, i.e. page boundary crossing is not handled.

-


-

                How Real Programmers Acknowledge Interrupts

-


-

  With RMW instructions:

-


-

        ; beginning of combined raster/timer interrupt routine

-

        LSR $D019       ; clear VIC interrupts, read raster interrupt flag to C

-

        BCS raster      ; jump if VIC caused an interrupt

-

        ...             ; timer interrupt routine

-


-

        Operational diagram of LSR $D019:

-


-

          #  data  address  R/W

-

         --- ----  -------  ---  ---------------------------------

-

          1   4E     PC      R   fetch opcode

-

          2   19    PC+1     R   fetch address low

-

          3   D0    PC+2     R   fetch address high

-

          4   xx    $D019    R   read memory

-

          5   xx    $D019    W   write the value back, rotate right

-

          6  xx/2   $D019    W   write the new value back

-


-

        The 5th cycle acknowledges the interrupt by writing the same

-

        value back. If only raster interrupts are used, the 6th cycle

-

        has no effect on the VIC. (It might acknowledge also some

-

        other interrupts.)

-


-

  With indexed addressing:

-


-

        ; acknowledge interrupts to both CIAs

-

        LDX #$10

-

        LDA $DCFD,X

-


-

        Operational diagram of LDA $DCFD,X:

-


-

          #  data  address  R/W  description

-

         --- ----  -------  ---  ---------------------------------

-

          1   BD     PC      R   fetch opcode

-

          2   FD    PC+1     R   fetch address low

-

          3   DC    PC+2     R   fetch address high, add X to address low

-

          4   xx    $DC0D    R   read from address, fix high byte of address

-

          5   yy    $DD0D    R   read from right address

-


-

        ; acknowledge interrupts to CIA 2

-

        LDX #$10

-

        STA $DDFD,X

-


-

        Operational diagram of STA $DDFD,X:

-


-

          #  data  address  R/W  description

-

         --- ----  -------  ---  ---------------------------------

-

          1   9D     PC      R   fetch opcode

-

          2   FD    PC+1     R   fetch address low

-

          3   DC    PC+2     R   fetch address high, add X to address low

-

          4   xx    $DD0D    R   read from address, fix high byte of address

-

          5   ac    $DE0D    W   write to right address

-


-

  With branch instructions:

-


-

        ; acknowledge interrupts to CIA 2

-

                LDA #$00  ; clear N flag

-

                JMP $DD0A

-

        DD0A    BPL $DC9D ; branch

-

        DC9D    BRK       ; return

-


-

        You need the following preparations to initialize the CIA registers:

-


-

                LDA #$91  ; argument of BPL

-

                STA $DD0B

-

                LDA #$10  ; BPL

-

                STA $DD0A

-

                STA $DD08 ; load the ToD values from the latches

-

                LDA $DD0B ; freeze the ToD display

-

                LDA #$7F

-

                STA $DC0D ; assure that $DC0D is $00

-


-

        Operational diagram of BPL $DC9D:

-


-

          #  data  address  R/W  description

-

         --- ----  -------  ---  ---------------------------------

-

          1   10    $DD0A    R   fetch opcode

-

          2   91    $DD0B    R   fetch argument

-

          3   xx    $DD0C    R   fetch opcode, add argument to PCL

-

          4   yy    $DD9D    R   fetch opcode, fix PCH

-

        ( 5   00    $DC9D    R   fetch opcode )

-


-

        ; acknowledge interrupts to CIA 1

-

                LSR       ; clear N flag

-

                JMP $DCFA

-

        DCFA    BPL $DD0D

-

        DD0D    BRK

-


-

        ; Again you need to set the ToD registers of CIA 1 and the

-

        ; Interrupt Control Register of CIA 2 first.

-


-

        Operational diagram of BPL $DD0D:

-


-

          #  data  address  R/W  description

-

         --- ----  -------  ---  ---------------------------------

-

          1   10    $DCFA    R   fetch opcode

-

          2   11    $DCFB    R   fetch argument

-

          3   xx    $DCFC    R   fetch opcode, add argument to PCL

-

          4   yy    $DC0D    R   fetch opcode, fix PCH

-

        ( 5   00    $DD0D    R   fetch opcode )

-


-

        ; acknowledge interrupts to CIA 2 automagically

-

                ; preparations

-

                LDA #$7F

-

                STA $DD0D       ; disable all interrupt sources of CIA2

-

                LDA $DD0E

-

                AND #$BE        ; ensure that $DD0C remains constant

-

                STA $DD0E       ; and stop the timer

-

                LDA #$FD

-

                STA $DD0C       ; parameter of BPL

-

                LDA #$10

-

                STA $DD0B       ; BPL

-

                LDA #$40

-

                STA $DD0A       ; RTI/parameter of LSR

-

                LDA #$46

-

                STA $DD09       ; LSR

-

                STA $DD08       ; load the ToD values from the latches

-

                LDA $DD0B       ; freeze the ToD display

-

                LDA #$09

-

                STA $0318

-

                LDA #$DD

-

                STA $0319       ; change NMI vector to $DD09

-

                LDA #$FF        ; Try changing this instruction's operand

-

                STA $DD05       ; (see comment below).

-

                LDA #$FF

-

                STA $DD04       ; set interrupt frequency to 1/65536 cycles

-

                LDA $DD0E

-

                AND #$80

-

                ORA #$11

-

                LDX #$81

-

                STX $DD0D       ; enable timer interrupt

-

                STA $DD0E       ; start timer

-


-

                LDA #$00        ; To see that the interrupts really occur,

-

                STA $D011       ; use something like this and see how

-

        LOOP    DEC $D020       ; changing the byte loaded to $DD05 from

-

                BNE LOOP        ; #$FF to #$0F changes the image.

-


-

        When an NMI occurs, the processor jumps to Kernal code, which jumps to

-

        ($0318), which points to the following routine:

-


-

        DD09    LSR $40         ; clear N flag

-

                BPL $DD0A       ; Note: $DD0A contains RTI.

-


-

        Operational diagram of BPL $DD0A:

-


-

          #  data  address  R/W  description

-

         --- ----  -------  ---  ---------------------------------

-

          1   10    $DD0B    R   fetch opcode

-

          2   11    $DD0C    R   fetch argument

-

          3   xx    $DD0D    R   fetch opcode, add argument to PCL

-

          4   40    $DD0A    R   fetch opcode, (fix PCH)

-


-

  With RTI:

-


-

        ; the fastest possible interrupt handler in the 6500 family

-

                ; preparations

-

                SEI

-

                LDA $01         ; disable ROM and enable I/O

-

                AND #$FD

-

                ORA #$05

-

                STA $01

-

                LDA #$7F

-

                STA $DD0D       ; disable CIA 2's all interrupt sources

-

                LDA $DD0E

-

                AND #$BE        ; ensure that $DD0C remains constant

-

                STA $DD0E       ; and stop the timer

-

                LDA #$40

-

                STA $DD0C       ; store RTI to $DD0C

-

                LDA #$0C

-

                STA $FFFA

-

                LDA #$DD

-

                STA $FFFB       ; change NMI vector to $DD0C

-

                LDA #$FF        ; Try changing this instruction's operand

-

                STA $DD05       ; (see comment below).

-

                LDA #$FF

-

                STA $DD04       ; set interrupt frequency to 1/65536 cycles

-

                LDA $DD0E

-

                AND #$80

-

                ORA #$11

-

                LDX #$81

-

                STX $DD0D       ; enable timer interrupt

-

                STA $DD0E       ; start timer

-


-

                LDA #$00        ; To see that the interrupts really occur,

-

                STA $D011       ; use something like this and see how

-

        LOOP    DEC $D020       ; changing the byte loaded to $DD05 from

-

                BNE LOOP        ; #$FF to #$0F changes the image.

-


+

     BRK

+


+

        #  address R/W description

+

       --- ------- --- -----------------------------------------------

+

        1    PC     R  fetch opcode, increment PC

+

        2    PC     R  read next instruction byte (and throw it away),

+

                       increment PC

+

        3  $0100,S  W  push PCH on stack (with B flag set), decrement S

+

        4  $0100,S  W  push PCL on stack, decrement S

+

        5  $0100,S  W  push P on stack, decrement S

+

        6   $FFFE   R  fetch PCL

+

        7   $FFFF   R  fetch PCH

+


+

     RTI

+


+

        #  address R/W description

+

       --- ------- --- -----------------------------------------------

+

        1    PC     R  fetch opcode, increment PC

+

        2    PC     R  read next instruction byte (and throw it away)

+

        3  $0100,S  R  increment S

+

        4  $0100,S  R  pull P from stack, increment S

+

        5  $0100,S  R  pull PCL from stack, increment S

+

        6  $0100,S  R  pull PCH from stack

+


+

     RTS

+


+

        #  address R/W description

+

       --- ------- --- -----------------------------------------------

+

        1    PC     R  fetch opcode, increment PC

+

        2    PC     R  read next instruction byte (and throw it away)

+

        3  $0100,S  R  increment S

+

        4  $0100,S  R  pull PCL from stack, increment S

+

        5  $0100,S  R  pull PCH from stack

+

        6    PC     R  increment PC

+


+

     PHA, PHP

+


+

        #  address R/W description

+

       --- ------- --- -----------------------------------------------

+

        1    PC     R  fetch opcode, increment PC

+

        2    PC     R  read next instruction byte (and throw it away)

+

        3  $0100,S  W  push register on stack, decrement S

+


+

     PLA, PLP

+


+

        #  address R/W description

+

       --- ------- --- -----------------------------------------------

+

        1    PC     R  fetch opcode, increment PC

+

        2    PC     R  read next instruction byte (and throw it away)

+

        3  $0100,S  R  increment S

+

        4  $0100,S  R  pull register from stack

+


+

     JSR

+


+

        #  address R/W description

+

       --- ------- --- -------------------------------------------------

+

        1    PC     R  fetch opcode, increment PC

+

        2    PC     R  fetch low address byte, increment PC

+

        3  $0100,S  R  internal operation (predecrement S?)

+

        4  $0100,S  W  push PCH on stack, decrement S

+

        5  $0100,S  W  push PCL on stack, decrement S

+

        6    PC     R  copy low address byte to PCL, fetch high address

+

                       byte to PCH

+


+

  Accumulator or implied addressing

+


+

        #  address R/W description

+

       --- ------- --- -----------------------------------------------

+

        1    PC     R  fetch opcode, increment PC

+

        2    PC     R  read next instruction byte (and throw it away)

+


+

  Immediate addressing

+


+

        #  address R/W description

+

       --- ------- --- ------------------------------------------

+

        1    PC     R  fetch opcode, increment PC

+

        2    PC     R  fetch value, increment PC

+


+

  Absolute addressing

+


+

     JMP

+


+

        #  address R/W description

+

       --- ------- --- -------------------------------------------------

+

        1    PC     R  fetch opcode, increment PC

+

        2    PC     R  fetch low address byte, increment PC

+

        3    PC     R  copy low address byte to PCL, fetch high address

+

                       byte to PCH

+


+

     Read instructions (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT,

+

                        LAX, NOP)

+


+

        #  address R/W description

+

       --- ------- --- ------------------------------------------

+

        1    PC     R  fetch opcode, increment PC

+

        2    PC     R  fetch low byte of address, increment PC

+

        3    PC     R  fetch high byte of address, increment PC

+

        4  address  R  read from effective address

+


+

     Read-Modify-Write instructions (ASL, LSR, ROL, ROR, INC, DEC,

+

                                     SLO, SRE, RLA, RRA, ISB, DCP)

+


+

        #  address R/W description

+

       --- ------- --- ------------------------------------------

+

        1    PC     R  fetch opcode, increment PC

+

        2    PC     R  fetch low byte of address, increment PC

+

        3    PC     R  fetch high byte of address, increment PC

+

        4  address  R  read from effective address

+

        5  address  W  write the value back to effective address,

+

                       and do the operation on it

+

        6  address  W  write the new value to effective address

+


+

     Write instructions (STA, STX, STY, SAX)

+


+

        #  address R/W description

+

       --- ------- --- ------------------------------------------

+

        1    PC     R  fetch opcode, increment PC

+

        2    PC     R  fetch low byte of address, increment PC

+

        3    PC     R  fetch high byte of address, increment PC

+

        4  address  W  write register to effective address

+


+

  Zero page addressing

+


+

     Read instructions (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT,

+

                        LAX, NOP)

+


+

        #  address R/W description

+

       --- ------- --- ------------------------------------------

+

        1    PC     R  fetch opcode, increment PC

+

        2    PC     R  fetch address, increment PC

+

        3  address  R  read from effective address

+


+

     Read-Modify-Write instructions (ASL, LSR, ROL, ROR, INC, DEC,

+

                                     SLO, SRE, RLA, RRA, ISB, DCP)

+


+

        #  address R/W description

+

       --- ------- --- ------------------------------------------

+

        1    PC     R  fetch opcode, increment PC

+

        2    PC     R  fetch address, increment PC

+

        3  address  R  read from effective address

+

        4  address  W  write the value back to effective address,

+

                       and do the operation on it

+

        5  address  W  write the new value to effective address

+


+

     Write instructions (STA, STX, STY, SAX)

+


+

        #  address R/W description

+

       --- ------- --- ------------------------------------------

+

        1    PC     R  fetch opcode, increment PC

+

        2    PC     R  fetch address, increment PC

+

        3  address  W  write register to effective address

+


+

  Zero page indexed addressing

+


+

     Read instructions (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT,

+

                        LAX, NOP)

+


+

        #   address  R/W description

+

       --- --------- --- ------------------------------------------

+

        1     PC      R  fetch opcode, increment PC

+

        2     PC      R  fetch address, increment PC

+

        3   address   R  read from address, add index register to it

+

        4  address+I* R  read from effective address

+


+

       Notes: I denotes either index register (X or Y).

+


+

              * The high byte of the effective address is always zero,

+

                i.e. page boundary crossings are not handled.

+


+

     Read-Modify-Write instructions (ASL, LSR, ROL, ROR, INC, DEC,

+

                                     SLO, SRE, RLA, RRA, ISB, DCP)

+


+

        #   address  R/W description

+

       --- --------- --- ---------------------------------------------

+

        1     PC      R  fetch opcode, increment PC

+

        2     PC      R  fetch address, increment PC

+

        3   address   R  read from address, add index register X to it

+

        4  address+X* R  read from effective address

+

        5  address+X* W  write the value back to effective address,

+

                         and do the operation on it

+

        6  address+X* W  write the new value to effective address

+


+

       Note: * The high byte of the effective address is always zero,

+

               i.e. page boundary crossings are not handled.

+


+

     Write instructions (STA, STX, STY, SAX)

+


+

        #   address  R/W description

+

       --- --------- --- -------------------------------------------

+

        1     PC      R  fetch opcode, increment PC

+

        2     PC      R  fetch address, increment PC

+

        3   address   R  read from address, add index register to it

+

        4  address+I* W  write to effective address

+


+

       Notes: I denotes either index register (X or Y).

+


+

              * The high byte of the effective address is always zero,

+

                i.e. page boundary crossings are not handled.

+


+

  Absolute indexed addressing

+


+

     Read instructions (LDA, LDX, LDY, EOR, AND, ORA, ADC, SBC, CMP, BIT,

+

                        LAX, LAE, SHS, NOP)

+


+

        #   address  R/W description

+

       --- --------- --- ------------------------------------------

+

        1     PC      R  fetch opcode, increment PC

+

        2     PC      R  fetch low byte of address, increment PC

+

        3     PC      R  fetch high byte of address,

+

                         add index register to low address byte,

+

                         increment PC

+

        4  address+I* R  read from effective address,

+

                         fix the high byte of effective address

+

        5+ address+I  R  re-read from effective address

+


+

       Notes: I denotes either index register (X or Y).

+


+

              * The high byte of the effective address may be invalid

+

                at this time, i.e. it may be smaller by $100.

+


+

              + This cycle will be executed only if the effective address

+

                was invalid during cycle #4, i.e. page boundary was crossed.

+


+

     Read-Modify-Write instructions (ASL, LSR, ROL, ROR, INC, DEC,

+

                                     SLO, SRE, RLA, RRA, ISB, DCP)

+


+

        #   address  R/W description

+

       --- --------- --- ------------------------------------------

+

        1    PC       R  fetch opcode, increment PC

+

        2    PC       R  fetch low byte of address, increment PC

+

        3    PC       R  fetch high byte of address,

+

                         add index register X to low address byte,

+

                         increment PC

+

        4  address+X* R  read from effective address,

+

                         fix the high byte of effective address

+

        5  address+X  R  re-read from effective address

+

        6  address+X  W  write the value back to effective address,

+

                         and do the operation on it

+

        7  address+X  W  write the new value to effective address

+


+

       Notes: * The high byte of the effective address may be invalid

+

                at this time, i.e. it may be smaller by $100.

+


+

     Write instructions (STA, STX, STY, SHA, SHX, SHY)

+


+

        #   address  R/W description

+

       --- --------- --- ------------------------------------------

+

        1     PC      R  fetch opcode, increment PC

+

        2     PC      R  fetch low byte of address, increment PC

+

        3     PC      R  fetch high byte of address,

+

                         add index register to low address byte,

+

                         increment PC

+

        4  address+I* R  read from effective address,

+

                         fix the high byte of effective address

+

        5  address+I  W  write to effective address

+


+

       Notes: I denotes either index register (X or Y).

+


+

              * The high byte of the effective address may be invalid

+

                at this time, i.e. it may be smaller by $100. Because

+

                the processor cannot undo a write to an invalid

+

                address, it always reads from the address first.

+


+

  Relative addressing (BCC, BCS, BNE, BEQ, BPL, BMI, BVC, BVS)

+


+

        #   address  R/W description

+

       --- --------- --- ---------------------------------------------

+

        1     PC      R  fetch opcode, increment PC

+

        2     PC      R  fetch operand, increment PC

+

        3     PC      R  Fetch opcode of next instruction,

+

                         If branch is taken, add operand to PCL.

+

                         Otherwise increment PC.

+

        4+    PC*     R  Fetch opcode of next instruction.

+

                         Fix PCH. If it did not change, increment PC.

+

        5!    PC      R  Fetch opcode of next instruction,

+

                         increment PC.

+


+

       Notes: The opcode fetch of the next instruction is included to

+

              this diagram for illustration purposes. When determining

+

              real execution times, remember to subtract the last

+

              cycle.

+


+

              * The high byte of Program Counter (PCH) may be invalid

+

                at this time, i.e. it may be smaller or bigger by $100.

+


+

              + If branch is taken, this cycle will be executed.

+


+

              ! If branch occurs to different page, this cycle will be

+

                executed.

+


+

  Indexed indirect addressing

+


+

     Read instructions (LDA, ORA, EOR, AND, ADC, CMP, SBC, LAX)

+


+

        #    address   R/W description

+

       --- ----------- --- ------------------------------------------

+

        1      PC       R  fetch opcode, increment PC

+

        2      PC       R  fetch pointer address, increment PC

+

        3    pointer    R  read from the address, add X to it

+

        4   pointer+X   R  fetch effective address low

+

        5  pointer+X+1  R  fetch effective address high

+

        6    address    R  read from effective address

+


+

       Note: The effective address is always fetched from zero page,

+

             i.e. the zero page boundary crossing is not handled.

+


+

     Read-Modify-Write instructions (SLO, SRE, RLA, RRA, ISB, DCP)

+


+

        #    address   R/W description

+

       --- ----------- --- ------------------------------------------

+

        1      PC       R  fetch opcode, increment PC

+

        2      PC       R  fetch pointer address, increment PC

+

        3    pointer    R  read from the address, add X to it

+

        4   pointer+X   R  fetch effective address low

+

        5  pointer+X+1  R  fetch effective address high

+

        6    address    R  read from effective address

+

        7    address    W  write the value back to effective address,

+

                           and do the operation on it

+

        8    address    W  write the new value to effective address

+


+

       Note: The effective address is always fetched from zero page,

+

             i.e. the zero page boundary crossing is not handled.

+


+

     Write instructions (STA, SAX)

+


+

        #    address   R/W description

+

       --- ----------- --- ------------------------------------------

+

        1      PC       R  fetch opcode, increment PC

+

        2      PC       R  fetch pointer address, increment PC

+

        3    pointer    R  read from the address, add X to it

+

        4   pointer+X   R  fetch effective address low

+

        5  pointer+X+1  R  fetch effective address high

+

        6    address    W  write to effective address

+


+

       Note: The effective address is always fetched from zero page,

+

             i.e. the zero page boundary crossing is not handled.

+


+

  Indirect indexed addressing

+


+

     Read instructions (LDA, EOR, AND, ORA, ADC, SBC, CMP)

+


+

        #    address   R/W description

+

       --- ----------- --- ------------------------------------------

+

        1      PC       R  fetch opcode, increment PC

+

        2      PC       R  fetch pointer address, increment PC

+

        3    pointer    R  fetch effective address low

+

        4   pointer+1   R  fetch effective address high,

+

                           add Y to low byte of effective address

+

        5   address+Y*  R  read from effective address,

+

                           fix high byte of effective address

+

        6+  address+Y   R  read from effective address

+


+

       Notes: The effective address is always fetched from zero page,

+

              i.e. the zero page boundary crossing is not handled.

+


+

              * The high byte of the effective address may be invalid

+

                at this time, i.e. it may be smaller by $100.

+


+

              + This cycle will be executed only if the effective address

+

                was invalid during cycle #5, i.e. page boundary was crossed.

+


+

     Read-Modify-Write instructions (SLO, SRE, RLA, RRA, ISB, DCP)

+


+

        #    address   R/W description

+

       --- ----------- --- ------------------------------------------

+

        1      PC       R  fetch opcode, increment PC

+

        2      PC       R  fetch pointer address, increment PC

+

        3    pointer    R  fetch effective address low

+

        4   pointer+1   R  fetch effective address high,

+

                           add Y to low byte of effective address

+

        5   address+Y*  R  read from effective address,

+

                           fix high byte of effective address

+

        6   address+Y   R  read from effective address

+

        7   address+Y   W  write the value back to effective address,

+

                           and do the operation on it

+

        8   address+Y   W  write the new value to effective address

+


+

       Notes: The effective address is always fetched from zero page,

+

              i.e. the zero page boundary crossing is not handled.

+


+

              * The high byte of the effective address may be invalid

+

                at this time, i.e. it may be smaller by $100.

+


+

     Write instructions (STA, SHA)

+


+

        #    address   R/W description

+

       --- ----------- --- ------------------------------------------

+

        1      PC       R  fetch opcode, increment PC

+

        2      PC       R  fetch pointer address, increment PC

+

        3    pointer    R  fetch effective address low

+

        4   pointer+1   R  fetch effective address high,

+

                           add Y to low byte of effective address

+

        5   address+Y*  R  read from effective address,

+

                           fix high byte of effective address

+

        6   address+Y   W  write to effective address

+


+

       Notes: The effective address is always fetched from zero page,

+

              i.e. the zero page boundary crossing is not handled.

+


+

              * The high byte of the effective address may be invalid

+

                at this time, i.e. it may be smaller by $100.

+


+

  Absolute indirect addressing (JMP)

+


+

        #   address  R/W description

+

       --- --------- --- ------------------------------------------

+

        1     PC      R  fetch opcode, increment PC

+

        2     PC      R  fetch pointer address low, increment PC

+

        3     PC      R  fetch pointer address high, increment PC

+

        4   pointer   R  fetch low address to latch

+

        5  pointer+1* R  fetch PCH, copy latch to PCL

+


+

       Note: * The PCH will always be fetched from the same page

+

               than PCL, i.e. page boundary crossing is not handled.

+


+

                How Real Programmers Acknowledge Interrupts

+


+

  With RMW instructions:

+


+

        ; beginning of combined raster/timer interrupt routine

+

        LSR $D019       ; clear VIC interrupts, read raster interrupt flag to C

+

        BCS raster      ; jump if VIC caused an interrupt

+

        ...             ; timer interrupt routine

+


+

        Operational diagram of LSR $D019:

+


+

          #  data  address  R/W

+

         --- ----  -------  ---  ---------------------------------

+

          1   4E     PC      R   fetch opcode

+

          2   19    PC+1     R   fetch address low

+

          3   D0    PC+2     R   fetch address high

+

          4   xx    $D019    R   read memory

+

          5   xx    $D019    W   write the value back, rotate right

+

          6  xx/2   $D019    W   write the new value back

+


+

        The 5th cycle acknowledges the interrupt by writing the same

+

        value back. If only raster interrupts are used, the 6th cycle

+

        has no effect on the VIC. (It might acknowledge also some

+

        other interrupts.)

+


+

  With indexed addressing:

+


+

        ; acknowledge interrupts to both CIAs

+

        LDX #$10

+

        LDA $DCFD,X

+


+

        Operational diagram of LDA $DCFD,X:

+


+

          #  data  address  R/W  description

+

         --- ----  -------  ---  ---------------------------------

+

          1   BD     PC      R   fetch opcode

+

          2   FD    PC+1     R   fetch address low

+

          3   DC    PC+2     R   fetch address high, add X to address low

+

          4   xx    $DC0D    R   read from address, fix high byte of address

+

          5   yy    $DD0D    R   read from right address

+


+

        ; acknowledge interrupts to CIA 2

+

        LDX #$10

+

        STA $DDFD,X

+


+

        Operational diagram of STA $DDFD,X:

+


+

          #  data  address  R/W  description

+

         --- ----  -------  ---  ---------------------------------

+

          1   9D     PC      R   fetch opcode

+

          2   FD    PC+1     R   fetch address low

+

          3   DC    PC+2     R   fetch address high, add X to address low

+

          4   xx    $DD0D    R   read from address, fix high byte of address

+

          5   ac    $DE0D    W   write to right address

+


+

  With branch instructions:

+


+

        ; acknowledge interrupts to CIA 2

+

                LDA #$00  ; clear N flag

+

                JMP $DD0A

+

        DD0A    BPL $DC9D ; branch

+

        DC9D    BRK       ; return

+


+

        You need the following preparations to initialize the CIA registers:

+


+

                LDA #$91  ; argument of BPL

+

                STA $DD0B

+

                LDA #$10  ; BPL

+

                STA $DD0A

+

                STA $DD08 ; load the ToD values from the latches

+

                LDA $DD0B ; freeze the ToD display

+

                LDA #$7F

+

                STA $DC0D ; assure that $DC0D is $00

+


+

        Operational diagram of BPL $DC9D:

+


+

          #  data  address  R/W  description

+

         --- ----  -------  ---  ---------------------------------

+

          1   10    $DD0A    R   fetch opcode

+

          2   91    $DD0B    R   fetch argument

+

          3   xx    $DD0C    R   fetch opcode, add argument to PCL

+

          4   yy    $DD9D    R   fetch opcode, fix PCH

+

        ( 5   00    $DC9D    R   fetch opcode )

+


+

        ; acknowledge interrupts to CIA 1

+

                LSR       ; clear N flag

+

                JMP $DCFA

+

        DCFA    BPL $DD0D

+

        DD0D    BRK

+


+

        ; Again you need to set the ToD registers of CIA 1 and the

+

        ; Interrupt Control Register of CIA 2 first.

+


+

        Operational diagram of BPL $DD0D:

+


+

          #  data  address  R/W  description

+

         --- ----  -------  ---  ---------------------------------

+

          1   10    $DCFA    R   fetch opcode

+

          2   11    $DCFB    R   fetch argument

+

          3   xx    $DCFC    R   fetch opcode, add argument to PCL

+

          4   yy    $DC0D    R   fetch opcode, fix PCH

+

        ( 5   00    $DD0D    R   fetch opcode )

+


+

        ; acknowledge interrupts to CIA 2 automagically

+

                ; preparations

+

                LDA #$7F

+

                STA $DD0D       ; disable all interrupt sources of CIA2

+

                LDA $DD0E

+

                AND #$BE        ; ensure that $DD0C remains constant

+

                STA $DD0E       ; and stop the timer

+

                LDA #$FD

+

                STA $DD0C       ; parameter of BPL

+

                LDA #$10

+

                STA $DD0B       ; BPL

+

                LDA #$40

+

                STA $DD0A       ; RTI/parameter of LSR

+

                LDA #$46

+

                STA $DD09       ; LSR

+

                STA $DD08       ; load the ToD values from the latches

+

                LDA $DD0B       ; freeze the ToD display

+

                LDA #$09

+

                STA $0318

+

                LDA #$DD

+

                STA $0319       ; change NMI vector to $DD09

+

                LDA #$FF        ; Try changing this instruction's operand

+

                STA $DD05       ; (see comment below).

+

                LDA #$FF

+

                STA $DD04       ; set interrupt frequency to 1/65536 cycles

+

                LDA $DD0E

+

                AND #$80

+

                ORA #$11

+

                LDX #$81

+

                STX $DD0D       ; enable timer interrupt

+

                STA $DD0E       ; start timer

+


+

                LDA #$00        ; To see that the interrupts really occur,

+

                STA $D011       ; use something like this and see how

+

        LOOP    DEC $D020       ; changing the byte loaded to $DD05 from

+

                BNE LOOP        ; #$FF to #$0F changes the image.

+


+

        When an NMI occurs, the processor jumps to Kernal code, which jumps to

+

        ($0318), which points to the following routine:

+


+

        DD09    LSR $40         ; clear N flag

+

                BPL $DD0A       ; Note: $DD0A contains RTI.

+


+

        Operational diagram of BPL $DD0A:

+


+

          #  data  address  R/W  description

+

         --- ----  -------  ---  ---------------------------------

+

          1   10    $DD0B    R   fetch opcode

+

          2   11    $DD0C    R   fetch argument

+

          3   xx    $DD0D    R   fetch opcode, add argument to PCL

+

          4   40    $DD0A    R   fetch opcode, (fix PCH)

+


+

  With RTI:

+


+

        ; the fastest possible interrupt handler in the 6500 family

+

                ; preparations

+

                SEI

+

                LDA $01         ; disable ROM and enable I/O

+

                AND #$FD

+

                ORA #$05

+

                STA $01

+

                LDA #$7F

+

                STA $DD0D       ; disable CIA 2's all interrupt sources

+

                LDA $DD0E

+

                AND #$BE        ; ensure that $DD0C remains constant

+

                STA $DD0E       ; and stop the timer

+

                LDA #$40

+

                STA $DD0C       ; store RTI to $DD0C

+

                LDA #$0C

+

                STA $FFFA

+

                LDA #$DD

+

                STA $FFFB       ; change NMI vector to $DD0C

+

                LDA #$FF        ; Try changing this instruction's operand

+

                STA $DD05       ; (see comment below).

+

                LDA #$FF

+

                STA $DD04       ; set interrupt frequency to 1/65536 cycles

+

                LDA $DD0E

+

                AND #$80

+

                ORA #$11

+

                LDX #$81

+

                STX $DD0D       ; enable timer interrupt

+

                STA $DD0E       ; start timer

+


+

                LDA #$00        ; To see that the interrupts really occur,

+

                STA $D011       ; use something like this and see how

+

        LOOP    DEC $D020       ; changing the byte loaded to $DD05 from

+

                BNE LOOP        ; #$FF to #$0F changes the image.

+


        When an NMI occurs, the processor jumps to Kernal code, which

        jumps to ($0318), which points to the following routine:


-

        DD0C    RTI

-


+

        DD0C    RTI

+


        How on earth can this clear the interrupts? Remember, the

        processor always fetches two successive bytes for each

        instruction.

@@ -1649,13 +1653,13 @@ p,ul,ol /* Paragraph Style */

        you used when writing the RTI.


        Or you can combine the latter two methods:

-


-

        DD09    LSR $xx  ; xx is any appropriate BCD value 00-59.

-

                BPL $DCFC

-

        DCFC    RTI

-


+


+

        DD09    LSR $xx  ; xx is any appropriate BCD value 00-59.

+

                BPL $DCFC

+

        DCFC    RTI

+


        This example acknowledges interrupts to both CIAs.

-


+


  If you want to confuse the examiners of your code, you can use any

of these techniques. Although these examples use no undefined opcodes,

they do not necessarily run correctly on CMOS processors. However, the

@@ -1670,7 +1674,7 @@ p,ul,ol /* Paragraph Style */




-

2008

-

This help file has been generated by the freeware version of HelpNDoc

+

2008

+

This help file has been generated by the freeware version of HelpNDoc

diff --git a/home.html b/home.html index 48bd2122..a7b1a1a6 100644 --- a/home.html +++ b/home.html @@ -59,22 +59,26 @@

 

Latest Release

-

FCEUX 2.1.3
- 08 April 2010

-

The 2.1.3 release that fixes some bugs of 2.1.2, increases game compatibility, and adds usability enhancements to the windows port and adds a GUI to the SDL port

-

Full changelog

+

FCEUX 2.1.4
+ 31 May 2010

+

The 2.1.4 release that fixes some many bugs and adds new features compared to 2.1.3. In addition it also fixes up the movie code significantly; ixing implementation problems, loading speed, adding new features, and fixing bugs.

+

Full changelog

Noteable changes

diff --git a/pressrelease-2.1.4.html b/pressrelease-2.1.4.html index efd51b85..1ea2a4bb 100644 --- a/pressrelease-2.1.4.html +++ b/pressrelease-2.1.4.html @@ -36,7 +36,7 @@

FCEUX 2.1.4 Release

-xx June 2010 +31 May 2010

The 2.1.4 release that fixes some many bugs and adds new features compared to 2.1.3. In addition it also fixes up the movie code significantly; fixing implementation problems, loading speed, adding new features, and fixing @@ -52,16 +52,16 @@ Disable auto-savestates during turbo
Fixed so Gotcha! auto-enables zapper

Movies

Fully implemented "bulletproof" read-only
-Movie code now fully conforms to the Savestate section of the Laws of TAS
+Movie code now fully conforms to the Savestate section of the Laws of TAS
Fixed a potential desync that plays out an extra frame without an update to the frame count involving heavy lua use, joypad.get, and a loadstate
-Movie support for microphone
+Movie support for microphone
Movies now have a "finished" mode. If a playback stops the movie isn't cleared from memory, and can be replayed or a state loaded. Similar functionality as DeSmuME and GENS rerecording
-New PPU flag in movie headers (doesn't change an emulators PPU state when loading a movie)
+New PPU flag in movie headers (doesn't change an emulators PPU state when loading a movie)
Much faster movie loading and movie-savestate loading
-Made gamepad 2 off by default (so less movies should have unused player 2 data)
+Made gamepad 2 off by default (so less movies should have unused player 2 data)
Implemented a "full savestate-movie load" mode similar to the implementation in VBA-rr and SNES9x-rr. In this mode loading a savestate in read+write doesn't truncate the movie to its frame count immediately. Instead it waits until input is recording into the movie (next frame). For win32 this feature is togglable in movie options and the context menu. For SDL this is off by default and a toggle will need to be added
Movie + loadstate errors are handled more gracefully now, with more informative error messages and the movie doesn't have to stop if backups are enabled
-Fix PlayMovieFromBeginning when using a movie that starts from savestate
+Fix PlayMovieFromBeginning when using a movie that starts from savestate

Lua

fix bug that caused zapper.read() to crash when movie playback ends
Win32 - Added option for palette selection as color for LUA colors. Included is a LUA script to display all choices with the value used to pick displayed color
@@ -96,7 +96,7 @@ Replay dialog - fix bug that was causing it to always report savestate movies as

Debugger

Added conditional debugging option 'K', for bank PC is on
Fixed bug involving pausing emulation outside of the debugger, then trying to use the debugger commands, and having the CPU registers become corrupted
-Made debugger able to break on and distinguish Stack reads/writes
+Made debugger able to break on and distinguish Stack reads/writes

Hex Editor

Added "Goto" command
Made the Hex Editor display the Frozen, Bookmarked, etc. status of the selected address, and made the Frozen color override the Bookmarked color
@@ -107,9 +107,10 @@ Added context menu to Cheat Dialog Cheat Listbox, populated list with Toggle Che Enabled multi-select for Cheat menu to allow multiple toggles and deletes
Made cheat menu's Pause When Active effect immediate

GUI

-Added Tools - GUI option to partially disable visual themes, so the emulator can be made to look like it did in 2.1.1 and earlier releases
+Added Tools -> GUI option to partially disable visual themes, so the emulator can be made to look like it did in 2.1.1 and earlier releases
Drag & Drop - if dropping a .fcm with no ROM loaded, prompt for one (same functionality that was added to .fm2 files)
-Added single-instance mode, which makes starting a second copy of FCEUX load the file into the first, then exit.Mode off by default, togglable under Config - GUI
+Added single-instance mode, which makes starting a second copy of FCEUX load the file into the first, then exit. Mode off by default, toggleable under Config + -> GUI