MMC5 - refixed
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CaH4e3
parent
009ece83d4
commit
52945e7484
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@ -145,51 +145,46 @@ uint8 FASTCALL mmc5_PPURead(uint32 A) {
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}
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}
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// ELROM seems to have 8KB of RAM
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// ETROM seems to have 16KB of WRAM
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// EWROM seems to have 32KB of WRAM
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cartdata MMC5CartList[] =
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{
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{ 0x9c18762b, 2 }, /* L'Empereur */
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{ 0x26533405, 2 },
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{ 0x6396b988, 2 },
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{ 0xaca15643, 2 }, /* Uncharted Waters */
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{ 0xfe3488d1, 2 }, /* Dai Koukai Jidai */
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{ 0x15fe6d0f, 2 }, /* BKAC */
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{ 0x39f2ce4b, 2 }, /* Suikoden */
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{ 0x8ce478db, 2 }, /* Nobunaga's Ambition 2 */
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{ 0xeee9a682, 2 },
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{ 0xf9b4240f, 2 },
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{ 0x6f4e4312, 4 }, /* Aoki Ookami to Shiroki Mejika - Genchou Hishi */
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{ 0x15fe6d0f, 2 }, /* Bandit Kings of Ancient China */
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{ 0x671f23a8, 0 }, /* Castlevania III - Dracula's Curse (E) */
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{ 0xcd4e7430, 0 }, /* Castlevania III - Dracula's Curse (KC) */
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{ 0xed2465be, 0 }, /* Castlevania III - Dracula's Curse (U) */
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{ 0xfe3488d1, 2 }, /* Daikoukai Jidai */
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{ 0x0ec6c023, 1 }, /* Gemfire */
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{ 0x0afb395e, 0 }, /* Gun Sight */
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{ 0x1ced086f, 2 }, /* Ishin no Arashi */
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{ 0xf540677b, 4 }, /* Nobunaga...Bushou Fuuun Roku */
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{ 0x6f4e4312, 4 }, /* Aoki Ookami..Genchou */
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{ 0xf011e490, 4 }, /* Romance of the 3 Kingdoms 2 */
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{ 0x184c2124, 4 }, /* Sangokushi 2 */
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{ 0xee8e6553, 4 },
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{ 0x9cbadc25, 1 }, /* Just Breed */
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{ 0x6396b988, 2 }, /* L'Empereur (J) */
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{ 0x9c18762b, 2 }, /* L'Empereur (U) */
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{ 0xb0480ae9, 0 }, /* Laser Invasion */
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{ 0xb4735fac, 0 }, /* Metal Slader Glory */
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{ 0xf540677b, 4 }, /* Nobunaga no Yabou - Bushou Fuuun Roku */
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{ 0xeee9a682, 2 }, /* Nobunaga no Yabou - Sengoku Gunyuu Den (J) (PRG0) */
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{ 0xf9b4240f, 2 }, /* Nobunaga no Yabou - Sengoku Gunyuu Den (J) (PRG1) */
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{ 0x8ce478db, 2 }, /* Nobunaga's Ambition 2 */
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{ 0xf011e490, 4 }, /* Romance of The Three Kingdoms II */
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{ 0xbc80fb52, 1 }, /* Royal Blood */
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{ 0x184c2124, 4 }, /* Sangokushi II (J) (PRG0) */
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{ 0xee8e6553, 4 }, /* Sangokushi II (J) (PRG1) */
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{ 0xd532e98f, 1 }, /* Shin 4 Nin Uchi Mahjong - Yakuman Tengoku */
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{ 0x39f2ce4b, 2 }, /* Suikoden - Tenmei no Chikai */
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{ 0xbb7f829a, 0 }, /* Uchuu Keibitai SDF */
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{ 0xaca15643, 2 }, /* Uncharted Waters */
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};
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#define MMC5_NOCARTS (sizeof(MMC5CartList) / sizeof(MMC5CartList[0]))
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#define MMC5_NOCARTS (sizeof(MMC5CartList) / sizeof(MMC5CartList[0]))
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int DetectMMC5WRAMSize(uint32 crc32) {
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int x;
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for (x = 0; x < MMC5_NOCARTS; x++) {
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if (crc32 == MMC5CartList[x].crc32) {
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FCEU_printf(" >8KB external WRAM present. Use UNIF if you hack the ROM image.\n");
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if(MMC5CartList[x].size > 1)
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FCEU_printf(" >8KB external WRAM present. Use UNIF if you hack the ROM image.\n");
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return(MMC5CartList[x].size * 8);
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}
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}
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//mbg 04-aug-08 - previously, this was returning 8KB
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//but I changed it to return 64 because unlisted carts are probably homebrews, and they should probably use 64 (why not use it all?)
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//ch4 10-dec-08 - then f***ng for what all this shit above? let's give em all this 64k shit! Damn
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// homebrew must use it's own emulators or standart features.
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//adelikat 20-dec-08 - reverting back to return 64, sounds like it was changed back to 8 simply on principle. FCEUX is all encompassing, and that include
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//rom-hacking. We want it to be the best emulator for such purposes. So unless return 64 harms compatibility with anything else, I see now reason not to have it
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//mbg 29-mar-09 - I should note that mmc5 is in principle capable of 64KB, even if no real carts ever supported it.
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//This does not in principle break any games which share this mapper, and it should be OK for homebrew.
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//if there are games which need 8KB instead of 64KB default then lets add them to the list
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return 64;
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}
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@ -197,17 +192,11 @@ static void BuildWRAMSizeTable(void) {
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int x;
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for (x = 0; x < 8; x++) {
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switch (MMC5WRAMsize) {
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case 0: MMC5WRAMIndex[x] = 255; break; //X,X,X,X,X,X,X,X
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case 1: MMC5WRAMIndex[x] = (x > 3) ? 255 : 0; break; //0,0,0,0,X,X,X,X
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case 2: MMC5WRAMIndex[x] = (x & 4) >> 2; break; //0,0,0,0,1,1,1,1
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case 4: MMC5WRAMIndex[x] = (x > 3) ? 255 : (x & 3); break; //0,1,2,3,X,X,X,X
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case 8: MMC5WRAMIndex[x] = x; break; //0,1,2,3,4,5,6,7,8
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//mbg 8/6/08 - i added this to support 64KB of wram
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//now, I have at least one example (laser invasion) which actually uses size 1 but isnt in the crc list
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//so, whereas before my change on 8/4/08 we would have selected size 1, now we select size 8
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//this means that we could have just introduced an emulation bug, in case those games happened to
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//address, say, page 3. with size 1 that would resolve to [0] but in size 8 it resolves to [3].
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//so, you know what to do if there are problems.
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case 0: MMC5WRAMIndex[x] = 255; break; //X,X,X,X,X,X,X,X
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case 1: MMC5WRAMIndex[x] = (x > 3) ? 255 : 0; break; //0,0,0,0,X,X,X,X
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case 2: MMC5WRAMIndex[x] = (x & 4) >> 2; break; //0,0,0,0,1,1,1,1
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case 4: MMC5WRAMIndex[x] = (x > 3) ? 255 : (x & 3); break; //0,1,2,3,X,X,X,X
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case 8: MMC5WRAMIndex[x] = x; break; //0,1,2,3,4,5,6,7
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}
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}
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}
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@ -277,7 +266,6 @@ static void MMC5CHRB(void) {
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}
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static void MMC5WRAM(uint32 A, uint32 V) {
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//printf("%02x\n",V);
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V = MMC5WRAMIndex[V & 7];
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if (V != 255) {
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setprg8r(0x10, A, V);
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@ -349,12 +337,31 @@ static void MMC5PRG(void) {
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}
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static DECLFW(Mapper5_write) {
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if (A >= 0x5120 && A <= 0x5127) {
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mmc5ABMode = 0;
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CHRBanksA[A & 7] = V | ((MMC50x5130 & 0x3) << 8); //if we had a test case for this then we could test this, but it hasnt been verified
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//CHRBanksA[A&7]=V;
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MMC5CHRA();
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} else switch (A) {
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switch (A) {
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case 0x5100:
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mmc5psize = V;
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MMC5PRG();
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break;
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case 0x5101:
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mmc5vsize = V;
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if (!mmc5ABMode) {
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MMC5CHRB();
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MMC5CHRA();
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} else {
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MMC5CHRA();
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MMC5CHRB();
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}
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break;
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case 0x5102:
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WRAMMaskEnable[0] = V;
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break;
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case 0x5103:
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WRAMMaskEnable[1] = V;
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break;
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case 0x5104:
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CHRMode = V;
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MMC5HackCHRMode = V & 3;
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break;
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case 0x5105:
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{
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int x;
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@ -369,53 +376,50 @@ static DECLFW(Mapper5_write) {
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NTAMirroring = V;
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break;
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}
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case 0x5113: WRAMPage = V; MMC5WRAM(0x6000, V & 7); break;
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case 0x5100: mmc5psize = V; MMC5PRG(); break;
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case 0x5101:
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mmc5vsize = V;
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if (!mmc5ABMode) {
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MMC5CHRB();
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MMC5CHRA();
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} else {
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MMC5CHRA();
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MMC5CHRB();
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case 0x5106:
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if (V != NTFill)
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FCEU_dwmemset(MMC5fill, (V | (V << 8) | (V << 16) | (V << 24)), 0x3c0);
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NTFill = V;
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break;
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case 0x5107:
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if (V != ATFill) {
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unsigned char moop = V | (V << 2) | (V << 4) | (V << 6);
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FCEU_dwmemset(MMC5fill + 0x3c0, moop | (moop << 8) | (moop << 16) | (moop << 24), 0x40);
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}
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ATFill = V;
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break;
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case 0x5113:
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WRAMPage = V;
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MMC5WRAM(0x6000, V & 7);
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break;
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case 0x5114:
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case 0x5115:
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case 0x5116:
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case 0x5117: PRGBanks[A & 3] = V; MMC5PRG(); break;
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case 0x5117:
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PRGBanks[A & 3] = V;
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MMC5PRG();
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break;
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case 0x5120:
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case 0x5121:
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case 0x5122:
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case 0x5123:
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case 0x5124:
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case 0x5125:
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case 0x5126:
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case 0x5127:
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mmc5ABMode = 0;
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CHRBanksA[A & 7] = V | ((MMC50x5130 & 0x3) << 8);
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MMC5CHRA();
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break;
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case 0x5128:
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case 0x5129:
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case 0x512a:
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case 0x512b:
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mmc5ABMode = 1;
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CHRBanksB[A & 3] = V;
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CHRBanksB[A & 3] = V | ((MMC50x5130 & 0x3) << 8);
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MMC5CHRB();
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break;
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case 0x5102: WRAMMaskEnable[0] = V; break;
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case 0x5103: WRAMMaskEnable[1] = V; break;
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case 0x5104: CHRMode = V; MMC5HackCHRMode = V & 3; break;
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case 0x5106:
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if (V != NTFill) {
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uint32 t;
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t = V | (V << 8) | (V << 16) | (V << 24);
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FCEU_dwmemset(MMC5fill, t, 0x3c0);
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}
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NTFill = V;
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break;
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case 0x5107:
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if (V != ATFill) {
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unsigned char moop;
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uint32 t;
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moop = V | (V << 2) | (V << 4) | (V << 6);
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t = moop | (moop << 8) | (moop << 16) | (moop << 24);
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FCEU_dwmemset(MMC5fill + 0x3c0, t, 0x40);
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}
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ATFill = V;
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break;
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case 0x5130: MMC50x5130 = V; break;
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case 0x5200: MMC5HackSPMode = V; break;
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case 0x5201: MMC5HackSPScroll = (V >> 3) & 0x1F; break;
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case 0x5202: MMC5HackSPPage = V & 0x3F; break;
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@ -434,10 +438,11 @@ static DECLFR(MMC5_ReadROMRAM) {
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}
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static DECLFW(MMC5_WriteROMRAM) {
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if (A >= 0x8000)
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if (MMC5ROMWrProtect[(A - 0x8000) >> 13]) return;
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if ((A >= 0x8000) && (MMC5ROMWrProtect[(A - 0x8000) >> 13]))
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return;
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if (MMC5MemIn[(A - 0x6000) >> 13])
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if (((WRAMMaskEnable[0] & 3) | ((WRAMMaskEnable[1] & 3) << 2)) == 6) Page[A >> 11][A] = V;
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if (((WRAMMaskEnable[0] & 3) | ((WRAMMaskEnable[1] & 3) << 2)) == 6)
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Page[A >> 11][A] = V;
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}
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static DECLFW(MMC5_ExRAMWr) {
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@ -446,17 +451,12 @@ static DECLFW(MMC5_ExRAMWr) {
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}
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static DECLFR(MMC5_ExRAMRd) {
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// Not sure if this is correct, so I'll comment it out for now.
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// if(MMC5HackCHRMode>=2)
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return ExRAM[A & 0x3ff];
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// else
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// return(X.DB);
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return ExRAM[A & 0x3ff];
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}
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static DECLFR(MMC5_read) {
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switch (A) {
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case 0x5204:
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{
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case 0x5204: {
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uint8 x;
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X6502_IRQEnd(FCEU_IQEXT);
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x = MMC5IRQR;
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@ -466,8 +466,10 @@ static DECLFR(MMC5_read) {
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MMC5IRQR &= 0x40;
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return x;
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}
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case 0x5205: return(mul[0] * mul[1]);
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case 0x5206: return((mul[0] * mul[1]) >> 8);
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case 0x5205:
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return(mul[0] * mul[1]);
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case 0x5206:
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return((mul[0] * mul[1]) >> 8);
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}
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return(X.DB);
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}
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@ -492,17 +494,10 @@ void MMC5Synco(void) {
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MMC5CHRA();
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MMC5CHRB();
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}
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FCEU_dwmemset(MMC5fill, NTFill | (NTFill << 8) | (NTFill << 16) | (NTFill << 24), 0x3c0);
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{
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uint32 t;
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t = NTFill | (NTFill << 8) | (NTFill << 16) | (NTFill << 24);
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FCEU_dwmemset(MMC5fill, t, 0x3c0);
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}
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{
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unsigned char moop;
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uint32 t;
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moop = ATFill | (ATFill << 2) | (ATFill << 4) | (ATFill << 6);
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t = moop | (moop << 8) | (moop << 16) | (moop << 24);
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FCEU_dwmemset(MMC5fill + 0x3c0, t, 0x40);
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unsigned char moop = ATFill | (ATFill << 2) | (ATFill << 4) | (ATFill << 6);
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FCEU_dwmemset(MMC5fill + 0x3c0, moop | (moop << 8) | (moop << 16) | (moop << 24), 0x40);
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}
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X6502_IRQEnd(FCEU_IQEXT);
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MMC5HackCHRMode = CHRMode & 3;
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@ -560,7 +555,7 @@ static void Do5PCM() {
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}
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static void Do5PCMHQ() {
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uint32 V; //mbg merge 7/17/06 made uint32
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uint32 V;
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if (!(MMC5Sound.rawcontrol & 0x40) && MMC5Sound.raw)
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for (V = MMC5Sound.BC[2]; V < SOUNDTS; V++)
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WaveHi[V] += MMC5Sound.raw << 5;
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@ -643,7 +638,7 @@ static void Do5SQ(int P) {
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static void Do5SQHQ(int P) {
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static int tal[4] = { 1, 2, 4, 6 };
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uint32 V; //mbg merge 7/17/06 made uint32
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uint32 V;
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int32 amp, rthresh, wl;
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wl = MMC5Sound.wl[P] + 1;
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@ -835,24 +830,22 @@ void Mapper5_Init(CartInfo *info) {
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}
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// ELROM seems to have 0KB of WRAM
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// EKROM seems to have 8KB of WRAM
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// ETROM seems to have 16KB of WRAM
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// EWROM seems to have 32KB of WRAM
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// ETROM and EWROM are battery-backed, EKROM isn't.
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void ETROM_Init(CartInfo *info) {
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GenMMC5_Init(info, 16, info->battery);
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}
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// EKROM seems to have 8KB of WRAM, battery-backed
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// ETROM seems to have 16KB of WRAM, battery-backed
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// EWROM seems to have 32KB of WRAM, battery-backed
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void ELROM_Init(CartInfo *info) {
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GenMMC5_Init(info, 0, 0);
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}
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void EWROM_Init(CartInfo *info) {
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GenMMC5_Init(info, 32, info->battery);
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}
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void EKROM_Init(CartInfo *info) {
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GenMMC5_Init(info, 8, info->battery);
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}
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void ETROM_Init(CartInfo *info) {
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GenMMC5_Init(info, 16, info->battery);
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}
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void EWROM_Init(CartInfo *info) {
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GenMMC5_Init(info, 32, info->battery);
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}
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