rainbow: updated to latest mapper version
- RX/TX now uses FPGA-RAM to automatically send/receive messages - first 2K of FPGA-RAM are now mapped at $4800-$4fff - ESP registers updated - multiplication registers behavior fixed - $6000 WRAM mapping behavior fixed - mapper reset support added TODO: - AP_GET_CONFIG and AP_SET_CONFIG commands have been added, but are currently not supported in rainbow_esp.cpp
This commit is contained in:
contact@brokestudio.fr
parent
c0e1b86eda
commit
192fb02b46
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@ -10,7 +10,7 @@ class EspFirmware {
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public:
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virtual ~EspFirmware() = default;
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// Communication pins (dont care about UART details, directly transmit bytes)
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// Communication pins (don't care about UART details, directly transmit bytes)
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virtual void rx(uint8 v) = 0;
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virtual uint8 tx() = 0;
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@ -57,17 +57,19 @@
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#define CHIP_TYPE_CHR 1
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static uint8 prg_mode, bootloader;
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static uint32 prg[3], wram_bank, fpga_wram_bank;
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static uint32 chr[8];
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static uint8 prg[3], wram_bank, wram_chip_select, fpga_wram_bank;
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static uint16 chr[8];
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static uint8 chr_chip, chr_mode, chr_upper_bank;
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static uint8 mirr_mode, nt_set;
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static uint8 mul_a, mul_b, mul_result;
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static uint8 mul_a, mul_b;
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static uint16 mul_result;
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static uint8 rx_address, tx_address;
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static uint8 *WRAM = NULL;
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const uint32 WRAMSIZE = 32 * 1024;
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static uint8 *FPGA_WRAM = NULL;
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const uint32 FPGA_WRAMSIZE = 9 * 1024;
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const uint32 FPGA_WRAMSIZE = 8 * 1024;
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static uint8 *DUMMY_CHRRAM = NULL;
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const uint32 DUMMY_CHRRAMSIZE = 4 * 1024;
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@ -130,13 +132,15 @@ static SFORMAT SStateRegs[] =
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static EspFirmware *esp = NULL;
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static bool esp_enable;
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static bool irq_enable;
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static uint8 last_byte_read;
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static bool esp_irq_enable;
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static bool esp_message_received;
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static bool esp_message_sent;
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std::thread esp_RX;
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static void Rainbow13EspMapIrq(int32) {
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if (irq_enable)
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if (esp_irq_enable)
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{
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if (esp->getGpio4())
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if (esp_message_received)
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{
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X6502_IRQBegin(FCEU_IQEXT);
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}
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@ -149,6 +153,22 @@ static void Rainbow13EspMapIrq(int32) {
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// Mapper
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void esp_check_new_message(void) {
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while (esp != NULL) {
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// get new message if needed
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if (esp_enable && esp->getGpio4() && !esp_message_received)
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{
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uint8 message_length = esp->tx();
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FPGA_WRAM[rx_address << 8] = message_length;
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for (uint8 i = 0; i < message_length; i++)
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{
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FPGA_WRAM[(rx_address << 8) + 1 + i] = esp->tx();
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}
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esp_message_received = true;
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}
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}
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}
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static void Sync(void) {
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static uint8 *address;
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uint32 start;
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@ -195,29 +215,30 @@ static void Sync(void) {
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setprg8r(0x11, 0xe000, ~0);
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// $6000-$7fff
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if (WRAM)
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switch (wram_chip_select & 0x03)
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{
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switch (wram_bank & 0xC0)
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{
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case 0x00:
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case 0x00: // PRG-RAM
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if (WRAM)
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setprg8r(0x10, 0x6000, wram_bank & 0x03);
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break;
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case 0x40:
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setprg8r(0x12, 0x6000, 0x00);
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break;
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case 0x80:
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case 0x81:
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setprg8r(0x11, 0x6000, wram_bank & 0x7f);
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break;
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}
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break;
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case 0x01: // FPGA-RAM
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setprg8r(0x12, 0x6000, 0x00);
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break;
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case 0x02: // PRG-ROM
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case 0x03:
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setprg8r(0x11, 0x6000, wram_bank & 0x3f);
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break;
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}
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// $5000-$5fff
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if (bootloader == 1)
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setprg4r(0x11, 0x5000, 125);
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setprg4r(0x11, 0x5000, 125); // todo: why 125 ?!
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else
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setprg4r(0x12, 0x5000, fpga_wram_bank & 0x01);
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// $4800-$4fff
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setprg2r(0x12, 0x4800, 0);
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cart_chr_map = chr_chip + 0x10;
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switch (chr_mode)
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{
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@ -306,27 +327,81 @@ static DECLFW(Rainbow13SW) {
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}
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}
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static DECLFW(WRAM_0x6000Wr)
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{
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// $6000-$7fff
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switch (wram_chip_select & 0x03)
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{
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case 0x00: // PRG-RAM
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CartBW(A, V);
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break;
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case 0x01: // FPGA-RAM
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FPGA_WRAM[A & 0x1fff] = V;
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break;
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case 0x02: //PRG-ROM
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case 0x03:
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CartBW(A, V);
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break;
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}
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}
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static DECLFR(WRAM_0x6000Rd)
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{
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// $6000-$7fff
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switch (wram_chip_select & 0x03)
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{
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case 0x00: // PRG-RAM
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CartBR(A);
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break;
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case 0x01: // FPGA-RAM
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return FPGA_WRAM[A & 0x1fff];
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break;
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case 0x02: //PRG-ROM
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case 0x03:
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CartBR(A);
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break;
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}
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}
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static DECLFW(WRAM_0x5000Wr)
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{
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FPGA_WRAM[(A & 0xfff) | ((fpga_wram_bank & 0x01) << 12)] = V;
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}
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static DECLFR(WRAM_0x5000Rd)
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{
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return FPGA_WRAM[(A & 0xfff) | ((fpga_wram_bank & 0x01) << 12)];
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}
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static DECLFW(FPGA_0x4800Wr)
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{
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FPGA_WRAM[A & 0x7ff] = V;
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}
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static DECLFR(FPGA_0x4800Rd)
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{
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return FPGA_WRAM[A & 0x7ff];
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}
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static DECLFR(Rainbow13Read) {
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switch (A)
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{
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case 0x4100:
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{
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if (esp_enable) last_byte_read = esp->tx();
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else FCEU_printf("RAINBOW warning: $4101.0 is not set\n");
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return last_byte_read;
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uint8 esp_enable_flag = esp_enable ? 0x01 : 0x00;
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uint8 irq_enable_flag = esp_irq_enable ? 0x02 : 0x00;
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UDBG("RAINBOW read flags %04x => %02xs\n", A, esp_enable_flag | irq_enable_flag);
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return esp_enable_flag | irq_enable_flag;
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}
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case 0x4101:
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{
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uint8 esp_rts_flag = esp->getGpio4() ? 0x80 : 0x00;
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uint8 esp_enable_flag = esp_enable ? 0x01 : 0x00;
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uint8 irq_enable_flag = irq_enable ? 0x40 : 0x00;
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UDBG("RAINBOW read flags %04x => %02x\n", A, esp_rts_flag | esp_enable_flag | irq_enable_flag);
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return esp_rts_flag | esp_enable_flag | irq_enable_flag;
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uint8 message_received = esp_message_received ? 1 << 7 : 0;
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uint8 esp_rts_flag = esp->getGpio4() ? 0x40 : 0x00;
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return message_received | esp_rts_flag;
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}
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case 0x4102:
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{
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return esp_message_sent << 7;
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}
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case 0x4110: return (nt_set << 6) | (mirr_mode << 4) | (chr_chip << 3) | (chr_mode << 1) | prg_mode;
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case 0x4113: return MAPPER_VERSION;
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case 0x4160: return (mul_result >> 8) & 0xff;
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case 0x4161: return mul_result & 0xff;
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case 0x4160: return mul_result & 0xff;
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case 0x4161: return (mul_result >> 8) & 0xff;
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default:
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return 0;
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}
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@ -336,18 +411,42 @@ static DECLFW(Rainbow13Write) {
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switch (A)
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{
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case 0x4100:
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if (esp_enable) esp->rx(V);
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else FCEU_printf("RAINBOW warning: $4101.0 is not set\n");
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esp_enable = V & 0x01;
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esp_irq_enable = V & 0x02;
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break;
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case 0x4101:
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esp_enable = V & 0x01;
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irq_enable = V & 0x40;
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if (esp_enable) esp_message_received = false;
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else FCEU_printf("RAINBOW warning: $4100.0 is not set\n");
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break;
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case 0x4102:
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if (esp_enable)
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{
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esp_message_sent = false;
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uint8 message_length = FPGA_WRAM[tx_address << 8];
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esp->rx(message_length);
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for (uint8 i = 0; i < message_length; i++)
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{
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esp->rx(FPGA_WRAM[(tx_address << 8) + 1 + i]);
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}
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esp_message_sent = true;
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}
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else FCEU_printf("RAINBOW warning: $4100.0 is not set\n");
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break;
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case 0x4103:
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rx_address = V & 0x03;
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break;
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case 0x4104:
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tx_address = V & 0x03;
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break;
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case 0x4120: prg[0] = V; Sync(); break;
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case 0x4121: prg[1] = V & 0x3f; Sync(); break;
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case 0x4122: prg[2] = V & 0x3f; Sync(); break;
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case 0x4123: fpga_wram_bank = V & 0x01; Sync(); break;
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case 0x4124: wram_bank = V; Sync(); break;
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case 0x4124:
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wram_bank = V & 0x3f;
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wram_chip_select = (V & 0xc0) >> 6;
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Sync();
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break;
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case 0x4110:
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prg_mode = V & 0x01;
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chr_chip = (V & 0x08) >> 3;
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@ -366,12 +465,15 @@ static DECLFW(Rainbow13Write) {
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case 0x4137:
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{
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int bank = A & 0x07;
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chr[bank] = ( chr[bank] & 0x100 ) | ( V & 0xff );
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if (chr_mode == CHR_MODE_1K)
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chr[bank] = (chr_upper_bank << 8) | (V & 0xff);
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else
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chr[bank] = (chr[bank] & 0x100) | (V & 0xff);
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Sync();
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break;
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}
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case 0x4138: chr_upper_bank = V & 0x01; Sync(); break;
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/*
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case 0x4170:
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case 0x4171:
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case 0x4172:
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@ -386,7 +488,7 @@ static DECLFW(Rainbow13Write) {
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Sync();
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break;
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}
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*/
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case 0x4140: IRQLatch = V; break;
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case 0x4141: IRQReload = 1; break;
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case 0x4142:
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@ -726,6 +828,14 @@ static void Rainbow13PPUWrite(uint32 A, uint8 V) {
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FFCEUX_PPUWrite_Default(A, V);
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}
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static void Rainbow13Reset(void) {
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esp_enable = false;
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esp_message_received = false;
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rx_address = 0;
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tx_address = 0;
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IRQa = 0;
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}
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static void Rainbow13Power(void) {
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// mapper
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@ -740,9 +850,10 @@ static void Rainbow13Power(void) {
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if (WRAM)
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FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
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FCEU_CheatAddRAM(FPGA_WRAMSIZE >> 10, 0x5000, FPGA_WRAM);
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FCEU_CheatAddRAM(0x800 >> 10, 0x4800, FPGA_WRAM);
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// mapper registers (writes)
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SetWriteHandler(0x4100, 0x4177, Rainbow13Write); //0x4161
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SetWriteHandler(0x4100, 0x4161, Rainbow13Write);
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// mapper registers (reads)
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SetReadHandler(0x4100, 0x4161, Rainbow13Read);
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@ -750,6 +861,18 @@ static void Rainbow13Power(void) {
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// audio expansion registers (writes)
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SetWriteHandler(0x4150, 0x4158, Rainbow13SW);
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// FPGA WRAM @ $4800-$4fff (reads/writes)
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SetWriteHandler(0x4800, 0x4fff, FPGA_0x4800Wr);
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SetReadHandler(0x4800, 0x4fff, FPGA_0x4800Rd);
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// FPGA WRAM @ $5000-$5fff (reads/writes)
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SetWriteHandler(0x5000, 0x5fff, WRAM_0x5000Wr);
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SetReadHandler(0x5000, 0x5fff, WRAM_0x5000Rd);
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// WRAM @ $6000-$7fff (reads/writes)
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SetWriteHandler(0x6000, 0x7fff, WRAM_0x6000Wr);
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SetReadHandler(0x6000, 0x7fff, WRAM_0x6000Rd);
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// self-flashing
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flash_mode[CHIP_TYPE_PRG] = 0;
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flash_mode[CHIP_TYPE_CHR] = 0;
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@ -778,8 +901,9 @@ static void Rainbow13Power(void) {
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// ESP firmware
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esp = new BrokeStudioFirmware;
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esp_enable = false;
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irq_enable = false;
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last_byte_read = 0x00;
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esp_irq_enable = false;
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esp_message_received = false;
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esp_RX = std::thread (esp_check_new_message);
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}
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static void Rainbow13Close(void)
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@ -820,6 +944,8 @@ static void Rainbow13Close(void)
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if (esp)
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{
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esp_enable = false;
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esp_RX.detach();
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delete esp;
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esp = NULL;
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}
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@ -1051,6 +1177,7 @@ void NSFRainbow13_Init(void) {
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void RAINBOW13_Init(CartInfo *info) {
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int save_game_index = 0;
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info->Power = Rainbow13Power;
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info->Reset = Rainbow13Reset;
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info->Close = Rainbow13Close;
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GameHBIRQHook = Rainbow13hb;
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@ -1076,6 +1203,12 @@ void RAINBOW13_Init(CartInfo *info) {
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FPGA_WRAM = (uint8*)FCEU_gmalloc(FPGA_WRAMSIZE);
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SetupCartPRGMapping(0x12, FPGA_WRAM, FPGA_WRAMSIZE, 1);
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AddExState(FPGA_WRAM, FPGA_WRAMSIZE, 0, "FPGA_WRAM");
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if (info->battery)
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{
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info->SaveGame[save_game_index] = FPGA_WRAM;
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info->SaveGameLen[save_game_index] = FPGA_WRAMSIZE;
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save_game_index++;
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}
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// PRG FLASH ROM
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PRG_FLASHROM = (uint8*)FCEU_gmalloc(PRG_FLASHROMSIZE);
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@ -197,10 +197,6 @@ uint8 BrokeStudioFirmware::tx() {
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// Fill buffer with the next message (if needed)
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if (this->tx_buffer.empty() && !this->tx_messages.empty()) {
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std::deque<uint8> message = this->tx_messages.front();
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// add last received byte first to match hardware behavior
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// it's more of a mapper thing though ...
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// needs a dummy $5000 read when reading data from buffer
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this->tx_buffer.push_back(last_byte_read);
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this->tx_buffer.insert(this->tx_buffer.end(), message.begin(), message.end());
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this->tx_messages.pop_front();
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}
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@ -70,6 +70,8 @@ private:
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// AP CMDS
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AP_GET_SSID,
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AP_GET_IP,
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AP_GET_CONFIG,
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AP_SET_CONFIG,
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// RND CMDS
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RND_GET_BYTE,
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@ -126,6 +128,7 @@ private:
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WIFI_STATUS,
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SSID,
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IP_ADDRESS,
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AP_CONFIG,
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// RND CMDS
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RND_BYTE,
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@ -352,7 +352,7 @@ uint8 GetMem(uint16 A) {
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case 6: return RawReg4016;
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case 7: return IRQFrameMode;
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}
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else if ((A >= 0x4018) && (A < 0x5000)) // AnS: changed the range, so MMC5 ExRAM can be watched in the Hexeditor
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else if ((A >= 0x4018) && (A < 0x4800)) // AnS: changed the range, so MMC5 ExRAM can be watched in the Hexeditor | BrokeStudio: changed the range, so Rainbow FPGA-RAM can be watched in the Hexeditor
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return 0xFF;
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if (GameInfo) { //adelikat: 11/17/09: Prevent crash if this is called with no game loaded.
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uint32 ret;
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