113 lines
3.1 KiB
Plaintext
113 lines
3.1 KiB
Plaintext
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SMB2j Revision "A". Mapper #50 Info
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-----------------------------------
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12.09.2000
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V2.00
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Mapper info by The Mad Dumper
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---
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This mapper has been assigned the number 50. (that's 50 decimal)
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Wow, another SMB2j cart! This one is alot different than the last one I
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worked on. It has a single 128K PRG ROM and VRAM. The other SMB2j had
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64K PRG and 8K CHR. Not much more to say other than this has one very
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fucked up mapper circuit on it!
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---
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The hardware:
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It consists of 6 TTL chips (74163, 74157, 74139, 7400, 7474, and a 4020),
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1 8K RAM chip for the VRAM, and 1 128K 28 pin ROM. There is some
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"M^2L" logic on the board (Mickey-Mouse Logic). It is a 3 input OR gate
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made out of 3 diodes and a resistor.
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Also, they swapped D3 and D6, as well as A1 and A3. Why this was done, I
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have no idea. It sure mussed up my REing efforts! I desoldered and read
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the ROM out through the EPROM programmer as a check and was not happy to
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find the data seemingly corrupt!
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After converting the ROM image over via some QBasic, it matched up great.
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You do not have to swap the addresses or data bytes; I have done this
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already in the released .NES ROM.
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---
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There are two registers on this cartridge. They are located in the 4000h-
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5FFFh block.
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Funny addresses are decoded for the register selection; presumably so they
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did not interfere with the FDS or NES registers.
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A15 ... A0
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-------------------
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010x xxxQ x01x xxxx
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x = Don't Care
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0 = must be 0
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1 = must be 1
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Q = register selection bit. 0 = ROM Page; 1 = IRQ Timer Enable
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-
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ROM Page Register:
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------------------
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Accessed when the address lines are in the above state. An example address
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would be 4020h. 4021h, 4022h, ... 403Fh, 40A0h, 40A1h, ... are all mirrors
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of this register. Writing here stores the desired bank #.
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7 bit 0
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---------
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xxxx DCBA
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These 4 bits are shown below in the ROM memory map. Note that they are
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somewhat "scrambled". The value of this register is unknown at powerup.
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-
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IRQ Timer.
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7 bit 0
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---------
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xxxx xxxI
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The IRQ Timer register controls the state of the IRQ timer. Writing here
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will turn it on or off. Turning the IRQ timer off resets it to 0. Writing
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a 1 here will turn the timer on, while writing a 0 will turn it off.
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The timer is composed of a binary ripple counter. After 4096 M2 cycles,
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/IRQ is pulled low. This is about 36 scanlines. The idea behind the timer
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is to split the screen for the score bar at the top. You start it at the
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beginning of the VBI routine, and then after 36 scanlines, it sends the IRQ
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which clears the timer, and resets the scroll registers. The value of this
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register is unknown at powerup.
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---
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ROM Memory Map:
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Address Range | Bank bits: 3210
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-------------------------------
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6000h-7FFFh 1111
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8000h-9FFFh 1000
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A000h-BFFFh 1001
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C000h-DFFFh DACB -- Selectable page
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E000h-FFFFh 1011
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The ROM is composed of 16 8K banks. The 4 bank bits are shown above. Bit 3
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is the MSB while bit 0 is the LSB. 6000h-7FFFh is set to 1111b, or bank 0fh.
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All banks are FIXED except the bank at C000h-DFFFh. Only it can be changed.
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