98 lines
3.4 KiB
Plaintext
98 lines
3.4 KiB
Plaintext
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This is an email posted to nesdev by Ki a while back. I have removed one
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line at the end regarding the B flag of the cpu(the information was
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incorrect, which Ki noted in a later email).
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--------------------------------------------------------------------------------
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By reading Brad's NESSOUND document, we know that there is a
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"frame counter" in the NES/FC APU. I would like to post
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some more on this.
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The frame counter is reset upon any write to $4017. It is
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reset at system power-on as well, but is NOT reset upon
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system reset.
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Thanks to Samus Aran, we now know the exact period of the
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PPU's single frame. In another words, we are now sure that
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the NMI occurs on every 29780 2/3 CPU cycles.
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However, the APU's single frame is NOT 29780 2/3 CPU cycles.
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What I mean by "APU's single frame" here is that it is the
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number of CPU cycles taken between the frame IRQs.
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The APU's single frame seems to be:
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1789772.727... / 60 = 29829 6/11 [CPU CYCLE]
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Below is a simple diagram which shows the difference
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in periods of the PPU's single frame and the APU's.
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RESET 29780 2/3 CPU CYCLES NMI
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PPU |------------------------------------------|
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| 29829 6/11 CPU CYCLES IRQ
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APU |----------|----------|----------|----------|
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Note that if you write $00 to $4017 on every NMI, the frame
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IRQ would NEVER go off even if it is enabled. This is because
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the the period of NMI is slightly shorter than the period of
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the frame IRQ. This causes the frame counter to be reset
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before the frame IRQ goes off.
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When you write zero to bit 7 of $4017, the frame counter will
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be reset, and the first sound update will be done after 7457 CPU
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cycles (i.e. 29829/4). 2nd update will be done 7457 after that,
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same goes for 3rd update and 4th update, but the frame IRQ occurs
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on 4th update, resetting the frame counter as well.
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When you write 1 to bit 7 of $4017, the frame counter will be
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reset, but the first sound update will occur at the same time.
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2nd, 3rd, and 4th update will be done after 7457, 14914, 22371
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CPU cycles after the first update respectively, but the 5th
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update will be 14914 cycles after the 4th update. This causes
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sound output to last 1.25 times longer than that of bit 7 = 0.
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$4017W:
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o when the MSB of $4017 is 0:
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bit7=0
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|---------|---------|---------|---------|---------|---------|----
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1st 2nd 3rd 4th 5th(1st) 6th(2nd)
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o when the MSB of $4017 is 1:
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bit7=1
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|---------|---------|---------|-------------------|---------|----
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1st 2nd 3rd 4th 5th(1st) 6th(2nd)
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On 1st, 3rd, 5th, ... updates, the envelope decay and the
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linear counter are updated.
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On 2nd, 4th, 6th, ... updates, the envelope decay, the
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linear counter, the length counter, and the frequency sweep
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are updated.
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----
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The original info was provided by goroh, and verified by me.
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However, it could still be wrong. Please tell me if you
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find anything wrong.
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----
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(Correction from my last posting)
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I have checked once again and it turned out that the frame IRQ
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was NOT disabled upon system reset. What actually prevented the
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frame IRQ to occur after system reset was, in fact, the I flag.
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I checked this flag shortly after system reset (right after stack
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pointer was initialized), and the flag was 1, although I never
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executed "sei" after reset. Therefore the I flag of the PR2A03G
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is 1 on system reset.
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Thanks Matthew Conte and Samus Aran for pointing out the
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inaccuracy.
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