154 lines
4.8 KiB
Plaintext
154 lines
4.8 KiB
Plaintext
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FCE Ultra Save State Format
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Updated: Mar 9, 2003
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---------------------------------------
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FCE Ultra's save state format is now designed to be as forward and backwards
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compatible as possible. This is achieved through the (over)use of chunks.
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All multiple-byte variables are stored LSB(least significant byte)-first.
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Data types:
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(u)int8 - (un)signed 8 bit variable(also referred to as "byte")
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(u)int16 - (un)signed 16 bit variable
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(u)int32 - (un)signed 32 bit variable
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-- Main File Header:
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The main file header is 16-bytes in length. The first three bytes contain
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the string "FCS". The next byte contains the version of FCE Ultra that saved
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this save state. This document only applies to version "53"(.53) and higher.
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After the version byte, the size of the entire file in bytes(minus the 16 byte
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main file header) is stored. The rest of the header is currently unused
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and should be nulled out. Example of relevant parts:
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FCS <uint8 version> <uint32 totalsize>
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-- Section Chunks:
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Sections chunk headers are 5-bytes in length. The first byte defines what
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section it is, the next four bytes define the total size of the section
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(including the section chunk header).
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<uint8 section> <uint32 size>
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Section definitions:
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1 - "CPU"
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2 - "CPUC"
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3 - "PPU"
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4 - "CTLR"
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5 - "SND"
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16 - "EXTRA"
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-- Subsection Chunks
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Subsection chunks are stored within section chunks. They contain the actual
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state data. Each subsection chunk is composed of an 8-byte header and the data.
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The header contains a description(a name) and the size of the data contained
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in the chunk:
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<uint8 description[4]> <uint32 size>
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The name is a four-byte string. It does not need to be null-terminated.
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If the string is less than four bytes in length, the remaining unused bytes
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must be null.
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-- Subsection Chunk Description Definitions
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Note that not all subsection chunk description definitions listed below
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are guaranteed to be in the section chunk. It's just a list of what CAN
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be in a section chunk. This especially applies to the "EXTRA" subsection.
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---- Section "CPU"
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Name: Type: Description:
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PC uint16 Program Counter
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A uint8 Accumulator
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P uint8 Processor status register
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X uint8 X register
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Y uint8 Y register
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S uint8 Stack pointer
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RAM uint8[0x800] 2KB work RAM
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---- Section "CPUC" (emulator specific)
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Name: Type: Description:
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JAMM uint8 Non-zero value if CPU in a "jammed" state
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IRQL uint8 Non-zero value if IRQs are to be generated constantly
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ICoa int32 Temporary cycle counter
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ICou int32 Cycle counter
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---- Section "PPU"
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Name: Type: Description:
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NTAR uint8[0x800] 2 KB of name/attribute table RAM
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PRAM uint8[32] 32 bytes of palette index RAM
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SPRA uint8[0x100] 256 bytes of sprite RAM
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PPU uint8[4] Last values written to $2000 and $2001, the PPU
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status register, and the last value written to
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$2003.
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XOFF uint8 Tile X-offset.
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VTOG uint8 Toggle used by $2005 and $2006.
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RADD uint16 PPU Address Register(address written to/read from
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when $2007 is accessed).
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TADD uint16 PPU Address Register
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VBUF uint8 VRAM Read Buffer
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PGEN uint8 PPU "general" latch. See Ki's document.
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---- Section "CTLR" (somewhat emulator specific)
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Name: Type: Description:
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J1RB uint8 Bit to be returned when first joystick is read.
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J2RB uint8 Bit to be returned when second joystick is read.
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---- Section "SND" (somewhat emulator specific)
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NREG uint16 Noise LFSR.
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P17 uint8 Last byte written to $4017.
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PBIN uint8 DMC bit index.
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PAIN uint32 DMC address index(from $8000).
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PSIN uint32 DMC length counter(how many bytes left
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to fetch).
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<to be finished>
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---- Section "EXTRA" (varying emulator specificness)
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For iNES-format games(incomplete, and doesn't apply to every game):
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Name: Type: Description:
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WRAM uint8[0x2000] 8KB of WRAM at $6000-$7fff
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MEXR uint8[0x8000] (very emulator specific)
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CHRR uint8[0x2000] 8KB of CHR RAM at $0000-$1fff(in PPU address space).
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EXNR uint8[0x800] Extra 2KB of name/attribute table RAM.
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MPBY uint8[32] (very emulator specific)
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MIRR uint8 Current mirroring:
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0 = "Horizontal"
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1 = "Vertical"
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$10 = Mirror from $2000
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$11 = Mirror from $2400
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IRQC uint32 Generic IRQ counter
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IQL1 uint32 Generic IRQ latch
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IQL2 uint32 Generic IRQ latch
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IRQA uint8 Generic IRQ on/off register.
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PBL uint8[4] List of 4 8KB ROM banks paged in at $8000-$FFFF
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CBL uint8[8] List of 8 1KB VROM banks page in at $0000-$1FFF(PPU).
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For FDS games(incomplete):
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Name: Type: Description:
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DDT<x> uint8[65500] Disk data for side x(0-3).
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FDSR uint8[0x8000] 32 KB of work RAM
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CHRR uint8[0x2000] 8 KB of CHR RAM
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IRQC uint32 IRQ counter
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IQL1 uint32 IRQ latch
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IRQA uint8 IRQ on/off.
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WAVE uint8[64] Carrier waveform data.
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MWAV uint8[32] Modulator waveform data.
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AMPL uint8[2] Amplitude data.
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