Let's add these too.
This commit is contained in:
iq_132
parent
65e6c74b2a
commit
f733f2625d
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@ -93,7 +93,7 @@ depobj := $(drvobj) \
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tilemap_generic.o tiles_generic.o timer.o vector.o \
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\
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6821pia.o 8255ppi.o 8257dma.o eeprom.o gaelco_crypt.o joyprocess.o nb1414m4.o nb1414m4_8bit.o nmk004.o nmk112.o kaneko_tmap.o mb87078.o mermaid.o \
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pandora.o resnet.o seibusnd.o sknsspr.o slapstic.o st0020.o t5182.o timekpr.o tms34061.o v3021.o vdc.o tms9928a.o \
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namcoio.o pandora.o resnet.o seibusnd.o sknsspr.o slapstic.o st0020.o t5182.o timekpr.o tms34061.o v3021.o vdc.o tms9928a.o \
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\
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ay8910.o burn_y8950.o burn_ym2151.o burn_ym2203.o burn_ym2413.o burn_ym2608.o burn_ym2610.o burn_ym2612.o \
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burn_ym3526.o burn_ym3812.o burn_ymf278b.o c6280.o dac.o es5506.o es8712.o flt_rc.o fm.o fmopl.o gaelco.o ics2115.o iremga20.o \
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@ -0,0 +1,461 @@
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// license:BSD-3-Clause
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// copyright-holders:Nicola Salmoria
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/***************************************************************************
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The following Namco custom chips are all instances of the same 4-bit MCU,
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the Fujitsu MB8843 (42-pin DIP package) and MB8842/MB8844 (28-pin DIP),
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differently programmed.
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chip MCU pins function
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---- ------ ---- --------
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56XX 42 I/O (coin management built-in)
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58XX 42 I/O (coin management built-in)
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62XX 28 I/O and explosion (noise) generator
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16XX interface:
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---------------
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Super Pac Man 56XX 56XX ---- ----
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Pac & Pal 56XX 59XX ---- ----
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Mappy 58XX 58XX ---- ----
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Phozon 58XX 56XX ---- ----
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The Tower of Druaga 58XX 56XX ---- ----
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Grobda 58XX 56XX ---- ----
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Dig Dug II 58XX 56XX ---- ----
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Motos 56XX 56XX ---- ----
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Gaplus 56XX 58XX 62XX ----
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Gaplus (alt.) 58XX 56XX 62XX ----
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Libble Rabble 58XX 56XX 56XX ----
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Toy Pop 58XX 56XX 56XX ----
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Pinouts:
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MB8843 MB8842/MB8844
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+------+ +------+
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EXTAL|1 42|Vcc EXTAL|1 28|Vcc
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XTAL|2 41|K3 XTAL|2 27|K3
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/RESET|3 40|K2 /RESET|3 26|K2
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/IRQ|4 39|K1 O0|4 25|K1
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SO|5 38|K0 O1|5 24|K0
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SI|6 37|R15 O2|6 23|R10 /IRQ
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/SC /TO|7 36|R14 O3|7 22|R9 /TC
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/TC|8 35|R13 O4|8 21|R8
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P0|9 34|R12 O5|9 20|R7
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P1|10 33|R11 O6|10 19|R6
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P2|11 32|R10 O7|11 18|R5
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P3|12 31|R9 R0|12 17|R4
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O0|13 30|R8 R1|13 16|R3
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O1|14 29|R7 GND|14 15|R2
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O2|15 28|R6 +------+
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O3|16 27|R5
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O4|17 26|R4
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O5|18 25|R3
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O6|19 24|R2
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O7|20 23|R1
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GND|21 22|R0
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+------+
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O O R R R K
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62XX O O IO O I
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P O O R R R R K
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56XX O O O I I I IO I
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58XX O O O I I I IO I
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59XX O O O I I I IO I
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Namco custom I/O chips 56XX, 58XX, 59XX
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These chips work together with a 16XX, that interfaces them with the buffer
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RAM. Each chip uses 16 nibbles of memory; the 16XX supports up to 4 chips,
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but most games use only 2.
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The 56XX, 58XX and 59XX are pin-to-pin compatible, but not functionally equivalent:
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they provide the same functions, but the command codes and memory addresses
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are different, so they cannot be exchanged.
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The devices have 42 pins. There are 16 input lines and 8 output lines to be
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used for I/O.
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pin description
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--- -----------
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1 clock (Mappy, Super Pac-Man)
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2 clock (Gaplus; equivalent to the above?)
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3 reset
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4 irq
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5-6 (to/from 16XX) (this is probably a normal I/O port used to synchronize with the 16XX)
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7-8 ?
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9-12 address to r/w from RAM; 12 also goes to the 16XX and acts as r/w line, so
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the chip can only read from addresses 0-7 and only write to addresses 8-F
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(this is probably a normal I/O port used for that purpose)
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13-16 out port A
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17-20 out port B
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21 GND
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22-25 in port B
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26-29 in port C
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30-33 in port D
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34-37 (to 16XX) probably data to r/w from RAM
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(this is probably a normal I/O port used for that purpose)
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38-41 in port A
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42 Vcc
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TODO:
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- It's likely that the 56XX and 58XX chips, when in "coin mode", also internally
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handle outputs for start lamps, coin counters and coin lockout, like the 51XX.
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Such lines are NOT present in the Mappy and Super Pacman schematics, so they
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were probably not used for those games, but they might have been used in
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others (most likely Gaplus).
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***************************************************************************/
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#include "burnint.h"
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#include "driver.h"
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struct ChipData
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{
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UINT8 (*in_0_cb)(UINT8);
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UINT8 (*in_1_cb)(UINT8);
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UINT8 (*in_2_cb)(UINT8);
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UINT8 (*in_3_cb)(UINT8);
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void (*out_0_cb)(UINT8, UINT8);
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void (*out_1_cb)(UINT8, UINT8);
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UINT8 ram[16];
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INT32 reset;
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INT32 lastcoins;
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INT32 lastbuttons;
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INT32 credits;
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INT32 coins[2];
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INT32 coins_per_cred[2];
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INT32 creds_per_coin[2];
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INT32 in_count;
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};
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static struct ChipData Chips[5];
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static UINT8 fakeIn(UINT8) { return 0; }
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static void fakeOut(UINT8,UINT8) { }
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void namcoio_init(INT32 chip, UINT8 (*in0)(UINT8), UINT8 (*in1)(UINT8), UINT8 (*in2)(UINT8), UINT8 (*in3)(UINT8), void (*out0)(UINT8, UINT8), void (*out1)(UINT8, UINT8))
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{
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ChipData *ptr = &Chips[chip];
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ptr->in_0_cb = (in0 == NULL) ? fakeIn : in0;
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ptr->in_1_cb = (in1 == NULL) ? fakeIn : in1;
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ptr->in_2_cb = (in2 == NULL) ? fakeIn : in2;
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ptr->in_3_cb = (in3 == NULL) ? fakeIn : in3;
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ptr->out_0_cb = (out0 == NULL) ? fakeOut : out0;
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ptr->out_1_cb = (out1 == NULL) ? fakeOut : out1;
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void namcoio_set_reset_line(INT32 chip, INT32 state)
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{
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ChipData *ptr = &Chips[chip];
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ptr->reset = (state == ASSERT_LINE) ? 1 : 0;
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if (state != CLEAR_LINE)
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{
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/* reset internal registers */
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ptr->credits = 0;
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ptr->coins[0] = 0;
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ptr->coins_per_cred[0] = 1;
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ptr->creds_per_coin[0] = 1;
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ptr->coins[1] = 0;
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ptr->coins_per_cred[1] = 1;
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ptr->creds_per_coin[1] = 1;
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ptr->in_count = 0;
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}
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}
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void namcoio_reset(INT32 chip)
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{
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namcoio_set_reset_line(chip, 1);
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namcoio_set_reset_line(chip, 0);
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}
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/*****************************************************************************
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DEVICE HANDLERS
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*****************************************************************************/
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#define IORAM_READ(offset) (ptr->ram[offset] & 0x0f)
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#define IORAM_WRITE(offset,data) {ptr->ram[offset] = (data) & 0x0f;}
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static void handle_coins( INT32 chip, int swap )
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{
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int val, toggled;
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int credit_add = 0;
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int credit_sub = 0;
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int button;
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ChipData *ptr = &Chips[chip];
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val = ~ptr->in_0_cb(0 & 0x0f); // pins 38-41
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toggled = val ^ ptr->lastcoins;
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ptr->lastcoins = val;
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/* check coin insertion */
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if (val & toggled & 0x01)
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{
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ptr->coins[0]++;
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if (ptr->coins[0] >= (ptr->coins_per_cred[0] & 7))
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{
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credit_add = ptr->creds_per_coin[0] - (ptr->coins_per_cred[0] >> 3);
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ptr->coins[0] -= ptr->coins_per_cred[0] & 7;
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}
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else if (ptr->coins_per_cred[0] & 8)
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credit_add = 1;
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}
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if (val & toggled & 0x02)
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{
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ptr->coins[1]++;
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if (ptr->coins[1] >= (ptr->coins_per_cred[1] & 7))
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{
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credit_add = ptr->creds_per_coin[1] - (ptr->coins_per_cred[1] >> 3);
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ptr->coins[1] -= ptr->coins_per_cred[1] & 7;
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}
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else if (ptr->coins_per_cred[1] & 8)
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credit_add = 1;
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}
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if (val & toggled & 0x08)
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{
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credit_add = 1;
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}
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val = ~ptr->in_3_cb(0 & 0x0f); // pins 30-33
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toggled = val ^ ptr->lastbuttons;
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ptr->lastbuttons = val;
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/* check start buttons, only if the game allows */
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if (IORAM_READ(9) == 0)
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// the other argument is IORAM_READ(10) = 1, meaning unknown
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{
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if (val & toggled & 0x04)
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{
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if (ptr->credits >= 1) credit_sub = 1;
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}
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else if (val & toggled & 0x08)
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{
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if (ptr->credits >= 2) credit_sub = 2;
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}
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}
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ptr->credits += credit_add - credit_sub;
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IORAM_WRITE(0 ^ swap, ptr->credits / 10); // BCD credits
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IORAM_WRITE(1 ^ swap, ptr->credits % 10); // BCD credits
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IORAM_WRITE(2 ^ swap, credit_add); // credit increment (coin inputs)
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IORAM_WRITE(3 ^ swap, credit_sub); // credit decrement (start buttons)
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IORAM_WRITE(4, ~ptr->in_1_cb(0 & 0x0f)); // pins 22-25
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button = ((val & 0x05) << 1) | (val & toggled & 0x05);
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IORAM_WRITE(5, button); // pins 30 & 32 normal and impulse
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IORAM_WRITE(6, ~ptr->in_2_cb(0 & 0x0f)); // pins 26-29
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button = (val & 0x0a) | ((val & toggled & 0x0a) >> 1);
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IORAM_WRITE(7, button); // pins 31 & 33 normal and impulse
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}
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void namco_customio_run(INT32 chip)
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{
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ChipData *ptr = &Chips[chip];
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switch (IORAM_READ(8))
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{
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case 1: // read switch inputs
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IORAM_WRITE(0, ~ptr->in_0_cb(0 & 0x0f)); // pins 38-41
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IORAM_WRITE(1, ~ptr->in_1_cb(0 & 0x0f)); // pins 22-25
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IORAM_WRITE(2, ~ptr->in_2_cb(0 & 0x0f)); // pins 26-29
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IORAM_WRITE(3, ~ptr->in_3_cb(0 & 0x0f)); // pins 30-33
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ptr->out_0_cb((UINT8)0, IORAM_READ(9)); // output to pins 13-16 (motos, pacnpal, gaplus)
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ptr->out_1_cb((UINT8)0, IORAM_READ(10)); // output to pins 17-20 (gaplus)
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break;
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case 2: // initialize coinage settings
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ptr->coins_per_cred[0] = IORAM_READ(9);
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ptr->creds_per_coin[0] = IORAM_READ(10);
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ptr->coins_per_cred[1] = IORAM_READ(11);
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ptr->creds_per_coin[1] = IORAM_READ(12);
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break;
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case 4:
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handle_coins(chip,0);
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break;
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case 7: // bootup check (liblrabl only)
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{
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IORAM_WRITE(2, 0xe);
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IORAM_WRITE(7, 0x6);
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}
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break;
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case 8: // bootup check
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{
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int i, sum;
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sum = 0;
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for (i = 9; i < 16; i++)
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sum += IORAM_READ(i);
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IORAM_WRITE(0, sum >> 4);
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IORAM_WRITE(1, sum & 0xf);
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}
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break;
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case 9: // read dip switches and inputs
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ptr->out_0_cb((UINT8)0, 0 & 0x0f); // set pin 13 = 0
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IORAM_WRITE(0, ~ptr->in_0_cb(0 & 0x0f)); // pins 38-41, pin 13 = 0
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IORAM_WRITE(2, ~ptr->in_1_cb(0 & 0x0f)); // pins 22-25, pin 13 = 0
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IORAM_WRITE(4, ~ptr->in_2_cb(0 & 0x0f)); // pins 26-29, pin 13 = 0
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IORAM_WRITE(6, ~ptr->in_3_cb(0 & 0x0f)); // pins 30-33, pin 13 = 0
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ptr->out_0_cb((UINT8)0, 1 & 0x0f); // set pin 13 = 1
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IORAM_WRITE(1, ~ptr->in_0_cb(0 & 0x0f)); // pins 38-41, pin 13 = 1
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IORAM_WRITE(3, ~ptr->in_1_cb(0 & 0x0f)); // pins 22-25, pin 13 = 1
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IORAM_WRITE(5, ~ptr->in_2_cb(0 & 0x0f)); // pins 26-29, pin 13 = 1
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IORAM_WRITE(7, ~ptr->in_3_cb(0 & 0x0f)); // pins 30-33, pin 13 = 1
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break;
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}
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}
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void namco59xx_customio_run(INT32 chip)
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{
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ChipData *ptr = &Chips[chip];
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switch (IORAM_READ(8))
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{
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case 3: // pacnpal chip #1: read dip switches and inputs
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IORAM_WRITE(4, ~ptr->in_0_cb(0 & 0x0f)); // pins 38-41, pin 13 = 0 ?
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IORAM_WRITE(5, ~ptr->in_2_cb(0 & 0x0f)); // pins 26-29 ?
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IORAM_WRITE(6, ~ptr->in_1_cb(0 & 0x0f)); // pins 22-25 ?
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IORAM_WRITE(7, ~ptr->in_3_cb(0 & 0x0f)); // pins 30-33
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break;
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}
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}
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void namco58xx_customio_run(INT32 chip)
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{
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ChipData *ptr = &Chips[chip];
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switch (IORAM_READ(8))
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{
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case 1: // read switch inputs
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IORAM_WRITE(4, ~ptr->in_0_cb(0 & 0x0f)); // pins 38-41
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IORAM_WRITE(5, ~ptr->in_1_cb(0 & 0x0f)); // pins 22-25
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IORAM_WRITE(6, ~ptr->in_2_cb(0 & 0x0f)); // pins 26-29
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IORAM_WRITE(7, ~ptr->in_3_cb(0 & 0x0f)); // pins 30-33
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ptr->out_0_cb((UINT8)0, IORAM_READ(9)); // output to pins 13-16 (toypop)
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ptr->out_1_cb((UINT8)0, IORAM_READ(10)); // output to pins 17-20 (toypop)
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break;
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case 2: // initialize coinage settings
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ptr->coins_per_cred[0] = IORAM_READ(9);
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ptr->creds_per_coin[0] = IORAM_READ(10);
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ptr->coins_per_cred[1] = IORAM_READ(11);
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ptr->creds_per_coin[1] = IORAM_READ(12);
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break;
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case 3: // process coin and start inputs, read switch inputs
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handle_coins(chip,2);
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break;
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case 4: // read dip switches and inputs
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ptr->out_0_cb((UINT8)0, 0 & 0x0f); // set pin 13 = 0
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IORAM_WRITE(0, ~ptr->in_0_cb(0 & 0x0f)); // pins 38-41, pin 13 = 0
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IORAM_WRITE(2, ~ptr->in_1_cb(0 & 0x0f)); // pins 22-25, pin 13 = 0
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IORAM_WRITE(4, ~ptr->in_2_cb(0 & 0x0f)); // pins 26-29, pin 13 = 0
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IORAM_WRITE(6, ~ptr->in_3_cb(0 & 0x0f)); // pins 30-33, pin 13 = 0
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ptr->out_0_cb((UINT8)0, 1 & 0x0f); // set pin 13 = 1
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IORAM_WRITE(1, ~ptr->in_0_cb(0 & 0x0f)); // pins 38-41, pin 13 = 1
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IORAM_WRITE(3, ~ptr->in_1_cb(0 & 0x0f)); // pins 22-25, pin 13 = 1
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IORAM_WRITE(5, ~ptr->in_2_cb(0 & 0x0f)); // pins 26-29, pin 13 = 1
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IORAM_WRITE(7, ~ptr->in_3_cb(0 & 0x0f)); // pins 30-33, pin 13 = 1
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break;
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case 5: // bootup check
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{
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int i, n, rng, seed;
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#define NEXT(n) ((((n) & 1) ? (n) ^ 0x90 : (n)) >> 1)
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/* initialize the LFSR depending on the first two arguments */
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n = (IORAM_READ(9) * 16 + IORAM_READ(10)) & 0x7f;
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seed = 0x22;
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for (i = 0; i < n; i++)
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seed = NEXT(seed);
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/* calculate the answer */
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for (i = 1; i < 8; i++)
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{
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n = 0;
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rng = seed;
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if (rng & 1) { n ^= ~IORAM_READ(11); }
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rng = NEXT(rng);
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seed = rng; // save state for next loop
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if (rng & 1) { n ^= ~IORAM_READ(10); }
|
||||
rng = NEXT(rng);
|
||||
if (rng & 1) { n ^= ~IORAM_READ(9); }
|
||||
rng = NEXT(rng);
|
||||
if (rng & 1) { n ^= ~IORAM_READ(15); }
|
||||
rng = NEXT(rng);
|
||||
if (rng & 1) { n ^= ~IORAM_READ(14); }
|
||||
rng = NEXT(rng);
|
||||
if (rng & 1) { n ^= ~IORAM_READ(13); }
|
||||
rng = NEXT(rng);
|
||||
if (rng & 1) { n ^= ~IORAM_READ(12); }
|
||||
|
||||
IORAM_WRITE(i, ~n);
|
||||
}
|
||||
IORAM_WRITE(0, 0x0);
|
||||
/* kludge for gaplus */
|
||||
if (IORAM_READ(9) == 0xf) IORAM_WRITE(0, 0xf);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
UINT8 namcoio_read(INT32 chip, UINT8 offset)
|
||||
{
|
||||
ChipData *ptr = &Chips[chip];
|
||||
|
||||
// RAM is 4-bit wide; Pac & Pal requires the | 0xf0 otherwise Easter egg doesn't work
|
||||
offset &= 0x3f;
|
||||
|
||||
return 0xf0 | ptr->ram[offset];
|
||||
}
|
||||
|
||||
void namcoio_write(INT32 chip, UINT8 offset, UINT8 data)
|
||||
{
|
||||
ChipData *ptr = &Chips[chip];
|
||||
|
||||
offset &= 0x3f;
|
||||
data &= 0x0f; // RAM is 4-bit wide
|
||||
|
||||
ptr->ram[offset] = data;
|
||||
}
|
||||
|
||||
UINT8 namcoio_read_reset_line(INT32 chip)
|
||||
{
|
||||
ChipData *ptr = &Chips[chip];
|
||||
|
||||
return ptr->reset;
|
||||
}
|
||||
|
||||
INT32 namcoio_scan(INT32 chip)
|
||||
{
|
||||
ChipData *ptr = &Chips[chip];
|
||||
|
||||
SCAN_VAR(ptr->ram);
|
||||
SCAN_VAR(ptr->reset);
|
||||
SCAN_VAR(ptr->lastcoins);
|
||||
SCAN_VAR(ptr->lastbuttons);
|
||||
SCAN_VAR(ptr->coins);
|
||||
SCAN_VAR(ptr->credits);
|
||||
SCAN_VAR(ptr->coins_per_cred);
|
||||
SCAN_VAR(ptr->creds_per_coin);
|
||||
SCAN_VAR(ptr->in_count);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
|
||||
void namcoio_init(INT32 chip, UINT8 (*in0)(UINT8), UINT8 (*in1)(UINT8), UINT8 (*in2)(UINT8), UINT8 (*in3)(UINT8), void (*out0)(UINT8, UINT8), void (*out1)(UINT8, UINT8));
|
||||
void namcoio_reset(INT32 chip);
|
||||
INT32 namcoio_scan(INT32 chip);
|
||||
|
||||
void namco_customio_run(INT32 chip);
|
||||
void namco59xx_customio_run(INT32 chip);
|
||||
void namco58xx_customio_run(INT32 chip);
|
||||
|
||||
UINT8 namcoio_read(INT32 chip, UINT8 offset);
|
||||
void namcoio_write(INT32 chip, UINT8 offset, UINT8 data);
|
||||
UINT8 namcoio_read_reset_line(INT32 chip);
|
||||
void namcoio_set_reset_line(INT32 chip, INT32 state);
|
||||
Loading…
Reference in New Issue