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TLCS-90 CPU: Fixed TRUN bit masking (timers start/stop) [Rainer Keuchel]

This commit is contained in:
dinkc64 2015-05-17 20:47:07 +00:00
parent d9400b3f9a
commit c68b09d073
1 changed files with 13 additions and 12 deletions
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23
src/cpu/tlcs90/tlcs90.cpp
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@ -2086,9 +2086,11 @@ INT32 tlcs90Reset()
P0/D0-D7 P1/A0-A7 P2/A8-A15 P6 P7 = INPUT P0/D0-D7 P1/A0-A7 P2/A8-A15 P6 P7 = INPUT
P35/~RD P36/~WR CLK = 1 (ALWAYS OUTPUTS) P35/~RD P36/~WR CLK = 1 (ALWAYS OUTPUTS)
P4/A16-A19 P83 = 0 P4/A16-A19 P83 = 0
dedicated input ports and registers remain unchanged, dedicated input ports and CPU registers remain unchanged,
but PC IFF BX BY = 0, A undefined but PC IFF BX BY = 0, A undefined
*/ */
memset(&cpustate->internal_registers, 0, sizeof(cpustate->internal_registers));
return 0; return 0;
} }
@ -2489,8 +2491,9 @@ void t90_timer_callback(INT32 param)
INT32 mode, timer_fired; INT32 mode, timer_fired;
INT32 i = param; INT32 i = param;
INT32 mask = 0x20 | (1 << i);
if ( (cpustate->internal_registers[ T90_TRUN - T90_IOBASE ] & (1 << i)) == 0 ) if ( (cpustate->internal_registers[ T90_TRUN - T90_IOBASE ] & mask) != mask )
return; return;
timer_fired = 0; timer_fired = 0;
@ -2585,19 +2588,22 @@ void t90_internal_registers_w(UINT16 offset, UINT8 data)
case T90_TRUN: case T90_TRUN:
{ {
int i; int i;
UINT8 mask;
// Timers 0-3 // Timers 0-3
for (i = 0; i < 4; i++) for (i = 0; i < 4; i++)
{ {
if ( (old ^ data) & (0x20 | (1 << i)) ) // if timer bit or prescaler bit changed mask = 0x20 | (1 << i);
if ( (old ^ data) & mask ) // if timer bit or prescaler bit changed
{ {
if ( (data & (1 << i)) && (data & 0x20) ) t90_start_timer(cpustate, i); if ( (data & mask) == mask ) t90_start_timer(cpustate, i);
else t90_stop_timer(cpustate, i); else t90_stop_timer(cpustate, i);
} }
} }
// Timer 4 // Timer 4
if ( (old ^ data) & (0x20 | 0x10) ) mask = 0x20 | 0x10;
if ( (old ^ data) & mask )
{ {
if ( data == (0x20 | 0x10) ) t90_start_timer4(cpustate); if ( (data & mask) == mask ) t90_start_timer4(cpustate);
else t90_stop_timer4(cpustate); else t90_stop_timer4(cpustate);
} }
break; break;
@ -2745,11 +2751,6 @@ INT32 tlcs90_init(INT32 clock)
cpustate->timer_period = clock / 1000000; cpustate->timer_period = clock / 1000000;
// Reset registers to their initial values
// IX = IY = 0xffff;
// F = ZF;
// Timers // Timers
for (i = 0; i < 4; i++) for (i = 0; i < 4; i++)
cpustate->timer_cb[i] = t90_timer_callback; cpustate->timer_cb[i] = t90_timer_callback;