TLCS-90 CPU: Fixed TRUN bit masking (timers start/stop) [Rainer Keuchel]
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@ -2086,9 +2086,11 @@ INT32 tlcs90Reset()
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P0/D0-D7 P1/A0-A7 P2/A8-A15 P6 P7 = INPUT
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P35/~RD P36/~WR CLK = 1 (ALWAYS OUTPUTS)
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P4/A16-A19 P83 = 0
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dedicated input ports and registers remain unchanged,
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dedicated input ports and CPU registers remain unchanged,
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but PC IFF BX BY = 0, A undefined
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*/
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memset(&cpustate->internal_registers, 0, sizeof(cpustate->internal_registers));
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return 0;
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}
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@ -2489,11 +2491,12 @@ void t90_timer_callback(INT32 param)
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INT32 mode, timer_fired;
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INT32 i = param;
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INT32 mask = 0x20 | (1 << i);
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if ( (cpustate->internal_registers[ T90_TRUN - T90_IOBASE ] & (1 << i)) == 0 )
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if ( (cpustate->internal_registers[ T90_TRUN - T90_IOBASE ] & mask) != mask )
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return;
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timer_fired = 0;
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timer_fired = 0;
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mode = (cpustate->internal_registers[ T90_TMOD - T90_IOBASE ] >> ((i & ~1) + 2)) & 0x03;
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// Match
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@ -2585,19 +2588,22 @@ void t90_internal_registers_w(UINT16 offset, UINT8 data)
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case T90_TRUN:
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{
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int i;
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UINT8 mask;
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// Timers 0-3
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for (i = 0; i < 4; i++)
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{
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if ( (old ^ data) & (0x20 | (1 << i)) ) // if timer bit or prescaler bit changed
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mask = 0x20 | (1 << i);
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if ( (old ^ data) & mask ) // if timer bit or prescaler bit changed
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{
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if ( (data & (1 << i)) && (data & 0x20) ) t90_start_timer(cpustate, i);
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if ( (data & mask) == mask ) t90_start_timer(cpustate, i);
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else t90_stop_timer(cpustate, i);
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}
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}
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// Timer 4
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if ( (old ^ data) & (0x20 | 0x10) )
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mask = 0x20 | 0x10;
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if ( (old ^ data) & mask )
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{
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if ( data == (0x20 | 0x10) ) t90_start_timer4(cpustate);
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if ( (data & mask) == mask ) t90_start_timer4(cpustate);
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else t90_stop_timer4(cpustate);
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}
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break;
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@ -2745,11 +2751,6 @@ INT32 tlcs90_init(INT32 clock)
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cpustate->timer_period = clock / 1000000;
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// Reset registers to their initial values
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// IX = IY = 0xffff;
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// F = ZF;
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// Timers
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for (i = 0; i < 4; i++)
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cpustate->timer_cb[i] = t90_timer_callback;
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