From 56fa5ab559e0f78a60222513cd5f7db87ed64433 Mon Sep 17 00:00:00 2001 From: dinkc64 Date: Wed, 4 May 2022 23:36:00 -0400 Subject: [PATCH] add new WIP (work-in-progress) / unfinished driver --- makefile.burn_rules | 8 +- src/burn/burn.h | 1 + src/burn/devices/epic12.cpp | 935 ++++++ src/burn/devices/epic12.h | 12 + src/burn/devices/epic12_blit0.inc | 556 ++++ src/burn/devices/epic12_blit1.inc | 556 ++++ src/burn/devices/epic12_blit2.inc | 556 ++++ src/burn/devices/epic12_blit3.inc | 556 ++++ src/burn/devices/epic12_blit4.inc | 556 ++++ src/burn/devices/epic12_blit5.inc | 556 ++++ src/burn/devices/epic12_blit6.inc | 556 ++++ src/burn/devices/epic12_blit7.inc | 556 ++++ src/burn/devices/epic12_blit8.inc | 40 + src/burn/devices/epic12in.inc | 168 + src/burn/devices/epic12pixel.inc | 193 ++ src/burn/devices/thready.h | 223 ++ src/burn/drv/cave/d_cv1k.cpp | 1322 ++++++++ src/burner/statec.cpp | 4 +- src/cpu/sh4/sh3comn.h | 100 + src/cpu/sh4/sh3comn.inc | 732 ++++ src/cpu/sh4/sh4.cpp | 5138 +++++++++++++++++++++++++++++ src/cpu/sh4/sh4.h | 817 +++++ src/cpu/sh4/sh4_intf.h | 71 + src/cpu/sh4/sh4comn.h | 172 + src/cpu/sh4/sh4comn.inc | 1285 ++++++++ src/cpu/sh4/sh4dmac.h | 63 + src/cpu/sh4/sh4dmac.inc | 704 ++++ src/cpu/sh4/sh4regs.h | 181 + src/cpu/sh4/sh4tmu.h | 1 + src/cpu/sh4/sh4tmu.inc | 323 ++ 30 files changed, 16935 insertions(+), 6 deletions(-) create mode 100644 src/burn/devices/epic12.cpp create mode 100644 src/burn/devices/epic12.h create mode 100644 src/burn/devices/epic12_blit0.inc create mode 100644 src/burn/devices/epic12_blit1.inc create mode 100644 src/burn/devices/epic12_blit2.inc create mode 100644 src/burn/devices/epic12_blit3.inc create mode 100644 src/burn/devices/epic12_blit4.inc create mode 100644 src/burn/devices/epic12_blit5.inc create mode 100644 src/burn/devices/epic12_blit6.inc create mode 100644 src/burn/devices/epic12_blit7.inc create mode 100644 src/burn/devices/epic12_blit8.inc create mode 100644 src/burn/devices/epic12in.inc create mode 100644 src/burn/devices/epic12pixel.inc create mode 100644 src/burn/devices/thready.h create mode 100644 src/burn/drv/cave/d_cv1k.cpp create mode 100644 src/cpu/sh4/sh3comn.h create mode 100644 src/cpu/sh4/sh3comn.inc create mode 100644 src/cpu/sh4/sh4.cpp create mode 100644 src/cpu/sh4/sh4.h create mode 100644 src/cpu/sh4/sh4_intf.h create mode 100644 src/cpu/sh4/sh4comn.h create mode 100644 src/cpu/sh4/sh4comn.inc create mode 100644 src/cpu/sh4/sh4dmac.h create mode 100644 src/cpu/sh4/sh4dmac.inc create mode 100644 src/cpu/sh4/sh4regs.h create mode 100644 src/cpu/sh4/sh4tmu.h create mode 100644 src/cpu/sh4/sh4tmu.inc diff --git a/makefile.burn_rules b/makefile.burn_rules index 9a0b27566..842da735c 100644 --- a/makefile.burn_rules +++ b/makefile.burn_rules @@ -2,13 +2,13 @@ alldir = burn burn/devices burn/snd burn/drv burn/drv/atari burn/drv/capcom bur burn/drv/galaxian burn/drv/irem burn/drv/konami burn/drv/megadrive burn/drv/midway burn/drv/pce burn/drv/pst90s burn/drv/pre90s burn/drv/neogeo burn/drv/nes \ burn/drv/pgm burn/drv/psikyo burn/drv/sega burn/drv/sg1000 burn/drv/sms burn/drv/msx burn/drv/spectrum burn/drv/taito \ burn/drv/toaplan cpu cpu/a68k cpu/arm cpu/arm7 cpu/e132xs cpu/f8 cpu/h6280 cpu/hd6309 cpu/i386 cpu/i8039 cpu/i8x41 cpu/i8051 cpu/adsp2100 cpu/konami cpu/m377 cpu/mips3 cpu/m68k \ - cpu/m6502 cpu/m6800 cpu/m6805 cpu/m6809 cpu/nec cpu/pic16c5x cpu/s2650 cpu/tlcs90 cpu/tlcs900 cpu/sh2 cpu/tms32010 cpu/tms34 cpu/upd7725 cpu/upd7810 \ + cpu/m6502 cpu/m6800 cpu/m6805 cpu/m6809 cpu/nec cpu/pic16c5x cpu/s2650 cpu/tlcs90 cpu/tlcs900 cpu/sh2 cpu/sh4 cpu/tms32010 cpu/tms34 cpu/upd7725 cpu/upd7810 \ cpu/v60 cpu/z80 cpu/z180 drvsrc = d_akkaarrh.o d_arcadecl.o d_atarig1.o d_badlands.o d_batman.o d_blstroid.o d_eprom.o d_gauntlet.o d_klax.o d_missile.o d_offtwall.o d_rampart.o \ d_relief.o d_shuuz.o d_skullxbo.o d_thunderj.o d_toobin.o d_vindictr.o d_xybots.o \ \ - d_dodonpachi.o d_donpachi.o d_esprade.o d_feversos.o d_gaia.o d_guwange.o d_hotdogst.o d_korokoro.o d_mazinger.o d_metmqstr.o d_pwrinst2.o \ + d_cv1k.o d_dodonpachi.o d_donpachi.o d_esprade.o d_feversos.o d_gaia.o d_guwange.o d_hotdogst.o d_korokoro.o d_mazinger.o d_metmqstr.o d_pwrinst2.o \ d_sailormn.o d_tjumpman.o d_uopoko.o \ \ d_cps1.o \ @@ -101,7 +101,7 @@ drvsrc = d_akkaarrh.o d_arcadecl.o d_atarig1.o d_badlands.o d_batman.o d_blstro depobj = burn.o burn_bitmap.o burn_gun.o burn_led.o burn_shift.o burn_memory.o burn_pal.o burn_sound.o burn_sound_c.o cheat.o debug_track.o hiscore.o \ load.o tilemap_generic.o tiles_generic.o timer.o vector.o \ \ - 6821pia.o 8255ppi.o 8257dma.o c169.o atariic.o atarijsa.o atarimo.o atarirle.o atarivad.o avgdvg.o bsmt2000.o decobsmt.o ds2404.o earom.o eeprom.o gaelco_crypt.o i4x00.o intelfsh.o \ + 6821pia.o 8255ppi.o 8257dma.o c169.o atariic.o atarijsa.o atarimo.o atarirle.o atarivad.o avgdvg.o bsmt2000.o decobsmt.o ds2404.o earom.o eeprom.o epic12.o gaelco_crypt.o i4x00.o intelfsh.o \ joyprocess.o nb1414m4.o nb1414m4_8bit.o nmk004.o nmk112.o k1ge.o kaneko_tmap.o mathbox.o mb87078.o mermaid.o midcsd.o midsat.o midsg.o midssio.o midtcs.o \ namco_c45.o namcoio.o pandora.o poly.o qs1000.o resnet.o rtc9701.o seibucop.o seibusnd.o serflash.o sknsspr.o slapstic.o st0020.o t5182.o timekpr.o tlc34076.o tms34061.o v3021.o vdc.o \ tms9928a.o watchdog.o x2212.o \ @@ -116,7 +116,7 @@ depobj = burn.o burn_bitmap.o burn_gun.o burn_led.o burn_shift.o burn_memory.o m68000_intf.o mips3_intf.o nec_intf.o pic16c5x_intf.o s2650_intf.o tlcs90_intf.o tms34010.o tms34_intf.o z80_intf.o \ z180_intf.o \ \ - arm.o arm7.o e132xs.o h6280.o hd6309.o i386.o i8039.o m37710.o mcs48.o mcs51.o konami.o m6502.o m6800.o m6805.o m6809.o nec.o pic16c5x.o s2650.o sh2.o tms32010.o tlcs90.o tlcs900.o \ + arm.o arm7.o e132xs.o h6280.o hd6309.o i386.o i8039.o m37710.o mcs48.o mcs51.o konami.o m6502.o m6800.o m6805.o m6809.o nec.o pic16c5x.o s2650.o sh2.o sh4.o tms32010.o tlcs90.o tlcs900.o \ upd7725.o upd7810.o v25.o v60.o z80.o z80daisy.o z80ctc.o z80pio.o z180.o \ \ cop0.o cop1.o mips3.o \ diff --git a/src/burn/burn.h b/src/burn/burn.h index afba3e5ad..8133f07be 100644 --- a/src/burn/burn.h +++ b/src/burn/burn.h @@ -550,6 +550,7 @@ INT32 GetIpsesMaxLen(char* rom_name); #define HARDWARE_CAVE_68K_Z80 (HARDWARE_PREFIX_CAVE | 0x0001) #define HARDWARE_CAVE_M6295 (0x0002) #define HARDWARE_CAVE_YM2151 (0x0004) +#define HARDWARE_CAVE_CV1000 (HARDWARE_PREFIX_CAVE | 0x00010000) #define HARDWARE_IGS_PGM (HARDWARE_PREFIX_IGS_PGM) #define HARDWARE_IGS_USE_ARM_CPU (0x0001) diff --git a/src/burn/devices/epic12.cpp b/src/burn/devices/epic12.cpp new file mode 100644 index 000000000..9e589efdf --- /dev/null +++ b/src/burn/devices/epic12.cpp @@ -0,0 +1,935 @@ +/* emulation of Altera Cyclone EPIC12 FPGA programmed as a blitter */ + +#include "burnint.h" +#include "tiles_generic.h" +#include "sh4_intf.h" +#include "thready.h" + +struct rectangle +{ + // mame-compatible rectangle object + INT32 min_x; + INT32 max_x; + INT32 min_y; + INT32 max_y; + + rectangle(INT32 minx = 0, INT32 maxx = 0, INT32 miny = 0, INT32 maxy = 0) { + set(minx, maxx, miny, maxy); + } + + void set(INT32 minx, INT32 maxx, INT32 miny, INT32 maxy) { + min_x = minx; max_x = maxx; + min_y = miny; max_y = maxy; + } + + rectangle operator &= (const rectangle &other) { + if (min_x < other.min_x) min_x = other.min_x; + if (min_y < other.min_y) min_y = other.min_y; + if (max_x > other.max_x) max_x = other.max_x; + if (max_y > other.max_y) max_y = other.max_y; + if (min_y > max_y) min_y = max_y; + if (min_x > max_x) min_x = max_x; + return *this; + } +}; + +static UINT16* m_ram16; +static UINT32 m_gfx_addr; +static UINT32 m_gfx_scroll_0_x, m_gfx_scroll_0_y; +static UINT32 m_gfx_scroll_1_x, m_gfx_scroll_1_y; + +static int m_gfx_size; +static UINT32 *m_bitmaps; +static rectangle m_clip; + +static UINT64 epic12_device_blit_delay; +static int m_blitter_busy; + +static UINT16* m_use_ram; +static int m_main_ramsize; // type D has double the main ram +static int m_main_rammask; + +static int m_delay_scale; +static int m_burn_cycles; + +static UINT8 epic12_device_colrtable[0x20][0x40]; +static UINT8 epic12_device_colrtable_rev[0x20][0x40]; +static UINT8 epic12_device_colrtable_add[0x20][0x20]; + +#include "epic12.h" + +struct _clr_t +{ + UINT8 b,g,r,t; +}; + +typedef struct _clr_t clr_t; + +union colour_t +{ + clr_t trgb; + UINT32 u32; +}; + +typedef const void (*epic12_device_blitfunction)( + const rectangle *, + UINT32 *, /* gfx */ + int , /* src_x */ + int , /* src_y */ + const int , /* dst_x_start */ + const int , /* dst_y_start */ + int , /* dimx */ + int , /* dimy */ + const int , /* flipy */ + const UINT8 , /* s_alpha */ + const UINT8 , /* d_alpha */ + //int , /* tint */ + const clr_t * ); + +#define BLIT_PARAMS const rectangle *clip, UINT32 *gfx, int src_x, int src_y, const int dst_x_start, const int dst_y_start, int dimx, int dimy, const int flipy, const UINT8 s_alpha, const UINT8 d_alpha, const clr_t *tint_clr + + static inline void pen_to_clr(UINT32 pen, clr_t *clr) + { + // --t- ---- rrrr r--- gggg g--- bbbb b--- format + clr->r = (pen >> (16+3));// & 0x1f; + clr->g = (pen >> (8+3));// & 0x1f; + clr->b = (pen >> 3);// & 0x1f; + + // --t- ---- ---r rrrr ---g gggg ---b bbbb format + // clr->r = (pen >> 16) & 0x1f; + // clr->g = (pen >> 8) & 0x1f; + // clr->b = (pen >> 0) & 0x1f; + + } + + + // convert separate r,g,b biases (0..80..ff) to clr_t (-1f..0..1f) + static inline void tint_to_clr(UINT8 r, UINT8 g, UINT8 b, clr_t *clr) + { + clr->r = r>>2; + clr->g = g>>2; + clr->b = b>>2; + } + + // clr_t to r5g5b5 + static inline UINT32 clr_to_pen(const clr_t *clr) + { + // --t- ---- rrrr r--- gggg g--- bbbb b--- format + return (clr->r << (16+3)) | (clr->g << (8+3)) | (clr->b << 3); + + // --t- ---- ---r rrrr ---g gggg ---b bbbb format + // return (clr->r << (16)) | (clr->g << (8)) | (clr->b); + } + + + static inline void clr_add_with_clr_mul_fixed(clr_t *clr, const clr_t *clr0, const UINT8 mulfixed_val, const clr_t *mulfixed_clr0) + { + clr->r = epic12_device_colrtable_add[clr0->r][epic12_device_colrtable[(mulfixed_clr0->r)][mulfixed_val]]; + clr->g = epic12_device_colrtable_add[clr0->g][epic12_device_colrtable[(mulfixed_clr0->g)][mulfixed_val]]; + clr->b = epic12_device_colrtable_add[clr0->b][epic12_device_colrtable[(mulfixed_clr0->b)][mulfixed_val]]; + } + + static inline void clr_add_with_clr_mul_3param(clr_t *clr, const clr_t *clr0, const clr_t *clr1, const clr_t *clr2) + { + clr->r = epic12_device_colrtable_add[clr0->r][epic12_device_colrtable[(clr2->r)][(clr1->r)]]; + clr->g = epic12_device_colrtable_add[clr0->g][epic12_device_colrtable[(clr2->g)][(clr1->g)]]; + clr->b = epic12_device_colrtable_add[clr0->b][epic12_device_colrtable[(clr2->b)][(clr1->b)]]; + } + + static inline void clr_add_with_clr_square(clr_t *clr, const clr_t *clr0, const clr_t *clr1) + { + clr->r = epic12_device_colrtable_add[clr0->r][epic12_device_colrtable[(clr1->r)][(clr1->r)]]; + clr->g = epic12_device_colrtable_add[clr0->r][epic12_device_colrtable[(clr1->g)][(clr1->g)]]; + clr->b = epic12_device_colrtable_add[clr0->r][epic12_device_colrtable[(clr1->b)][(clr1->b)]]; + } + + static inline void clr_add_with_clr_mul_fixed_rev(clr_t *clr, const clr_t *clr0, const UINT8 val, const clr_t *clr1) + { + clr->r = epic12_device_colrtable_add[clr0->r][epic12_device_colrtable_rev[val][(clr1->r)]]; + clr->g = epic12_device_colrtable_add[clr0->g][epic12_device_colrtable_rev[val][(clr1->g)]]; + clr->b = epic12_device_colrtable_add[clr0->b][epic12_device_colrtable_rev[val][(clr1->b)]]; + } + + static inline void clr_add_with_clr_mul_rev_3param(clr_t *clr, const clr_t *clr0, const clr_t *clr1, const clr_t *clr2) + { + clr->r = epic12_device_colrtable_add[clr0->r][epic12_device_colrtable_rev[(clr2->r)][(clr1->r)]]; + clr->g = epic12_device_colrtable_add[clr0->g][epic12_device_colrtable_rev[(clr2->g)][(clr1->g)]]; + clr->b = epic12_device_colrtable_add[clr0->b][epic12_device_colrtable_rev[(clr2->b)][(clr1->b)]]; + } + + static inline void clr_add_with_clr_mul_rev_square(clr_t *clr, const clr_t *clr0, const clr_t *clr1) + { + clr->r = epic12_device_colrtable_add[clr0->r][epic12_device_colrtable_rev[(clr1->r)][(clr1->r)]]; + clr->g = epic12_device_colrtable_add[clr0->g][epic12_device_colrtable_rev[(clr1->g)][(clr1->g)]]; + clr->b = epic12_device_colrtable_add[clr0->b][epic12_device_colrtable_rev[(clr1->b)][(clr1->b)]]; + } + + + static inline void clr_add(clr_t *clr, const clr_t *clr0, const clr_t *clr1) + { + /* + clr->r = clr0->r + clr1->r; + clr->g = clr0->g + clr1->g; + clr->b = clr0->b + clr1->b; + */ + // use pre-clamped lookup table + clr->r = epic12_device_colrtable_add[clr0->r][clr1->r]; + clr->g = epic12_device_colrtable_add[clr0->g][clr1->g]; + clr->b = epic12_device_colrtable_add[clr0->b][clr1->b]; + + } + + + static inline void clr_mul(clr_t *clr0, const clr_t *clr1) + { + clr0->r = epic12_device_colrtable[(clr0->r)][(clr1->r)]; + clr0->g = epic12_device_colrtable[(clr0->g)][(clr1->g)]; + clr0->b = epic12_device_colrtable[(clr0->b)][(clr1->b)]; + } + + static inline void clr_square(clr_t *clr0, const clr_t *clr1) + { + clr0->r = epic12_device_colrtable[(clr1->r)][(clr1->r)]; + clr0->g = epic12_device_colrtable[(clr1->g)][(clr1->g)]; + clr0->b = epic12_device_colrtable[(clr1->b)][(clr1->b)]; + } + + static inline void clr_mul_3param(clr_t *clr0, const clr_t *clr1, const clr_t *clr2) + { + clr0->r = epic12_device_colrtable[(clr2->r)][(clr1->r)]; + clr0->g = epic12_device_colrtable[(clr2->g)][(clr1->g)]; + clr0->b = epic12_device_colrtable[(clr2->b)][(clr1->b)]; + } + + static inline void clr_mul_rev(clr_t *clr0, const clr_t *clr1) + { + clr0->r = epic12_device_colrtable_rev[(clr0->r)][(clr1->r)]; + clr0->g = epic12_device_colrtable_rev[(clr0->g)][(clr1->g)]; + clr0->b = epic12_device_colrtable_rev[(clr0->b)][(clr1->b)]; + } + + static inline void clr_mul_rev_square(clr_t *clr0, const clr_t *clr1) + { + clr0->r = epic12_device_colrtable_rev[(clr1->r)][(clr1->r)]; + clr0->g = epic12_device_colrtable_rev[(clr1->g)][(clr1->g)]; + clr0->b = epic12_device_colrtable_rev[(clr1->b)][(clr1->b)]; + } + + + static inline void clr_mul_rev_3param(clr_t *clr0, const clr_t *clr1, const clr_t *clr2) + { + clr0->r = epic12_device_colrtable_rev[(clr2->r)][(clr1->r)]; + clr0->g = epic12_device_colrtable_rev[(clr2->g)][(clr1->g)]; + clr0->b = epic12_device_colrtable_rev[(clr2->b)][(clr1->b)]; + } + + static inline void clr_mul_fixed(clr_t *clr, const UINT8 val, const clr_t *clr0) + { + clr->r = epic12_device_colrtable[val][(clr0->r)]; + clr->g = epic12_device_colrtable[val][(clr0->g)]; + clr->b = epic12_device_colrtable[val][(clr0->b)]; + } + + static inline void clr_mul_fixed_rev(clr_t *clr, const UINT8 val, const clr_t *clr0) + { + clr->r = epic12_device_colrtable_rev[val][(clr0->r)]; + clr->g = epic12_device_colrtable_rev[val][(clr0->g)]; + clr->b = epic12_device_colrtable_rev[val][(clr0->b)]; + } + + static inline void clr_copy(clr_t *clr, const clr_t *clr0) + { + clr->r = clr0->r; + clr->g = clr0->g; + clr->b = clr0->b; + } + + + + // (1|s|d) * s_factor * s + (1|s|d) * d_factor * d + // 0: +alpha + // 1: +source + // 2: +dest + // 3: * + // 4: -alpha + // 5: -source + // 6: -dest + // 7: * + +#include "epic12_blit0.inc" +#include "epic12_blit1.inc" +#include "epic12_blit2.inc" +#include "epic12_blit3.inc" +#include "epic12_blit4.inc" +#include "epic12_blit5.inc" +#include "epic12_blit6.inc" +#include "epic12_blit7.inc" +#include "epic12_blit8.inc" + +static UINT8 *dips; // pointer to cv1k's dips + +static void blitter_delay_callback(int) +{ + m_blitter_busy = 0; + //bprintf(0, _T("cyc @ blitdelay callback: %d\n"), Sh3TotalCycles()); +} + +static void gfx_exec(); // forward + +static void run_blitter_cb() +{ + epic12_device_blit_delay = 0; + gfx_exec(); +} + +void epic12_exit() +{ + BurnFree(m_bitmaps); + + thready.exit(); +} + +void epic12_init(INT32 ram_size, UINT16 *ram, UINT8 *dippy) +{ + m_main_ramsize = ram_size; + m_main_rammask = ram_size - 1; + + m_use_ram = m_ram16 = ram; + + dips = dippy; + + m_gfx_size = 0x2000 * 0x1000; + m_bitmaps = (UINT32*)BurnMalloc (0x2000 * 0x1000 * 4); + + m_clip.set(0, 0x2000-1, 0, 0x1000-1); + + m_delay_scale = 50; + m_blitter_busy = 0; + m_gfx_addr = 0; + m_gfx_scroll_0_x = 0; + m_gfx_scroll_0_y = 0; + m_gfx_scroll_1_x = 0; + m_gfx_scroll_1_y = 0; + epic12_device_blit_delay = 0; + + thready.init(run_blitter_cb); + + sh4_set_cave_blitter_delay_func(blitter_delay_callback); +} + +void epic12_set_blitterthreading(INT32 value) +{ + thready.set_threading(value); +} + +void epic12_set_blitterdelay(INT32 delay, INT32 burn_cycles) +{ + m_delay_scale = delay; + m_burn_cycles = burn_cycles; +} + +void epic12_reset() +{ + // cache table to avoid divides in blit code, also pre-clamped + int x,y; + for (y=0;y<0x40;y++) + { + for (x=0;x<0x20;x++) + { + epic12_device_colrtable[x][y] = (x*y) / 0x1f; + if (epic12_device_colrtable[x][y]>0x1f) epic12_device_colrtable[x][y] = 0x1f; + + epic12_device_colrtable_rev[x^0x1f][y] = (x*y) / 0x1f; + if (epic12_device_colrtable_rev[x^0x1f][y]>0x1f) epic12_device_colrtable_rev[x^0x1f][y] = 0x1f; + } + } + + // preclamped add table + for (y=0;y<0x20;y++) + { + for (x=0;x<0x20;x++) + { + epic12_device_colrtable_add[x][y] = (x+y); + if (epic12_device_colrtable_add[x][y]>0x1f) epic12_device_colrtable_add[x][y] = 0x1f; + } + } + + m_blitter_busy = 0; + m_gfx_addr = 0; + m_gfx_scroll_0_x = 0; + m_gfx_scroll_0_y = 0; + m_gfx_scroll_1_x = 0; + m_gfx_scroll_1_y = 0; + epic12_device_blit_delay = 0; +} + +static UINT16 READ_NEXT_WORD(UINT32 *addr) +{ + UINT16 data = m_use_ram[((*addr & m_main_rammask) >> 1)]; + + *addr += 2; + + return data; +} + +static void gfx_upload(UINT32 *addr) +{ + UINT32 x,y, dst_p,dst_x_start,dst_y_start, dimx,dimy; + UINT32 *dst; + + // 0x20000000 + READ_NEXT_WORD(addr); + READ_NEXT_WORD(addr); + + // 0x99999999 + READ_NEXT_WORD(addr); + READ_NEXT_WORD(addr); + + dst_x_start = READ_NEXT_WORD(addr); + dst_y_start = READ_NEXT_WORD(addr); + + dst_p = 0; + dst_x_start &= 0x1fff; + dst_y_start &= 0x0fff; + + dimx = (READ_NEXT_WORD(addr) & 0x1fff) + 1; + dimy = (READ_NEXT_WORD(addr) & 0x0fff) + 1; + + //bprintf(0, _T("GFX COPY: DST %02X,%02X,%03X DIM %02X,%03X\n"), dst_p,dst_x_start,dst_y_start, dimx,dimy); + + for (y = 0; y < dimy; y++) + { + //dst = &m_bitmaps->pix(dst_y_start + y, 0); + dst = m_bitmaps + (dst_y_start + y) * 0x2000; + + dst += dst_x_start; + + for (x = 0; x < dimx; x++) + { + UINT16 pendat = READ_NEXT_WORD(addr); + // real hw would upload the gfxword directly, but our VRAM is 32-bit, so convert it. + //dst[dst_x_start + x] = pendat; + *dst++ = ((pendat&0x8000)<<14) | ((pendat&0x7c00)<<9) | ((pendat&0x03e0)<<6) | ((pendat&0x001f)<<3); // --t- ---- rrrr r--- gggg g--- bbbb b--- format + //dst[dst_x_start + x] = ((pendat&0x8000)<<14) | ((pendat&0x7c00)<<6) | ((pendat&0x03e0)<<3) | ((pendat&0x001f)<<0); // --t- ---- ---r rrrr ---g gggg ---b bbbb format + + + } + } +} + +#define draw_params &m_clip, m_bitmaps,src_x,src_y, x,y, dimx,dimy, flipy, s_alpha, d_alpha, &tint_clr + + + +static epic12_device_blitfunction epic12_device_f0_ti1_tr1_blit_funcs[] = +{ + draw_sprite_f0_ti1_tr1_s0_d0, draw_sprite_f0_ti1_tr1_s1_d0, draw_sprite_f0_ti1_tr1_s2_d0, draw_sprite_f0_ti1_tr1_s3_d0, draw_sprite_f0_ti1_tr1_s4_d0, draw_sprite_f0_ti1_tr1_s5_d0, draw_sprite_f0_ti1_tr1_s6_d0, draw_sprite_f0_ti1_tr1_s7_d0, + draw_sprite_f0_ti1_tr1_s0_d1, draw_sprite_f0_ti1_tr1_s1_d1, draw_sprite_f0_ti1_tr1_s2_d1, draw_sprite_f0_ti1_tr1_s3_d1, draw_sprite_f0_ti1_tr1_s4_d1, draw_sprite_f0_ti1_tr1_s5_d1, draw_sprite_f0_ti1_tr1_s6_d1, draw_sprite_f0_ti1_tr1_s7_d1, + draw_sprite_f0_ti1_tr1_s0_d2, draw_sprite_f0_ti1_tr1_s1_d2, draw_sprite_f0_ti1_tr1_s2_d2, draw_sprite_f0_ti1_tr1_s3_d2, draw_sprite_f0_ti1_tr1_s4_d2, draw_sprite_f0_ti1_tr1_s5_d2, draw_sprite_f0_ti1_tr1_s6_d2, draw_sprite_f0_ti1_tr1_s7_d2, + draw_sprite_f0_ti1_tr1_s0_d3, draw_sprite_f0_ti1_tr1_s1_d3, draw_sprite_f0_ti1_tr1_s2_d3, draw_sprite_f0_ti1_tr1_s3_d3, draw_sprite_f0_ti1_tr1_s4_d3, draw_sprite_f0_ti1_tr1_s5_d3, draw_sprite_f0_ti1_tr1_s6_d3, draw_sprite_f0_ti1_tr1_s7_d3, + draw_sprite_f0_ti1_tr1_s0_d4, draw_sprite_f0_ti1_tr1_s1_d4, draw_sprite_f0_ti1_tr1_s2_d4, draw_sprite_f0_ti1_tr1_s3_d4, draw_sprite_f0_ti1_tr1_s4_d4, draw_sprite_f0_ti1_tr1_s5_d4, draw_sprite_f0_ti1_tr1_s6_d4, draw_sprite_f0_ti1_tr1_s7_d4, + draw_sprite_f0_ti1_tr1_s0_d5, draw_sprite_f0_ti1_tr1_s1_d5, draw_sprite_f0_ti1_tr1_s2_d5, draw_sprite_f0_ti1_tr1_s3_d5, draw_sprite_f0_ti1_tr1_s4_d5, draw_sprite_f0_ti1_tr1_s5_d5, draw_sprite_f0_ti1_tr1_s6_d5, draw_sprite_f0_ti1_tr1_s7_d5, + draw_sprite_f0_ti1_tr1_s0_d6, draw_sprite_f0_ti1_tr1_s1_d6, draw_sprite_f0_ti1_tr1_s2_d6, draw_sprite_f0_ti1_tr1_s3_d6, draw_sprite_f0_ti1_tr1_s4_d6, draw_sprite_f0_ti1_tr1_s5_d6, draw_sprite_f0_ti1_tr1_s6_d6, draw_sprite_f0_ti1_tr1_s7_d6, + draw_sprite_f0_ti1_tr1_s0_d7, draw_sprite_f0_ti1_tr1_s1_d7, draw_sprite_f0_ti1_tr1_s2_d7, draw_sprite_f0_ti1_tr1_s3_d7, draw_sprite_f0_ti1_tr1_s4_d7, draw_sprite_f0_ti1_tr1_s5_d7, draw_sprite_f0_ti1_tr1_s6_d7, draw_sprite_f0_ti1_tr1_s7_d7, +}; + +static epic12_device_blitfunction epic12_device_f0_ti1_tr0_blit_funcs[] = +{ + draw_sprite_f0_ti1_tr0_s0_d0, draw_sprite_f0_ti1_tr0_s1_d0, draw_sprite_f0_ti1_tr0_s2_d0, draw_sprite_f0_ti1_tr0_s3_d0, draw_sprite_f0_ti1_tr0_s4_d0, draw_sprite_f0_ti1_tr0_s5_d0, draw_sprite_f0_ti1_tr0_s6_d0, draw_sprite_f0_ti1_tr0_s7_d0, + draw_sprite_f0_ti1_tr0_s0_d1, draw_sprite_f0_ti1_tr0_s1_d1, draw_sprite_f0_ti1_tr0_s2_d1, draw_sprite_f0_ti1_tr0_s3_d1, draw_sprite_f0_ti1_tr0_s4_d1, draw_sprite_f0_ti1_tr0_s5_d1, draw_sprite_f0_ti1_tr0_s6_d1, draw_sprite_f0_ti1_tr0_s7_d1, + draw_sprite_f0_ti1_tr0_s0_d2, draw_sprite_f0_ti1_tr0_s1_d2, draw_sprite_f0_ti1_tr0_s2_d2, draw_sprite_f0_ti1_tr0_s3_d2, draw_sprite_f0_ti1_tr0_s4_d2, draw_sprite_f0_ti1_tr0_s5_d2, draw_sprite_f0_ti1_tr0_s6_d2, draw_sprite_f0_ti1_tr0_s7_d2, + draw_sprite_f0_ti1_tr0_s0_d3, draw_sprite_f0_ti1_tr0_s1_d3, draw_sprite_f0_ti1_tr0_s2_d3, draw_sprite_f0_ti1_tr0_s3_d3, draw_sprite_f0_ti1_tr0_s4_d3, draw_sprite_f0_ti1_tr0_s5_d3, draw_sprite_f0_ti1_tr0_s6_d3, draw_sprite_f0_ti1_tr0_s7_d3, + draw_sprite_f0_ti1_tr0_s0_d4, draw_sprite_f0_ti1_tr0_s1_d4, draw_sprite_f0_ti1_tr0_s2_d4, draw_sprite_f0_ti1_tr0_s3_d4, draw_sprite_f0_ti1_tr0_s4_d4, draw_sprite_f0_ti1_tr0_s5_d4, draw_sprite_f0_ti1_tr0_s6_d4, draw_sprite_f0_ti1_tr0_s7_d4, + draw_sprite_f0_ti1_tr0_s0_d5, draw_sprite_f0_ti1_tr0_s1_d5, draw_sprite_f0_ti1_tr0_s2_d5, draw_sprite_f0_ti1_tr0_s3_d5, draw_sprite_f0_ti1_tr0_s4_d5, draw_sprite_f0_ti1_tr0_s5_d5, draw_sprite_f0_ti1_tr0_s6_d5, draw_sprite_f0_ti1_tr0_s7_d5, + draw_sprite_f0_ti1_tr0_s0_d6, draw_sprite_f0_ti1_tr0_s1_d6, draw_sprite_f0_ti1_tr0_s2_d6, draw_sprite_f0_ti1_tr0_s3_d6, draw_sprite_f0_ti1_tr0_s4_d6, draw_sprite_f0_ti1_tr0_s5_d6, draw_sprite_f0_ti1_tr0_s6_d6, draw_sprite_f0_ti1_tr0_s7_d6, + draw_sprite_f0_ti1_tr0_s0_d7, draw_sprite_f0_ti1_tr0_s1_d7, draw_sprite_f0_ti1_tr0_s2_d7, draw_sprite_f0_ti1_tr0_s3_d7, draw_sprite_f0_ti1_tr0_s4_d7, draw_sprite_f0_ti1_tr0_s5_d7, draw_sprite_f0_ti1_tr0_s6_d7, draw_sprite_f0_ti1_tr0_s7_d7, +}; + +static epic12_device_blitfunction epic12_device_f1_ti1_tr1_blit_funcs[] = +{ + draw_sprite_f1_ti1_tr1_s0_d0, draw_sprite_f1_ti1_tr1_s1_d0, draw_sprite_f1_ti1_tr1_s2_d0, draw_sprite_f1_ti1_tr1_s3_d0, draw_sprite_f1_ti1_tr1_s4_d0, draw_sprite_f1_ti1_tr1_s5_d0, draw_sprite_f1_ti1_tr1_s6_d0, draw_sprite_f1_ti1_tr1_s7_d0, + draw_sprite_f1_ti1_tr1_s0_d1, draw_sprite_f1_ti1_tr1_s1_d1, draw_sprite_f1_ti1_tr1_s2_d1, draw_sprite_f1_ti1_tr1_s3_d1, draw_sprite_f1_ti1_tr1_s4_d1, draw_sprite_f1_ti1_tr1_s5_d1, draw_sprite_f1_ti1_tr1_s6_d1, draw_sprite_f1_ti1_tr1_s7_d1, + draw_sprite_f1_ti1_tr1_s0_d2, draw_sprite_f1_ti1_tr1_s1_d2, draw_sprite_f1_ti1_tr1_s2_d2, draw_sprite_f1_ti1_tr1_s3_d2, draw_sprite_f1_ti1_tr1_s4_d2, draw_sprite_f1_ti1_tr1_s5_d2, draw_sprite_f1_ti1_tr1_s6_d2, draw_sprite_f1_ti1_tr1_s7_d2, + draw_sprite_f1_ti1_tr1_s0_d3, draw_sprite_f1_ti1_tr1_s1_d3, draw_sprite_f1_ti1_tr1_s2_d3, draw_sprite_f1_ti1_tr1_s3_d3, draw_sprite_f1_ti1_tr1_s4_d3, draw_sprite_f1_ti1_tr1_s5_d3, draw_sprite_f1_ti1_tr1_s6_d3, draw_sprite_f1_ti1_tr1_s7_d3, + draw_sprite_f1_ti1_tr1_s0_d4, draw_sprite_f1_ti1_tr1_s1_d4, draw_sprite_f1_ti1_tr1_s2_d4, draw_sprite_f1_ti1_tr1_s3_d4, draw_sprite_f1_ti1_tr1_s4_d4, draw_sprite_f1_ti1_tr1_s5_d4, draw_sprite_f1_ti1_tr1_s6_d4, draw_sprite_f1_ti1_tr1_s7_d4, + draw_sprite_f1_ti1_tr1_s0_d5, draw_sprite_f1_ti1_tr1_s1_d5, draw_sprite_f1_ti1_tr1_s2_d5, draw_sprite_f1_ti1_tr1_s3_d5, draw_sprite_f1_ti1_tr1_s4_d5, draw_sprite_f1_ti1_tr1_s5_d5, draw_sprite_f1_ti1_tr1_s6_d5, draw_sprite_f1_ti1_tr1_s7_d5, + draw_sprite_f1_ti1_tr1_s0_d6, draw_sprite_f1_ti1_tr1_s1_d6, draw_sprite_f1_ti1_tr1_s2_d6, draw_sprite_f1_ti1_tr1_s3_d6, draw_sprite_f1_ti1_tr1_s4_d6, draw_sprite_f1_ti1_tr1_s5_d6, draw_sprite_f1_ti1_tr1_s6_d6, draw_sprite_f1_ti1_tr1_s7_d6, + draw_sprite_f1_ti1_tr1_s0_d7, draw_sprite_f1_ti1_tr1_s1_d7, draw_sprite_f1_ti1_tr1_s2_d7, draw_sprite_f1_ti1_tr1_s3_d7, draw_sprite_f1_ti1_tr1_s4_d7, draw_sprite_f1_ti1_tr1_s5_d7, draw_sprite_f1_ti1_tr1_s6_d7, draw_sprite_f1_ti1_tr1_s7_d7, +}; + +static epic12_device_blitfunction epic12_device_f1_ti1_tr0_blit_funcs[] = +{ + draw_sprite_f1_ti1_tr0_s0_d0, draw_sprite_f1_ti1_tr0_s1_d0, draw_sprite_f1_ti1_tr0_s2_d0, draw_sprite_f1_ti1_tr0_s3_d0, draw_sprite_f1_ti1_tr0_s4_d0, draw_sprite_f1_ti1_tr0_s5_d0, draw_sprite_f1_ti1_tr0_s6_d0, draw_sprite_f1_ti1_tr0_s7_d0, + draw_sprite_f1_ti1_tr0_s0_d1, draw_sprite_f1_ti1_tr0_s1_d1, draw_sprite_f1_ti1_tr0_s2_d1, draw_sprite_f1_ti1_tr0_s3_d1, draw_sprite_f1_ti1_tr0_s4_d1, draw_sprite_f1_ti1_tr0_s5_d1, draw_sprite_f1_ti1_tr0_s6_d1, draw_sprite_f1_ti1_tr0_s7_d1, + draw_sprite_f1_ti1_tr0_s0_d2, draw_sprite_f1_ti1_tr0_s1_d2, draw_sprite_f1_ti1_tr0_s2_d2, draw_sprite_f1_ti1_tr0_s3_d2, draw_sprite_f1_ti1_tr0_s4_d2, draw_sprite_f1_ti1_tr0_s5_d2, draw_sprite_f1_ti1_tr0_s6_d2, draw_sprite_f1_ti1_tr0_s7_d2, + draw_sprite_f1_ti1_tr0_s0_d3, draw_sprite_f1_ti1_tr0_s1_d3, draw_sprite_f1_ti1_tr0_s2_d3, draw_sprite_f1_ti1_tr0_s3_d3, draw_sprite_f1_ti1_tr0_s4_d3, draw_sprite_f1_ti1_tr0_s5_d3, draw_sprite_f1_ti1_tr0_s6_d3, draw_sprite_f1_ti1_tr0_s7_d3, + draw_sprite_f1_ti1_tr0_s0_d4, draw_sprite_f1_ti1_tr0_s1_d4, draw_sprite_f1_ti1_tr0_s2_d4, draw_sprite_f1_ti1_tr0_s3_d4, draw_sprite_f1_ti1_tr0_s4_d4, draw_sprite_f1_ti1_tr0_s5_d4, draw_sprite_f1_ti1_tr0_s6_d4, draw_sprite_f1_ti1_tr0_s7_d4, + draw_sprite_f1_ti1_tr0_s0_d5, draw_sprite_f1_ti1_tr0_s1_d5, draw_sprite_f1_ti1_tr0_s2_d5, draw_sprite_f1_ti1_tr0_s3_d5, draw_sprite_f1_ti1_tr0_s4_d5, draw_sprite_f1_ti1_tr0_s5_d5, draw_sprite_f1_ti1_tr0_s6_d5, draw_sprite_f1_ti1_tr0_s7_d5, + draw_sprite_f1_ti1_tr0_s0_d6, draw_sprite_f1_ti1_tr0_s1_d6, draw_sprite_f1_ti1_tr0_s2_d6, draw_sprite_f1_ti1_tr0_s3_d6, draw_sprite_f1_ti1_tr0_s4_d6, draw_sprite_f1_ti1_tr0_s5_d6, draw_sprite_f1_ti1_tr0_s6_d6, draw_sprite_f1_ti1_tr0_s7_d6, + draw_sprite_f1_ti1_tr0_s0_d7, draw_sprite_f1_ti1_tr0_s1_d7, draw_sprite_f1_ti1_tr0_s2_d7, draw_sprite_f1_ti1_tr0_s3_d7, draw_sprite_f1_ti1_tr0_s4_d7, draw_sprite_f1_ti1_tr0_s5_d7, draw_sprite_f1_ti1_tr0_s6_d7, draw_sprite_f1_ti1_tr0_s7_d7, +}; + + + +static epic12_device_blitfunction epic12_device_f0_ti0_tr1_blit_funcs[] = +{ + draw_sprite_f0_ti0_tr1_s0_d0, draw_sprite_f0_ti0_tr1_s1_d0, draw_sprite_f0_ti0_tr1_s2_d0, draw_sprite_f0_ti0_tr1_s3_d0, draw_sprite_f0_ti0_tr1_s4_d0, draw_sprite_f0_ti0_tr1_s5_d0, draw_sprite_f0_ti0_tr1_s6_d0, draw_sprite_f0_ti0_tr1_s7_d0, + draw_sprite_f0_ti0_tr1_s0_d1, draw_sprite_f0_ti0_tr1_s1_d1, draw_sprite_f0_ti0_tr1_s2_d1, draw_sprite_f0_ti0_tr1_s3_d1, draw_sprite_f0_ti0_tr1_s4_d1, draw_sprite_f0_ti0_tr1_s5_d1, draw_sprite_f0_ti0_tr1_s6_d1, draw_sprite_f0_ti0_tr1_s7_d1, + draw_sprite_f0_ti0_tr1_s0_d2, draw_sprite_f0_ti0_tr1_s1_d2, draw_sprite_f0_ti0_tr1_s2_d2, draw_sprite_f0_ti0_tr1_s3_d2, draw_sprite_f0_ti0_tr1_s4_d2, draw_sprite_f0_ti0_tr1_s5_d2, draw_sprite_f0_ti0_tr1_s6_d2, draw_sprite_f0_ti0_tr1_s7_d2, + draw_sprite_f0_ti0_tr1_s0_d3, draw_sprite_f0_ti0_tr1_s1_d3, draw_sprite_f0_ti0_tr1_s2_d3, draw_sprite_f0_ti0_tr1_s3_d3, draw_sprite_f0_ti0_tr1_s4_d3, draw_sprite_f0_ti0_tr1_s5_d3, draw_sprite_f0_ti0_tr1_s6_d3, draw_sprite_f0_ti0_tr1_s7_d3, + draw_sprite_f0_ti0_tr1_s0_d4, draw_sprite_f0_ti0_tr1_s1_d4, draw_sprite_f0_ti0_tr1_s2_d4, draw_sprite_f0_ti0_tr1_s3_d4, draw_sprite_f0_ti0_tr1_s4_d4, draw_sprite_f0_ti0_tr1_s5_d4, draw_sprite_f0_ti0_tr1_s6_d4, draw_sprite_f0_ti0_tr1_s7_d4, + draw_sprite_f0_ti0_tr1_s0_d5, draw_sprite_f0_ti0_tr1_s1_d5, draw_sprite_f0_ti0_tr1_s2_d5, draw_sprite_f0_ti0_tr1_s3_d5, draw_sprite_f0_ti0_tr1_s4_d5, draw_sprite_f0_ti0_tr1_s5_d5, draw_sprite_f0_ti0_tr1_s6_d5, draw_sprite_f0_ti0_tr1_s7_d5, + draw_sprite_f0_ti0_tr1_s0_d6, draw_sprite_f0_ti0_tr1_s1_d6, draw_sprite_f0_ti0_tr1_s2_d6, draw_sprite_f0_ti0_tr1_s3_d6, draw_sprite_f0_ti0_tr1_s4_d6, draw_sprite_f0_ti0_tr1_s5_d6, draw_sprite_f0_ti0_tr1_s6_d6, draw_sprite_f0_ti0_tr1_s7_d6, + draw_sprite_f0_ti0_tr1_s0_d7, draw_sprite_f0_ti0_tr1_s1_d7, draw_sprite_f0_ti0_tr1_s2_d7, draw_sprite_f0_ti0_tr1_s3_d7, draw_sprite_f0_ti0_tr1_s4_d7, draw_sprite_f0_ti0_tr1_s5_d7, draw_sprite_f0_ti0_tr1_s6_d7, draw_sprite_f0_ti0_tr1_s7_d7, +}; + +static epic12_device_blitfunction epic12_device_f0_ti0_tr0_blit_funcs[] = +{ + draw_sprite_f0_ti0_tr0_s0_d0, draw_sprite_f0_ti0_tr0_s1_d0, draw_sprite_f0_ti0_tr0_s2_d0, draw_sprite_f0_ti0_tr0_s3_d0, draw_sprite_f0_ti0_tr0_s4_d0, draw_sprite_f0_ti0_tr0_s5_d0, draw_sprite_f0_ti0_tr0_s6_d0, draw_sprite_f0_ti0_tr0_s7_d0, + draw_sprite_f0_ti0_tr0_s0_d1, draw_sprite_f0_ti0_tr0_s1_d1, draw_sprite_f0_ti0_tr0_s2_d1, draw_sprite_f0_ti0_tr0_s3_d1, draw_sprite_f0_ti0_tr0_s4_d1, draw_sprite_f0_ti0_tr0_s5_d1, draw_sprite_f0_ti0_tr0_s6_d1, draw_sprite_f0_ti0_tr0_s7_d1, + draw_sprite_f0_ti0_tr0_s0_d2, draw_sprite_f0_ti0_tr0_s1_d2, draw_sprite_f0_ti0_tr0_s2_d2, draw_sprite_f0_ti0_tr0_s3_d2, draw_sprite_f0_ti0_tr0_s4_d2, draw_sprite_f0_ti0_tr0_s5_d2, draw_sprite_f0_ti0_tr0_s6_d2, draw_sprite_f0_ti0_tr0_s7_d2, + draw_sprite_f0_ti0_tr0_s0_d3, draw_sprite_f0_ti0_tr0_s1_d3, draw_sprite_f0_ti0_tr0_s2_d3, draw_sprite_f0_ti0_tr0_s3_d3, draw_sprite_f0_ti0_tr0_s4_d3, draw_sprite_f0_ti0_tr0_s5_d3, draw_sprite_f0_ti0_tr0_s6_d3, draw_sprite_f0_ti0_tr0_s7_d3, + draw_sprite_f0_ti0_tr0_s0_d4, draw_sprite_f0_ti0_tr0_s1_d4, draw_sprite_f0_ti0_tr0_s2_d4, draw_sprite_f0_ti0_tr0_s3_d4, draw_sprite_f0_ti0_tr0_s4_d4, draw_sprite_f0_ti0_tr0_s5_d4, draw_sprite_f0_ti0_tr0_s6_d4, draw_sprite_f0_ti0_tr0_s7_d4, + draw_sprite_f0_ti0_tr0_s0_d5, draw_sprite_f0_ti0_tr0_s1_d5, draw_sprite_f0_ti0_tr0_s2_d5, draw_sprite_f0_ti0_tr0_s3_d5, draw_sprite_f0_ti0_tr0_s4_d5, draw_sprite_f0_ti0_tr0_s5_d5, draw_sprite_f0_ti0_tr0_s6_d5, draw_sprite_f0_ti0_tr0_s7_d5, + draw_sprite_f0_ti0_tr0_s0_d6, draw_sprite_f0_ti0_tr0_s1_d6, draw_sprite_f0_ti0_tr0_s2_d6, draw_sprite_f0_ti0_tr0_s3_d6, draw_sprite_f0_ti0_tr0_s4_d6, draw_sprite_f0_ti0_tr0_s5_d6, draw_sprite_f0_ti0_tr0_s6_d6, draw_sprite_f0_ti0_tr0_s7_d6, + draw_sprite_f0_ti0_tr0_s0_d7, draw_sprite_f0_ti0_tr0_s1_d7, draw_sprite_f0_ti0_tr0_s2_d7, draw_sprite_f0_ti0_tr0_s3_d7, draw_sprite_f0_ti0_tr0_s4_d7, draw_sprite_f0_ti0_tr0_s5_d7, draw_sprite_f0_ti0_tr0_s6_d7, draw_sprite_f0_ti0_tr0_s7_d7, +}; + +static epic12_device_blitfunction epic12_device_f1_ti0_tr1_blit_funcs[] = +{ + draw_sprite_f1_ti0_tr1_s0_d0, draw_sprite_f1_ti0_tr1_s1_d0, draw_sprite_f1_ti0_tr1_s2_d0, draw_sprite_f1_ti0_tr1_s3_d0, draw_sprite_f1_ti0_tr1_s4_d0, draw_sprite_f1_ti0_tr1_s5_d0, draw_sprite_f1_ti0_tr1_s6_d0, draw_sprite_f1_ti0_tr1_s7_d0, + draw_sprite_f1_ti0_tr1_s0_d1, draw_sprite_f1_ti0_tr1_s1_d1, draw_sprite_f1_ti0_tr1_s2_d1, draw_sprite_f1_ti0_tr1_s3_d1, draw_sprite_f1_ti0_tr1_s4_d1, draw_sprite_f1_ti0_tr1_s5_d1, draw_sprite_f1_ti0_tr1_s6_d1, draw_sprite_f1_ti0_tr1_s7_d1, + draw_sprite_f1_ti0_tr1_s0_d2, draw_sprite_f1_ti0_tr1_s1_d2, draw_sprite_f1_ti0_tr1_s2_d2, draw_sprite_f1_ti0_tr1_s3_d2, draw_sprite_f1_ti0_tr1_s4_d2, draw_sprite_f1_ti0_tr1_s5_d2, draw_sprite_f1_ti0_tr1_s6_d2, draw_sprite_f1_ti0_tr1_s7_d2, + draw_sprite_f1_ti0_tr1_s0_d3, draw_sprite_f1_ti0_tr1_s1_d3, draw_sprite_f1_ti0_tr1_s2_d3, draw_sprite_f1_ti0_tr1_s3_d3, draw_sprite_f1_ti0_tr1_s4_d3, draw_sprite_f1_ti0_tr1_s5_d3, draw_sprite_f1_ti0_tr1_s6_d3, draw_sprite_f1_ti0_tr1_s7_d3, + draw_sprite_f1_ti0_tr1_s0_d4, draw_sprite_f1_ti0_tr1_s1_d4, draw_sprite_f1_ti0_tr1_s2_d4, draw_sprite_f1_ti0_tr1_s3_d4, draw_sprite_f1_ti0_tr1_s4_d4, draw_sprite_f1_ti0_tr1_s5_d4, draw_sprite_f1_ti0_tr1_s6_d4, draw_sprite_f1_ti0_tr1_s7_d4, + draw_sprite_f1_ti0_tr1_s0_d5, draw_sprite_f1_ti0_tr1_s1_d5, draw_sprite_f1_ti0_tr1_s2_d5, draw_sprite_f1_ti0_tr1_s3_d5, draw_sprite_f1_ti0_tr1_s4_d5, draw_sprite_f1_ti0_tr1_s5_d5, draw_sprite_f1_ti0_tr1_s6_d5, draw_sprite_f1_ti0_tr1_s7_d5, + draw_sprite_f1_ti0_tr1_s0_d6, draw_sprite_f1_ti0_tr1_s1_d6, draw_sprite_f1_ti0_tr1_s2_d6, draw_sprite_f1_ti0_tr1_s3_d6, draw_sprite_f1_ti0_tr1_s4_d6, draw_sprite_f1_ti0_tr1_s5_d6, draw_sprite_f1_ti0_tr1_s6_d6, draw_sprite_f1_ti0_tr1_s7_d6, + draw_sprite_f1_ti0_tr1_s0_d7, draw_sprite_f1_ti0_tr1_s1_d7, draw_sprite_f1_ti0_tr1_s2_d7, draw_sprite_f1_ti0_tr1_s3_d7, draw_sprite_f1_ti0_tr1_s4_d7, draw_sprite_f1_ti0_tr1_s5_d7, draw_sprite_f1_ti0_tr1_s6_d7, draw_sprite_f1_ti0_tr1_s7_d7, +}; + +static epic12_device_blitfunction epic12_device_f1_ti0_tr0_blit_funcs[] = +{ + draw_sprite_f1_ti0_tr0_s0_d0, draw_sprite_f1_ti0_tr0_s1_d0, draw_sprite_f1_ti0_tr0_s2_d0, draw_sprite_f1_ti0_tr0_s3_d0, draw_sprite_f1_ti0_tr0_s4_d0, draw_sprite_f1_ti0_tr0_s5_d0, draw_sprite_f1_ti0_tr0_s6_d0, draw_sprite_f1_ti0_tr0_s7_d0, + draw_sprite_f1_ti0_tr0_s0_d1, draw_sprite_f1_ti0_tr0_s1_d1, draw_sprite_f1_ti0_tr0_s2_d1, draw_sprite_f1_ti0_tr0_s3_d1, draw_sprite_f1_ti0_tr0_s4_d1, draw_sprite_f1_ti0_tr0_s5_d1, draw_sprite_f1_ti0_tr0_s6_d1, draw_sprite_f1_ti0_tr0_s7_d1, + draw_sprite_f1_ti0_tr0_s0_d2, draw_sprite_f1_ti0_tr0_s1_d2, draw_sprite_f1_ti0_tr0_s2_d2, draw_sprite_f1_ti0_tr0_s3_d2, draw_sprite_f1_ti0_tr0_s4_d2, draw_sprite_f1_ti0_tr0_s5_d2, draw_sprite_f1_ti0_tr0_s6_d2, draw_sprite_f1_ti0_tr0_s7_d2, + draw_sprite_f1_ti0_tr0_s0_d3, draw_sprite_f1_ti0_tr0_s1_d3, draw_sprite_f1_ti0_tr0_s2_d3, draw_sprite_f1_ti0_tr0_s3_d3, draw_sprite_f1_ti0_tr0_s4_d3, draw_sprite_f1_ti0_tr0_s5_d3, draw_sprite_f1_ti0_tr0_s6_d3, draw_sprite_f1_ti0_tr0_s7_d3, + draw_sprite_f1_ti0_tr0_s0_d4, draw_sprite_f1_ti0_tr0_s1_d4, draw_sprite_f1_ti0_tr0_s2_d4, draw_sprite_f1_ti0_tr0_s3_d4, draw_sprite_f1_ti0_tr0_s4_d4, draw_sprite_f1_ti0_tr0_s5_d4, draw_sprite_f1_ti0_tr0_s6_d4, draw_sprite_f1_ti0_tr0_s7_d4, + draw_sprite_f1_ti0_tr0_s0_d5, draw_sprite_f1_ti0_tr0_s1_d5, draw_sprite_f1_ti0_tr0_s2_d5, draw_sprite_f1_ti0_tr0_s3_d5, draw_sprite_f1_ti0_tr0_s4_d5, draw_sprite_f1_ti0_tr0_s5_d5, draw_sprite_f1_ti0_tr0_s6_d5, draw_sprite_f1_ti0_tr0_s7_d5, + draw_sprite_f1_ti0_tr0_s0_d6, draw_sprite_f1_ti0_tr0_s1_d6, draw_sprite_f1_ti0_tr0_s2_d6, draw_sprite_f1_ti0_tr0_s3_d6, draw_sprite_f1_ti0_tr0_s4_d6, draw_sprite_f1_ti0_tr0_s5_d6, draw_sprite_f1_ti0_tr0_s6_d6, draw_sprite_f1_ti0_tr0_s7_d6, + draw_sprite_f1_ti0_tr0_s0_d7, draw_sprite_f1_ti0_tr0_s1_d7, draw_sprite_f1_ti0_tr0_s2_d7, draw_sprite_f1_ti0_tr0_s3_d7, draw_sprite_f1_ti0_tr0_s4_d7, draw_sprite_f1_ti0_tr0_s5_d7, draw_sprite_f1_ti0_tr0_s6_d7, draw_sprite_f1_ti0_tr0_s7_d7, +}; + + +static void gfx_draw(UINT32 *addr) +{ + int x,y, dimx,dimy, flipx,flipy;//, src_p; + int trans,blend, s_mode, d_mode; + clr_t tint_clr; + int tinted = 0; + + UINT16 attr = READ_NEXT_WORD(addr); + UINT16 alpha = READ_NEXT_WORD(addr); + UINT16 src_x = READ_NEXT_WORD(addr); + UINT16 src_y = READ_NEXT_WORD(addr); + UINT16 dst_x_start = READ_NEXT_WORD(addr); + UINT16 dst_y_start = READ_NEXT_WORD(addr); + UINT16 w = READ_NEXT_WORD(addr); + UINT16 h = READ_NEXT_WORD(addr); + UINT16 tint_r = READ_NEXT_WORD(addr); + UINT16 tint_gb = READ_NEXT_WORD(addr); + + // 0: +alpha + // 1: +source + // 2: +dest + // 3: * + // 4: -alpha + // 5: -source + // 6: -dest + // 7: * + + d_mode = attr & 0x0007; + s_mode = (attr & 0x0070) >> 4; + + trans = attr & 0x0100; + blend = attr & 0x0200; + + flipy = attr & 0x0400; + flipx = attr & 0x0800; + + const UINT8 d_alpha = ((alpha & 0x00ff) )>>3; + const UINT8 s_alpha = ((alpha & 0xff00) >> 8 )>>3; + +// src_p = 0; + src_x = src_x & 0x1fff; + src_y = src_y & 0x0fff; + + + x = (dst_x_start & 0x7fff) - (dst_x_start & 0x8000); + y = (dst_y_start & 0x7fff) - (dst_y_start & 0x8000); + + dimx = (w & 0x1fff) + 1; + dimy = (h & 0x0fff) + 1; + + // convert parameters to clr + + + tint_to_clr(tint_r & 0x00ff, (tint_gb >> 8) & 0xff, tint_gb & 0xff, &tint_clr); + + /* interestingly this gets set to 0x20 for 'normal' not 0x1f */ + + if (tint_clr.r!=0x20) + tinted = 1; + + if (tint_clr.g!=0x20) + tinted = 1; + + if (tint_clr.b!=0x20) + tinted = 1; + + + // surprisingly frequent, need to verify if it produces a worthwhile speedup tho. + if ((s_mode==0 && s_alpha==0x1f) && (d_mode==4 && d_alpha==0x1f)) + blend = 0; + + if (tinted) + { + if (!flipx) + { + if (trans) + { + if (!blend) + { + draw_sprite_f0_ti1_tr1_plain(draw_params); + } + else + { + epic12_device_f0_ti1_tr1_blit_funcs[s_mode | (d_mode<<3)](draw_params); + } + } + else + { + if (!blend) + { + draw_sprite_f0_ti1_tr0_plain(draw_params); + } + else + { + epic12_device_f0_ti1_tr0_blit_funcs[s_mode | (d_mode<<3)](draw_params); + } + } + } + else // flipx + { + if (trans) + { + if (!blend) + { + draw_sprite_f1_ti1_tr1_plain(draw_params); + } + else + { + epic12_device_f1_ti1_tr1_blit_funcs[s_mode | (d_mode<<3)](draw_params); + } + } + else + { + if (!blend) + { + draw_sprite_f1_ti1_tr0_plain(draw_params); + } + else + { + epic12_device_f1_ti1_tr0_blit_funcs[s_mode | (d_mode<<3)](draw_params); + } + } + } + } + else + { + if (blend==0 && tinted==0) + { + if (!flipx) + { + if (trans) + { + draw_sprite_f0_ti0_tr1_simple(draw_params); + } + else + { + draw_sprite_f0_ti0_tr0_simple(draw_params); + } + } + else + { + if (trans) + { + draw_sprite_f1_ti0_tr1_simple(draw_params); + } + else + { + draw_sprite_f1_ti0_tr0_simple(draw_params); + } + + } + + return; + } + + + + //printf("smode %d dmode %d\n", s_mode, d_mode); + + if (!flipx) + { + if (trans) + { + if (!blend) + { + draw_sprite_f0_ti0_plain(draw_params); + } + else + { + epic12_device_f0_ti0_tr1_blit_funcs[s_mode | (d_mode<<3)](draw_params); + } + } + else + { + if (!blend) + { + draw_sprite_f0_ti0_tr0_plain(draw_params); + } + else + { + epic12_device_f0_ti0_tr0_blit_funcs[s_mode | (d_mode<<3)](draw_params); + } + } + } + else // flipx + { + if (trans) + { + if (!blend) + { + draw_sprite_f1_ti0_plain(draw_params); + } + else + { + epic12_device_f1_ti0_tr1_blit_funcs[s_mode | (d_mode<<3)](draw_params); + } + } + else + { + if (!blend) + { + draw_sprite_f1_ti0_tr0_plain(draw_params); + } + else + { + epic12_device_f1_ti0_tr0_blit_funcs[s_mode | (d_mode<<3)](draw_params); + } + } + } + } +} + + +static void gfx_exec() +{ + UINT32 addr = m_gfx_addr & 0x1fffffff; + m_clip.set(m_gfx_scroll_1_x, m_gfx_scroll_1_x + 320-1, m_gfx_scroll_1_y, m_gfx_scroll_1_y + 240-1); + +// logerror("GFX EXEC: %08X\n", addr); + + while (1) + { + UINT16 data = READ_NEXT_WORD(&addr); + + switch( data & 0xf000 ) + { + case 0x0000: + case 0xf000: + return; + + case 0xc000: + if (READ_NEXT_WORD(&addr)) // cliptype + m_clip.set(m_gfx_scroll_1_x, m_gfx_scroll_1_x + 320-1, m_gfx_scroll_1_y, m_gfx_scroll_1_y + 240-1); + else + m_clip.set(0, 0x2000-1, 0, 0x1000-1); + break; + + case 0x2000: + addr -= 2; + gfx_upload(&addr); + break; + + case 0x1000: + addr -= 2; + gfx_draw(&addr); + break; + + default: + //popmessage("GFX op = %04X", data); + return; + } + } +} + + + +static UINT32 gfx_ready_read() +{ + if (m_blitter_busy) + { + //m_maincpu->spin_until_time(attotime::from_usec(10)); + Sh3BurnCycles(m_burn_cycles); // 0x400 @ (12800000*8) + //bprintf(0, _T("%d frame - blitter busy read....."), nCurrentFrame); + + return 0x00000000; + } + else + return 0x00000010; +} + + +static void gfx_exec_write(UINT32 offset, UINT32 data) +{ +// if ( ACCESSING_BITS_0_7 ) + { + if (data & 1) + { + if (epic12_device_blit_delay && m_delay_scale) + { + m_blitter_busy = 1; + int delay = epic12_device_blit_delay*(15 * m_delay_scale / 50); + INT32 cycles = (INT32)((double)((double)delay / 1000000000) * sh4_get_cpu_speed()); + + sh4_set_cave_blitter_delay_timer(cycles); + } + else + { + m_blitter_busy = 0; + } + + epic12_device_blit_delay = 0; + + if (!bBurnRunAheadFrame) thready.notify(); // run gfx_exec(), w/ threading if set (via dip option) + } + } +} + + +void epic12_draw_screen() +{ + INT32 scrollx = -m_gfx_scroll_0_x; + INT32 scrolly = -m_gfx_scroll_0_y; + + if (nBurnBpp != 4) { + //bprintf(0, _T("epic12_draw_screen(): need 32bit for now!\n")); + return; + } + + UINT32 *dst = (UINT32 *)pBurnDraw; + UINT32 *src = (UINT32 *)m_bitmaps; + const INT32 heightmask = 0x1000 - 1; + const INT32 widthmask = 0x2000 - 1; + + for (INT32 y = 0; y < nScreenHeight; y++) + { + UINT32 *s0 = &src[((y - scrolly) & heightmask) * 0x2000]; + UINT32 *d0 = dst + (y * nScreenWidth); + INT32 sx; + for (INT32 x = 0; x < nScreenWidth; x+=16) + { + sx = x - scrollx; + d0[x + 0] = s0[((sx + 0)) & widthmask]; + d0[x + 1] = s0[((sx + 1)) & widthmask]; + d0[x + 2] = s0[((sx + 2)) & widthmask]; + d0[x + 3] = s0[((sx + 3)) & widthmask]; + d0[x + 4] = s0[((sx + 4)) & widthmask]; + d0[x + 5] = s0[((sx + 5)) & widthmask]; + d0[x + 6] = s0[((sx + 6)) & widthmask]; + d0[x + 7] = s0[((sx + 7)) & widthmask]; + d0[x + 8] = s0[((sx + 8)) & widthmask]; + d0[x + 9] = s0[((sx + 9)) & widthmask]; + d0[x +10] = s0[((sx +10)) & widthmask]; + d0[x +11] = s0[((sx +11)) & widthmask]; + d0[x +12] = s0[((sx +12)) & widthmask]; + d0[x +13] = s0[((sx +13)) & widthmask]; + d0[x +14] = s0[((sx +14)) & widthmask]; + d0[x +15] = s0[((sx +15)) & widthmask]; + } + } +} + + + +// 0x18000000 - 0x18000057 + +UINT32 epic12_blitter_read(UINT32 offset) +{ + switch (offset) + { + case 0x10: + return gfx_ready_read(); + + case 0x24: + return 0xffffffff; + + case 0x28: + return 0xffffffff; + + case 0x50: + return *dips; + + default: + //logerror("unknownblitter_r %08x %08x\n", offset*4, mem_mask); + break; + + } + return 0; +} + + +void epic12_blitter_write(UINT32 offset, UINT32 data) +{ + switch (offset) + { + case 0x04: + gfx_exec_write(offset,data); + break; + + case 0x08: + m_gfx_addr = data & 0xffffff; + break; + + case 0x14: + m_gfx_scroll_0_x = data; + break; + + case 0x18: + m_gfx_scroll_0_y = data; + break; + + case 0x40: + m_gfx_scroll_1_x = data; + break; + + case 0x44: + m_gfx_scroll_1_y = data; + break; + } +} + +void epic12_scan(INT32 nAction, INT32 *pnMin) +{ + SCAN_VAR(m_gfx_addr); + SCAN_VAR(m_gfx_scroll_0_x); + SCAN_VAR(m_gfx_scroll_0_y); + SCAN_VAR(m_gfx_scroll_1_x); + SCAN_VAR(m_gfx_scroll_1_y); + SCAN_VAR(epic12_device_blit_delay); + SCAN_VAR(m_delay_scale); + SCAN_VAR(m_blitter_busy); + ScanVar(m_bitmaps, m_gfx_size * 4, "epic12 vram"); +} + diff --git a/src/burn/devices/epic12.h b/src/burn/devices/epic12.h new file mode 100644 index 000000000..fe9e81771 --- /dev/null +++ b/src/burn/devices/epic12.h @@ -0,0 +1,12 @@ +/* emulation of Altera Cyclone EPIC12 FPGA programmed as a blitter */ + +void epic12_init(INT32 ram_size, UINT16 *ram, UINT8 *dippy); +void epic12_exit(); +void epic12_reset(); +void epic12_scan(INT32 nAction, INT32 *pnMin); +void epic12_set_blitterdelay(INT32 delay, INT32 burn_cycles); +void epic12_set_blitterthreading(INT32 value); +void epic12_draw_screen(); +UINT32 epic12_blitter_read(UINT32 offset); // 0x18000000 - 0x18000057 +void epic12_blitter_write(UINT32 offset, UINT32 data); + diff --git a/src/burn/devices/epic12_blit0.inc b/src/burn/devices/epic12_blit0.inc new file mode 100644 index 000000000..31a544e90 --- /dev/null +++ b/src/burn/devices/epic12_blit0.inc @@ -0,0 +1,556 @@ +#define REALLY_SIMPLE 0 +/* Non-Flipped, Non-Tinted, Transparent */ +#define FLIPX 0 +#define TINT 0 +#define TRANSPARENT 1 + +//#include "emu.h" +//#include "epic12.h" + +/* Special Case */ +#define BLENDED 0 +#define FUNCNAME draw_sprite_f0_ti0_plain +#include "epic12in.inc" +#undef FUNCNAME +#undef BLENDED + +/* Regular Cases*/ +#define BLENDED 1 + +#define _SMODE 0 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s0_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s1_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s2_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s3_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s4_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s5_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s6_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s7_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/////// + + +#define _SMODE 0 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s0_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s1_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s2_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s3_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s4_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s5_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s6_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s7_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +//// + + +#define _SMODE 0 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s0_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s1_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s2_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s3_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s4_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s5_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s6_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s7_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s0_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s1_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s2_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s3_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s4_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s5_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s6_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s7_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s0_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s1_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s2_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s3_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s4_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s5_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s6_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s7_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + +#define _SMODE 0 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s0_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s1_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s2_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s3_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s4_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s5_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s6_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s7_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + +#define _SMODE 0 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s0_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s1_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s2_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s3_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s4_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s5_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s6_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s7_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s0_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s1_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s2_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s3_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s4_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s5_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s6_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti0_tr1_s7_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#undef BLENDED + +#undef FLIPX +#undef TINT +#undef TRANSPARENT +#undef REALLY_SIMPLE diff --git a/src/burn/devices/epic12_blit1.inc b/src/burn/devices/epic12_blit1.inc new file mode 100644 index 000000000..f309161d8 --- /dev/null +++ b/src/burn/devices/epic12_blit1.inc @@ -0,0 +1,556 @@ +#define REALLY_SIMPLE 0 +/* Non-Flipped, Non-Tinted, Non-Transparent */ +#define FLIPX 0 +#define TINT 0 +#define TRANSPARENT 0 + +//#include "emu.h" +//#include "epic12.h" + +/* Special Case */ +#define BLENDED 0 +#define FUNCNAME draw_sprite_f0_ti0_tr0_plain +#include "epic12in.inc" +#undef FUNCNAME +#undef BLENDED + +/* Regular Cases*/ +#define BLENDED 1 + +#define _SMODE 0 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s0_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s1_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s2_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s3_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s4_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s5_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s6_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s7_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/////// + + +#define _SMODE 0 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s0_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s1_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s2_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s3_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s4_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s5_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s6_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s7_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +//// + + +#define _SMODE 0 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s0_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s1_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s2_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s3_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s4_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s5_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s6_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s7_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s0_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s1_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s2_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s3_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s4_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s5_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s6_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s7_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s0_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s1_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s2_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s3_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s4_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s5_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s6_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s7_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + +#define _SMODE 0 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s0_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s1_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s2_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s3_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s4_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s5_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s6_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s7_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + +#define _SMODE 0 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s0_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s1_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s2_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s3_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s4_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s5_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s6_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s7_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s0_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s1_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s2_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s3_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s4_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s5_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s6_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti0_tr0_s7_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#undef BLENDED + +#undef FLIPX +#undef TINT +#undef TRANSPARENT +#undef REALLY_SIMPLE diff --git a/src/burn/devices/epic12_blit2.inc b/src/burn/devices/epic12_blit2.inc new file mode 100644 index 000000000..35ca6ba93 --- /dev/null +++ b/src/burn/devices/epic12_blit2.inc @@ -0,0 +1,556 @@ +#define REALLY_SIMPLE 0 +/* X-Flipped, Non-Tinted, Transparent */ +#define FLIPX 1 +#define TINT 0 +#define TRANSPARENT 1 + +//#include "emu.h" +//#include "epic12.h" + +/* Special Case */ +#define BLENDED 0 +#define FUNCNAME draw_sprite_f1_ti0_plain +#include "epic12in.inc" +#undef FUNCNAME +#undef BLENDED + +/* Regular Cases*/ +#define BLENDED 1 + +#define _SMODE 0 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s0_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s1_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s2_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s3_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s4_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s5_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s6_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s7_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/////// + + +#define _SMODE 0 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s0_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s1_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s2_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s3_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s4_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s5_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s6_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s7_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +//// + + +#define _SMODE 0 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s0_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s1_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s2_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s3_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s4_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s5_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s6_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s7_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s0_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s1_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s2_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s3_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s4_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s5_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s6_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s7_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s0_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s1_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s2_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s3_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s4_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s5_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s6_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s7_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + +#define _SMODE 0 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s0_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s1_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s2_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s3_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s4_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s5_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s6_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s7_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + +#define _SMODE 0 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s0_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s1_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s2_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s3_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s4_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s5_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s6_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s7_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s0_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s1_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s2_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s3_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s4_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s5_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s6_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti0_tr1_s7_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#undef BLENDED + +#undef FLIPX +#undef TINT +#undef TRANSPARENT +#undef REALLY_SIMPLE diff --git a/src/burn/devices/epic12_blit3.inc b/src/burn/devices/epic12_blit3.inc new file mode 100644 index 000000000..df6e4eb2b --- /dev/null +++ b/src/burn/devices/epic12_blit3.inc @@ -0,0 +1,556 @@ +#define REALLY_SIMPLE 0 +/* X-Flipped, Non-Tinted, Non-Transparent */ +#define FLIPX 1 +#define TINT 0 +#define TRANSPARENT 0 + +//#include "emu.h" +//#include "epic12.h" + +/* Special Case */ +#define BLENDED 0 +#define FUNCNAME draw_sprite_f1_ti0_tr0_plain +#include "epic12in.inc" +#undef FUNCNAME +#undef BLENDED + +/* Regular Cases*/ +#define BLENDED 1 + +#define _SMODE 0 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s0_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s1_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s2_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s3_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s4_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s5_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s6_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s7_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/////// + + +#define _SMODE 0 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s0_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s1_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s2_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s3_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s4_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s5_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s6_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s7_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +//// + + +#define _SMODE 0 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s0_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s1_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s2_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s3_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s4_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s5_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s6_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s7_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s0_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s1_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s2_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s3_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s4_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s5_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s6_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s7_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s0_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s1_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s2_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s3_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s4_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s5_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s6_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s7_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + +#define _SMODE 0 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s0_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s1_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s2_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s3_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s4_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s5_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s6_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s7_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + +#define _SMODE 0 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s0_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s1_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s2_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s3_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s4_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s5_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s6_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s7_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s0_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s1_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s2_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s3_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s4_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s5_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s6_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti0_tr0_s7_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#undef BLENDED + +#undef FLIPX +#undef TINT +#undef TRANSPARENT +#undef REALLY_SIMPLE diff --git a/src/burn/devices/epic12_blit4.inc b/src/burn/devices/epic12_blit4.inc new file mode 100644 index 000000000..2cb9649fe --- /dev/null +++ b/src/burn/devices/epic12_blit4.inc @@ -0,0 +1,556 @@ +#define REALLY_SIMPLE 0 +/* Non-Flipped, Tinted, Transparent */ +#define FLIPX 0 +#define TINT 1 +#define TRANSPARENT 1 + +//#include "emu.h" +//#include "epic12.h" + +/* Special Case */ +#define BLENDED 0 +#define FUNCNAME draw_sprite_f0_ti1_tr1_plain +#include "epic12in.inc" +#undef FUNCNAME +#undef BLENDED + +/* Regular Cases*/ +#define BLENDED 1 + +#define _SMODE 0 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s0_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s1_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s2_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s3_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s4_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s5_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s6_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s7_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/////// + + +#define _SMODE 0 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s0_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s1_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s2_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s3_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s4_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s5_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s6_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s7_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +//// + + +#define _SMODE 0 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s0_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s1_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s2_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s3_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s4_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s5_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s6_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s7_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s0_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s1_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s2_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s3_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s4_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s5_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s6_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s7_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s0_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s1_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s2_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s3_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s4_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s5_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s6_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s7_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + +#define _SMODE 0 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s0_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s1_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s2_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s3_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s4_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s5_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s6_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s7_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + +#define _SMODE 0 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s0_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s1_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s2_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s3_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s4_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s5_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s6_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s7_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s0_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s1_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s2_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s3_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s4_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s5_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s6_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti1_tr1_s7_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#undef BLENDED + +#undef FLIPX +#undef TINT +#undef TRANSPARENT +#undef REALLY_SIMPLE diff --git a/src/burn/devices/epic12_blit5.inc b/src/burn/devices/epic12_blit5.inc new file mode 100644 index 000000000..43fb4fe73 --- /dev/null +++ b/src/burn/devices/epic12_blit5.inc @@ -0,0 +1,556 @@ +#define REALLY_SIMPLE 0 +/* Non-Flipped, Tinted, Non-Transparent */ +#define FLIPX 0 +#define TINT 1 +#define TRANSPARENT 0 + +//#include "emu.h" +//#include "epic12.h" + +/* Special Case */ +#define BLENDED 0 +#define FUNCNAME draw_sprite_f0_ti1_tr0_plain +#include "epic12in.inc" +#undef FUNCNAME +#undef BLENDED + +/* Regular Cases*/ +#define BLENDED 1 + +#define _SMODE 0 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s0_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s1_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s2_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s3_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s4_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s5_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s6_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s7_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/////// + + +#define _SMODE 0 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s0_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s1_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s2_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s3_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s4_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s5_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s6_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s7_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +//// + + +#define _SMODE 0 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s0_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s1_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s2_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s3_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s4_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s5_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s6_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s7_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s0_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s1_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s2_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s3_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s4_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s5_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s6_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s7_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s0_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s1_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s2_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s3_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s4_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s5_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s6_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s7_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + +#define _SMODE 0 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s0_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s1_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s2_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s3_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s4_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s5_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s6_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s7_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + +#define _SMODE 0 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s0_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s1_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s2_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s3_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s4_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s5_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s6_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s7_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s0_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s1_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s2_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s3_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s4_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s5_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s6_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f0_ti1_tr0_s7_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#undef BLENDED + +#undef FLIPX +#undef TINT +#undef TRANSPARENT +#undef REALLY_SIMPLE diff --git a/src/burn/devices/epic12_blit6.inc b/src/burn/devices/epic12_blit6.inc new file mode 100644 index 000000000..8212e6c36 --- /dev/null +++ b/src/burn/devices/epic12_blit6.inc @@ -0,0 +1,556 @@ +#define REALLY_SIMPLE 0 +/* X-Flipped, Tinted, Transparent */ +#define FLIPX 1 +#define TINT 1 +#define TRANSPARENT 1 + +//#include "emu.h" +//#include "epic12.h" + +/* Special Case */ +#define BLENDED 0 +#define FUNCNAME draw_sprite_f1_ti1_tr1_plain +#include "epic12in.inc" +#undef FUNCNAME +#undef BLENDED + +/* Regular Cases*/ +#define BLENDED 1 + +#define _SMODE 0 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s0_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s1_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s2_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s3_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s4_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s5_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s6_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s7_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/////// + + +#define _SMODE 0 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s0_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s1_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s2_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s3_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s4_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s5_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s6_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s7_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +//// + + +#define _SMODE 0 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s0_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s1_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s2_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s3_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s4_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s5_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s6_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s7_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s0_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s1_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s2_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s3_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s4_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s5_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s6_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s7_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s0_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s1_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s2_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s3_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s4_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s5_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s6_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s7_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + +#define _SMODE 0 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s0_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s1_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s2_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s3_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s4_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s5_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s6_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s7_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + +#define _SMODE 0 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s0_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s1_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s2_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s3_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s4_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s5_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s6_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s7_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s0_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s1_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s2_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s3_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s4_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s5_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s6_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti1_tr1_s7_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#undef BLENDED + +#undef FLIPX +#undef TINT +#undef TRANSPARENT +#undef REALLY_SIMPLE diff --git a/src/burn/devices/epic12_blit7.inc b/src/burn/devices/epic12_blit7.inc new file mode 100644 index 000000000..c82e68725 --- /dev/null +++ b/src/burn/devices/epic12_blit7.inc @@ -0,0 +1,556 @@ +#define REALLY_SIMPLE 0 +/* X-Flipped, Tinted, Non-Transparent */ +#define FLIPX 1 +#define TINT 1 +#define TRANSPARENT 0 + +//#include "emu.h" +//#include "epic12.h" + +/* Special Case */ +#define BLENDED 0 +#define FUNCNAME draw_sprite_f1_ti1_tr0_plain +#include "epic12in.inc" +#undef FUNCNAME +#undef BLENDED + +/* Regular Cases*/ +#define BLENDED 1 + +#define _SMODE 0 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s0_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s1_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s2_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s3_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s4_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s5_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s6_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 0 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s7_d0 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/////// + + +#define _SMODE 0 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s0_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s1_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s2_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s3_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s4_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s5_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s6_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 1 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s7_d1 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +//// + + +#define _SMODE 0 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s0_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s1_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s2_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s3_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s4_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s5_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s6_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 2 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s7_d2 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s0_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s1_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s2_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s3_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s4_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s5_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s6_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 3 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s7_d3 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s0_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s1_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s2_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s3_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s4_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s5_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s6_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 4 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s7_d4 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + +#define _SMODE 0 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s0_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s1_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s2_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s3_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s4_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s5_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s6_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 5 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s7_d5 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + +#define _SMODE 0 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s0_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s1_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s2_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s3_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s4_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s5_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s6_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 6 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s7_d6 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +/// + + +#define _SMODE 0 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s0_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 1 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s1_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 2 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s2_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 3 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s3_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 4 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s4_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 5 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s5_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 6 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s6_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#define _SMODE 7 +#define _DMODE 7 +#define FUNCNAME draw_sprite_f1_ti1_tr0_s7_d7 +#include "epic12in.inc" +#undef FUNCNAME +#undef _SMODE +#undef _DMODE + +#undef BLENDED + +#undef FLIPX +#undef TINT +#undef TRANSPARENT +#undef REALLY_SIMPLE diff --git a/src/burn/devices/epic12_blit8.inc b/src/burn/devices/epic12_blit8.inc new file mode 100644 index 000000000..7e4747754 --- /dev/null +++ b/src/burn/devices/epic12_blit8.inc @@ -0,0 +1,40 @@ +/* Special case 'Really Simple' blitters, no blending, no tinting etc.*/ + +//#include "emu.h" +//#include "epic12.h" + + +#define REALLY_SIMPLE 1 +#define BLENDED 0 + +#define TRANSPARENT 1 +#define FLIPX 0 +#define FUNCNAME draw_sprite_f0_ti0_tr1_simple +#include "epic12in.inc" +#undef FUNCNAME +#undef FLIPX + +#define FLIPX 1 +#define FUNCNAME draw_sprite_f1_ti0_tr1_simple +#include "epic12in.inc" +#undef FUNCNAME +#undef FLIPX +#undef TRANSPARENT + + +#define TRANSPARENT 0 +#define FLIPX 0 +#define FUNCNAME draw_sprite_f0_ti0_tr0_simple +#include "epic12in.inc" +#undef FUNCNAME +#undef FLIPX + +#define FLIPX 1 +#define FUNCNAME draw_sprite_f1_ti0_tr0_simple +#include "epic12in.inc" +#undef FUNCNAME +#undef FLIPX +#undef TRANSPARENT + +#undef BLENDED +#undef REALLY_SIMPLE diff --git a/src/burn/devices/epic12in.inc b/src/burn/devices/epic12in.inc new file mode 100644 index 000000000..e54a0a983 --- /dev/null +++ b/src/burn/devices/epic12in.inc @@ -0,0 +1,168 @@ +/* blitter function */ + +static const void FUNCNAME(BLIT_PARAMS) +{ + UINT32* gfx2; + int y, yf; + +#if REALLY_SIMPLE == 0 + colour_t s_clr; +#endif + +#if BLENDED == 1 + colour_t d_clr; + +#if _SMODE == 2 +#if _DMODE != 0 + colour_t clr0; +#endif +#elif _SMODE == 0 +#if _DMODE != 0 +#if _DMODE != 5 +#if _DMODE != 1 + colour_t clr0; +#endif +#endif +#endif +#else + colour_t clr0; +#endif + + +#endif + +#if REALLY_SIMPLE == 1 +#if TRANSPARENT == 1 + UINT32 pen; +#endif +#else + UINT32 pen; +#endif + UINT32 *bmp; + +#if FLIPX == 1 + src_x += (dimx-1); +#endif + + if (flipy) { yf = -1; src_y += (dimy-1); } + else { yf = +1; } + + int starty = 0; + const int dst_y_end = dst_y_start+dimy; + + if (dst_y_start < clip->min_y) + starty = clip->min_y - dst_y_start; + + if (dst_y_end > clip->max_y) + dimy -= (dst_y_end-1) - clip->max_y; + + // check things are safe to draw (note, if the source would wrap round an edge of the 0x2000*0x1000 vram we don't draw.. not sure what the hw does anyway) + // ddpdfk triggers this on boss explosions so it needs fixing +#if FLIPX == 1 + if ((src_x &0x1fff) < ((src_x-(dimx-1))&0x1fff)) + { + // popmessage("sprite gets clipped off src_x %04x dimx %04x\n", src_x, dimx); + return; + } +#else + if ((src_x &0x1fff) > ((src_x+(dimx-1))&0x1fff)) + { + // popmessage("sprite gets clipped off src_x %04x dimx %04x\n", src_x, dimx); + return; + } +#endif + + int startx = 0; + const int dst_x_end = dst_x_start+dimx; + + if (dst_x_start < clip->min_x) + startx = clip->min_x - dst_x_start; + + if (dst_x_end > clip->max_x) + dimx -= (dst_x_end-1) - clip->max_x; + +// wrong/unsafe slowdown sim + if (dimy > starty && dimx > startx) + { + epic12_device_blit_delay += (dimy - starty)*(dimx - startx); + + //printf("delay is now %d\n", epic12_device_blit_delay); + } + +#if BLENDED == 1 +#if _SMODE == 0 +#if _DMODE == 0 + const UINT8* salpha_table = epic12_device_colrtable[s_alpha]; + const UINT8* dalpha_table = epic12_device_colrtable[d_alpha]; +#endif + +#if _DMODE == 5 + const UINT8* salpha_table = epic12_device_colrtable[s_alpha]; +#endif +#if _DMODE == 1 + const UINT8* salpha_table = epic12_device_colrtable[s_alpha]; +#endif + +#endif + +#if _SMODE == 2 +#if _DMODE == 0 + + const UINT8* dalpha_table = epic12_device_colrtable[d_alpha]; +#endif +#endif +#endif + + + + for (y = starty; y < dimy; y++) + { + //bmp = &bitmap->pix(dst_y_start + y, dst_x_start+startx); + bmp = m_bitmaps + (dst_y_start + y) * 0x2000 + (dst_x_start+startx); + + const int ysrc_index = ((src_y + yf * y) & 0x0fff) * 0x2000; + gfx2 = gfx + ysrc_index; + + #if FLIPX == 1 + gfx2 += (src_x-startx); + #else + gfx2 += (src_x+startx); + #endif + +#if 1 + const UINT32* end = bmp+(dimx-startx); +#else + // maybe we can do some SSE type optimizations on larger blocks? right now this just results in more code and slower compiling tho. + + const int width = dimx-startx; + const UINT32* end = bmp+(width); + + if (width<0) return; + + int bigblocks = width>>3; + + while (bigblocks) + { + #include "epic12pixel.inc" + #include "epic12pixel.inc" + #include "epic12pixel.inc" + #include "epic12pixel.inc" + #include "epic12pixel.inc" + #include "epic12pixel.inc" + #include "epic12pixel.inc" + #include "epic12pixel.inc" + + bigblocks--; + } +#endif + while (bmp> 3); // using the union is actually significantly slower than our pen_to_clr to function! + // source * intesity and clamp + +#if TINT == 1 + clr_mul(&s_clr.trgb, tint_clr); +#endif + + #if BLENDED == 1 + + // convert destination to clr + pen_to_clr(*bmp, &d_clr.trgb); + //d_clr.u32 = *bmp >> 3; // using the union is actually significantly slower than our pen_to_clr to function! + #if _SMODE == 0 + //g_profiler.start(PROFILER_USER7); + + + #if _DMODE == 0 + //g_profiler.start(PROFILER_USER1); + // this is used extensively in the games (ingame, futari title screens etc.) + + s_clr.trgb.r = epic12_device_colrtable_add[salpha_table[(s_clr.trgb.r)]][dalpha_table[(d_clr.trgb.r)]]; + s_clr.trgb.g = epic12_device_colrtable_add[salpha_table[(s_clr.trgb.g)]][dalpha_table[(d_clr.trgb.g)]]; + s_clr.trgb.b = epic12_device_colrtable_add[salpha_table[(s_clr.trgb.b)]][dalpha_table[(d_clr.trgb.b)]]; + #elif _DMODE == 1 + //g_profiler.start(PROFILER_USER2); + // futari ~7% + s_clr.trgb.r = epic12_device_colrtable_add[salpha_table[(s_clr.trgb.r)]][epic12_device_colrtable[(s_clr.trgb.r)][(d_clr.trgb.r)]]; + s_clr.trgb.g = epic12_device_colrtable_add[salpha_table[(s_clr.trgb.g)]][epic12_device_colrtable[(s_clr.trgb.g)][(d_clr.trgb.g)]]; + s_clr.trgb.b = epic12_device_colrtable_add[salpha_table[(s_clr.trgb.b)]][epic12_device_colrtable[(s_clr.trgb.b)][(d_clr.trgb.b)]]; + #elif _DMODE == 2 + //g_profiler.start(PROFILER_USER3); + clr_mul_fixed(&clr0.trgb, s_alpha, &s_clr.trgb); + clr_add_with_clr_square(&s_clr.trgb, &clr0.trgb, &d_clr.trgb); + #elif _DMODE == 3 + //g_profiler.start(PROFILER_USER4); + clr_mul_fixed(&clr0.trgb, s_alpha, &s_clr.trgb); + clr_add(&s_clr.trgb, &clr0.trgb, &d_clr.trgb); + + #elif _DMODE == 4 + //g_profiler.start(PROFILER_USER5); + clr_mul_fixed(&clr0.trgb, s_alpha, &s_clr.trgb); + clr_add_with_clr_mul_fixed_rev(&s_clr.trgb, &clr0.trgb, d_alpha, &d_clr.trgb); + #elif _DMODE == 5 + // futari black character select ~13% + //g_profiler.start(PROFILER_USER6); + s_clr.trgb.r = epic12_device_colrtable_add[salpha_table[(s_clr.trgb.r)]][epic12_device_colrtable_rev[(s_clr.trgb.r)][(d_clr.trgb.r)]]; + s_clr.trgb.g = epic12_device_colrtable_add[salpha_table[(s_clr.trgb.g)]][epic12_device_colrtable_rev[(s_clr.trgb.g)][(d_clr.trgb.g)]]; + s_clr.trgb.b = epic12_device_colrtable_add[salpha_table[(s_clr.trgb.b)]][epic12_device_colrtable_rev[(s_clr.trgb.b)][(d_clr.trgb.b)]]; + + #elif _DMODE == 6 + //g_profiler.start(PROFILER_USER7); + clr_mul_fixed(&clr0.trgb, s_alpha, &s_clr.trgb); + clr_add_with_clr_mul_rev_square(&s_clr.trgb, &clr0.trgb, &d_clr.trgb); + #elif _DMODE == 7 + //g_profiler.start(PROFILER_USER8); + clr_mul_fixed(&clr0.trgb, s_alpha, &s_clr.trgb); + clr_add(&s_clr.trgb, &clr0.trgb, &d_clr.trgb); + #endif + + //g_profiler.stop(); + #elif _SMODE == 1 + //g_profiler.start(PROFILER_USER6); + clr_square(&clr0.trgb, &s_clr.trgb); + + #elif _SMODE == 2 + // g_profiler.start(PROFILER_USER4); + #if _DMODE == 0 + // this is used heavily on espgal2 highscore screen (~28%) optimized to avoid use of temp clr0 variable + s_clr.trgb.r = epic12_device_colrtable_add[epic12_device_colrtable[(d_clr.trgb.r)][(s_clr.trgb.r)]][dalpha_table[(d_clr.trgb.r)]]; + s_clr.trgb.g = epic12_device_colrtable_add[epic12_device_colrtable[(d_clr.trgb.g)][(s_clr.trgb.g)]][dalpha_table[(d_clr.trgb.g)]]; + s_clr.trgb.b = epic12_device_colrtable_add[epic12_device_colrtable[(d_clr.trgb.b)][(s_clr.trgb.b)]][dalpha_table[(d_clr.trgb.b)]]; + #elif _DMODE == 1 + clr_mul_3param(&clr0.trgb, &s_clr.trgb, &d_clr.trgb); + clr_add_with_clr_mul_3param(&s_clr.trgb, &clr0.trgb, &d_clr.trgb, &s_clr.trgb); + #elif _DMODE == 2 + clr_mul_3param(&clr0.trgb, &s_clr.trgb, &d_clr.trgb); + clr_add_with_clr_square(&s_clr.trgb, &clr0.trgb, &d_clr.trgb); + #elif _DMODE == 3 + clr_mul_3param(&clr0.trgb, &s_clr.trgb, &d_clr.trgb); + clr_add(&s_clr.trgb, &clr0.trgb, &d_clr.trgb); + + #elif _DMODE == 4 + clr_mul_3param(&clr0.trgb, &s_clr.trgb, &d_clr.trgb); + clr_add_with_clr_mul_fixed_rev(&s_clr.trgb, &clr0.trgb, d_alpha, &d_clr.trgb); + #elif _DMODE == 5 + clr_mul_3param(&clr0.trgb, &s_clr.trgb, &d_clr.trgb); + clr_add_with_clr_mul_rev_3param(&s_clr.trgb, &clr0.trgb, &d_clr.trgb, &s_clr.trgb); + #elif _DMODE == 6 + clr_mul_3param(&clr0.trgb, &s_clr.trgb, &d_clr.trgb); + clr_add_with_clr_mul_rev_square(&s_clr.trgb, &clr0.trgb, &d_clr.trgb); + #elif _DMODE == 7 + clr_mul_3param(&clr0.trgb, &s_clr.trgb, &d_clr.trgb); + clr_add(&s_clr.trgb, &clr0.trgb, &d_clr.trgb); + #endif + //g_profiler.stop(); + + #elif _SMODE == 3 + //g_profiler.start(PROFILER_USER1); + clr_copy(&clr0.trgb, &s_clr.trgb); + + #elif _SMODE == 4 + //g_profiler.start(PROFILER_USER2); + clr_mul_fixed_rev(&clr0.trgb, s_alpha, &s_clr.trgb); + #elif _SMODE == 5 + //g_profiler.start(PROFILER_USER3); + clr_mul_rev_square(&clr0.trgb, &s_clr.trgb); + #elif _SMODE == 6 + //g_profiler.start(PROFILER_USER4); + clr_mul_rev_3param(&clr0.trgb, &s_clr.trgb, &d_clr.trgb); + #elif _SMODE == 7 + //g_profiler.start(PROFILER_USER5); + clr_copy(&clr0.trgb, &s_clr.trgb); + #endif + + +// smode 0/2 cases are already split up and handled above. +#if _SMODE != 2 +#if _SMODE != 0 + + #if _DMODE == 0 + clr_add_with_clr_mul_fixed(&s_clr.trgb, &clr0.trgb, d_alpha, &d_clr.trgb); + #elif _DMODE == 1 + clr_add_with_clr_mul_3param(&s_clr.trgb, &clr0.trgb, &d_clr.trgb, &s_clr.trgb); + #elif _DMODE == 2 + clr_add_with_clr_square(&s_clr.trgb, &clr0.trgb, &d_clr.trgb); + #elif _DMODE == 3 + clr_add(&s_clr.trgb, &clr0.trgb, &d_clr.trgb); + + #elif _DMODE == 4 + clr_add_with_clr_mul_fixed_rev(&s_clr.trgb, &clr0.trgb, d_alpha, &d_clr.trgb); + #elif _DMODE == 5 + clr_add_with_clr_mul_rev_3param(&s_clr.trgb, &clr0.trgb, &d_clr.trgb, &s_clr.trgb); + #elif _DMODE == 6 + clr_add_with_clr_mul_rev_square(&s_clr.trgb, &clr0.trgb, &d_clr.trgb); + #elif _DMODE == 7 + clr_add(&s_clr.trgb, &clr0.trgb, &d_clr.trgb); + #endif + + //g_profiler.stop(); +#endif +#endif + + + #endif + + // write result + *bmp = clr_to_pen(&s_clr.trgb)|(pen&0x20000000); + //*bmp = (s_clr.u32<<3)|(pen&0x20000000); // using the union is actually significantly slower than our clr_to_pen function! + +#endif // END NOT REALLY SIMPLE + +#if TRANSPARENT == 1 + } +#endif + LOOP_INCREMENTS diff --git a/src/burn/devices/thready.h b/src/burn/devices/thready.h new file mode 100644 index 000000000..e01af7789 --- /dev/null +++ b/src/burn/devices/thready.h @@ -0,0 +1,223 @@ +// thready spent most of the 1900's in a little old lady's sewing basket.. +// thready had big dreams, this is one of them! - dink 2022 + +#define THREADY_WINDOWS 1 // we're on Windows +#define THREADY_PTHREAD 2 // anything that supports pthreads (linux, android, mac) +#define THREADY_0THREAD 3 // neither of the above.. (no threading!) + +#if defined(WIN32) +#define THREADY THREADY_WINDOWS +#include "windows.h" +#endif + +#if !defined(WIN32) && ( defined(__linux__) || defined(__ANDROID__) || defined(__APPLE__) ) +#define THREADY THREADY_PTHREAD +#include +#include +#include +#endif + +#ifndef THREADY +// system not windows and without pthreads +#define THREADY THREADY_0THREAD +#endif + +#if (THREADY == THREADY_WINDOWS) +long unsigned int __stdcall ThreadyProc(void*); + +struct threadystruct +{ + INT32 thready_ok; + INT32 ok_to_thread; + INT32 end_thread; + HANDLE our_thread; + HANDLE our_event; + DWORD our_threadid; + void (*our_callback)(); + + void init(void (*thread_callback)()) { + thready_ok = 0; + ok_to_thread = 0; + + our_callback = thread_callback; + + SYSTEM_INFO info; + GetSystemInfo(&info); + INT32 maxproc = (info.dwNumberOfProcessors > 4) ? 4 : info.dwNumberOfProcessors; + INT32 thready_proc = rand() % maxproc; + + //bprintf(0, _T("Thready: processors available: %d, blitter processor: %d\n"), info.dwNumberOfProcessors, thready_proc); + + end_thread = 0; // good to go! + + our_event = CreateEvent(NULL, TRUE, FALSE, TEXT("blitEvent")); + our_thread = CreateThread(NULL, 0, ThreadyProc, NULL, 0, &our_threadid); + + SetThreadIdealProcessor(our_thread, thready_proc); + + if (our_event && our_thread) { + //bprintf(0, _T("Thready: we're gonna git 'r dun!\n")); + thready_ok = 1; + ok_to_thread = 1; + } else { + //bprintf(0, _T("Thready: failure to create thread!\n")); + } + } + + void exit() { + if (thready_ok) { + //bprintf(0, _T("Thready: notify thread to exit..\n")); + end_thread = 1; + SetEvent(our_event); + do { + Sleep(42); // let thread realize it's time to die + } while (~end_thread & 0x100); + CloseHandle(our_event); + CloseHandle(our_thread); + thready_ok = 0; + } + } + + void set_threading(INT32 value) + { + ok_to_thread = value; + } + + void notify() { + if (thready_ok && ok_to_thread) { + SetEvent(our_event); + } else { + // fallback to single-threaded mode + our_callback(); + } + } +}; + +static threadystruct thready; + +long unsigned int __stdcall ThreadyProc(void*) { + do { + DWORD dwWaitResult = WaitForSingleObject(thready.our_event, INFINITE); + + if (dwWaitResult == WAIT_OBJECT_0 && thready.end_thread == 0) { + thready.our_callback(); + ResetEvent(thready.our_event); + } else { + thready.end_thread |= 0x100; + //bprintf(0, _T("Thready: thread-event thread ending..\n")); + return 0; + } + } while (1); + + return 0; +} +#endif // THREADY_WINDOWS + +#if (THREADY == THREADY_PTHREAD) +static void *ThreadyProc(void*); + +struct threadystruct +{ + INT32 thready_ok; + INT32 ok_to_thread; + INT32 end_thread; + sem_t our_event; + pthread_t our_thread; + void (*our_callback)(); + + void init(void (*thread_callback)()) { + thready_ok = 0; + ok_to_thread = 0; + end_thread = 0; + + our_callback = thread_callback; + + INT32 our_event_rv = sem_init(&our_event, 0, 0); + INT32 our_thread_rv = pthread_create(&our_thread, NULL, ThreadyProc, NULL); + + if (our_thread_rv == 0 && our_event_rv == 0) { + //bprintf(0, _T("Thready: we're gonna git 'r dun!\n")); + thready_ok = 1; + ok_to_thread = 1; + } else { + //bprintf(0, _T("Thready: failure to create thread - falling back to single-thread mode!\n")); + } + } + + void exit() { + if (thready_ok) { + //bprintf(0, _T("Thready: notify thread to exit..\n")); + end_thread = 1; + sem_post(&our_event); + do { + sleep(1); // let thread realize it's time to die + } while (~end_thread & 0x100); + pthread_join(our_thread, NULL); + sem_destroy(&our_event); + thready_ok = 0; + } + } + + void set_threading(INT32 value) + { + ok_to_thread = value; + } + + void notify() { + if (thready_ok && ok_to_thread) { + sem_post(&our_event); + } else { + // fallback to single-threaded mode + our_callback(); + } + } +}; + +static threadystruct thready; + +static void *ThreadyProc(void*) { + do { + sem_wait(&thready.our_event); + + if (thready.end_thread == 0) { + thready.our_callback(); + } else { + thready.end_thread |= 0x100; + //bprintf(0, _T("Thready: thread-event thread ending..\n")); + return 0; + } + } while (1); + + return 0; +} +#endif // THREADY_PTHREAD + +#if (THREADY == THREADY_0THREAD) +// this isn't great +struct threadystruct +{ + void (*our_callback)(); + + void init(void (*thread_callback)()) { + our_callback = thread_callback; + + bprintf(0, _T("Thready: single-threaded on this platform, performance will suck.\n")); + } + + void exit() { + } + + void set_threading(INT32 value) + { + if (value) + bprintf(0, _T("Thready: we can't thread on this platform yet.\n")); + } + + void notify() { + // fallback to single-threaded mode + our_callback(); + } +}; + +static threadystruct thready; +#endif // THREADY_0THREAD diff --git a/src/burn/drv/cave/d_cv1k.cpp b/src/burn/drv/cave/d_cv1k.cpp new file mode 100644 index 000000000..acbfd5105 --- /dev/null +++ b/src/burn/drv/cave/d_cv1k.cpp @@ -0,0 +1,1322 @@ +// FinalBurn Neo Cave-1000 System driver module +// Based on MAME driver by David Haywood, Luca Elia, MetalliC +// +// notes / to-fix: +// support cpu rate change for non-multiples of (12800000 * 2) without +// breaking music. + +#include "tiles_generic.h" +#include "sh4_intf.h" +#include "sh3comn.h" +#include "epic12.h" +#include "serflash.h" +#include "rtc9701.h" +#include "ymz770.h" + +#define SH3_CLOCK (12800000 * 8) + +static UINT8 *AllMem; +static UINT8 *AllRam; +static UINT8 *RamEnd; +static UINT8 *MemEnd; + +static UINT8 *DrvMainROM; +static UINT8 *DrvFlashROM; +static UINT8 *DrvSoundROM; + +static UINT8 *DrvMainRAM; +static UINT8 *DrvCacheRAM; + +static UINT8 DrvRecalc; + +static INT32 nExtraCycles[1]; + +static UINT8 DrvJoy1[8]; +static UINT8 DrvJoy2[8]; +static UINT8 DrvJoy3[8]; +static UINT8 DrvJoy4[8]; +static UINT8 DrvDips[3]; +static UINT8 DrvInputs[5]; +static UINT8 DrvReset; + +// cpu speed changing +static INT32 DriverClock; // selected cpu clockrate +static INT32 nPrevBurnCPUSpeedAdjust; +static INT32 speedhack_burn; // 10ms @ cpu clock, calculated in DrvFrame + +static struct BurnInputInfo Cv1kInputList[] = { + {"P1 Coin", BIT_DIGITAL, DrvJoy1 + 2, "p1 coin" }, + {"P1 Start", BIT_DIGITAL, DrvJoy1 + 4, "p1 start" }, + {"P1 Up", BIT_DIGITAL, DrvJoy2 + 0, "p1 up" }, + {"P1 Down", BIT_DIGITAL, DrvJoy2 + 1, "p1 down" }, + {"P1 Left", BIT_DIGITAL, DrvJoy2 + 2, "p1 left" }, + {"P1 Right", BIT_DIGITAL, DrvJoy2 + 3, "p1 right" }, + {"P1 Button 1", BIT_DIGITAL, DrvJoy2 + 4, "p1 fire 1" }, + {"P1 Button 2", BIT_DIGITAL, DrvJoy2 + 5, "p1 fire 2" }, + {"P1 Button 3", BIT_DIGITAL, DrvJoy2 + 6, "p1 fire 3" }, + {"P1 Button 4", BIT_DIGITAL, DrvJoy2 + 7, "p1 fire 4" }, + + {"P2 Coin", BIT_DIGITAL, DrvJoy1 + 3, "p2 coin" }, + {"P2 Start", BIT_DIGITAL, DrvJoy1 + 5, "p2 start" }, + {"P2 Up", BIT_DIGITAL, DrvJoy4 + 0, "p2 up" }, + {"P2 Down", BIT_DIGITAL, DrvJoy4 + 1, "p2 down" }, + {"P2 Left", BIT_DIGITAL, DrvJoy4 + 2, "p2 left" }, + {"P2 Right", BIT_DIGITAL, DrvJoy4 + 3, "p2 right" }, + {"P2 Button 1", BIT_DIGITAL, DrvJoy4 + 4, "p2 fire 1" }, + {"P2 Button 2", BIT_DIGITAL, DrvJoy4 + 5, "p2 fire 2" }, + {"P2 Button 3", BIT_DIGITAL, DrvJoy4 + 6, "p2 fire 3" }, + {"P2 Button 4", BIT_DIGITAL, DrvJoy4 + 7, "p2 fire 4" }, + + {"Reset", BIT_DIGITAL, &DrvReset, "reset" }, + {"Service", BIT_DIGITAL, DrvJoy1 + 0, "service" }, + {"S3 Test (Jamma)", BIT_DIGITAL, DrvJoy1 + 1, "service2" }, + {"S3 Test", BIT_DIGITAL, DrvJoy3 + 1, "diag" }, + {"Dip A", BIT_DIPSWITCH, DrvDips + 0, "dip" }, + {"Dip B", BIT_DIPSWITCH, DrvDips + 1, "dip" }, + {"Dip C", BIT_DIPSWITCH, DrvDips + 2, "dip" }, +}; + +STDINPUTINFO(Cv1k) + +static struct BurnDIPInfo DefaultDIPList[]= +{ + {0 , 0xfe, 0 , 2, "Thread Blitter"}, + {0x01, 0x01, 0x01, 0x00, "Off" }, + {0x01, 0x01, 0x01, 0x01, "On" }, + + {0 , 0xfe, 0 , 2, "Speed Hacks" }, + {0x01, 0x01, 0x02, 0x00, "Off" }, + {0x01, 0x01, 0x02, 0x02, "On" }, + + {0 , 0xfe, 0 , 0x20, "Blitter Delay"}, + {0x02, 0x01, 0x1f, 0x00, "Off" }, + {0x02, 0x01, 0x1f, 0x01, "50" }, + {0x02, 0x01, 0x1f, 0x02, "51" }, + {0x02, 0x01, 0x1f, 0x03, "52" }, + {0x02, 0x01, 0x1f, 0x04, "53" }, + {0x02, 0x01, 0x1f, 0x05, "54" }, + {0x02, 0x01, 0x1f, 0x06, "55" }, + {0x02, 0x01, 0x1f, 0x07, "56" }, + {0x02, 0x01, 0x1f, 0x08, "57" }, + {0x02, 0x01, 0x1f, 0x09, "58" }, + {0x02, 0x01, 0x1f, 0x0a, "59" }, + {0x02, 0x01, 0x1f, 0x0b, "60" }, + {0x02, 0x01, 0x1f, 0x0c, "61" }, + {0x02, 0x01, 0x1f, 0x0d, "62" }, + {0x02, 0x01, 0x1f, 0x0e, "63" }, + {0x02, 0x01, 0x1f, 0x0f, "64" }, + {0x02, 0x01, 0x1f, 0x10, "65" }, + {0x02, 0x01, 0x1f, 0x11, "66" }, + {0x02, 0x01, 0x1f, 0x12, "67" }, + {0x02, 0x01, 0x1f, 0x13, "68" }, + {0x02, 0x01, 0x1f, 0x14, "69" }, + {0x02, 0x01, 0x1f, 0x15, "70" }, + {0x02, 0x01, 0x1f, 0x16, "71" }, + {0x02, 0x01, 0x1f, 0x17, "72" }, + {0x02, 0x01, 0x1f, 0x18, "73" }, + {0x02, 0x01, 0x1f, 0x19, "74" }, + {0x02, 0x01, 0x1f, 0x1a, "75" }, + {0x02, 0x01, 0x1f, 0x1b, "76" }, + {0x02, 0x01, 0x1f, 0x1c, "77" }, + {0x02, 0x01, 0x1f, 0x1d, "78" }, + {0x02, 0x01, 0x1f, 0x1e, "79" }, + {0x02, 0x01, 0x1f, 0x1f, "80" }, +}; + +static struct BurnDIPInfo Cv1kDIPList[]= +{ + DIP_OFFSET(0x18) + {0x00, 0xff, 0xff, 0x00, NULL }, + {0x01, 0xff, 0xff, 0x03, NULL }, + {0x02, 0xff, 0xff, 0x00, NULL }, + + {0 , 0xfe, 0 , 2, "S2:1" }, + {0x00, 0x01, 0x01, 0x00, "Off" }, + {0x00, 0x01, 0x01, 0x01, "On" }, + + {0 , 0xfe, 0 , 2, "S2:2" }, + {0x00, 0x01, 0x02, 0x00, "Off" }, + {0x00, 0x01, 0x02, 0x02, "On" }, + + {0 , 0xfe, 0 , 2, "S2:3" }, + {0x00, 0x01, 0x04, 0x00, "Off" }, + {0x00, 0x01, 0x04, 0x04, "On" }, + + {0 , 0xfe, 0 , 2, "S2:4" }, + {0x00, 0x01, 0x08, 0x00, "Off" }, + {0x00, 0x01, 0x08, 0x08, "On" }, +}; + +static struct BurnDIPInfo Cv1ksDIPList[]= +{ + DIP_OFFSET(0x18) + {0x00, 0xff, 0xff, 0x00, NULL }, + {0x01, 0xff, 0xff, 0x03, NULL }, + {0x02, 0xff, 0xff, 0x00, NULL }, + + {0 , 0xfe, 0 , 2, "Service Mode" }, + {0x00, 0x01, 0x01, 0x00, "Off" }, + {0x00, 0x01, 0x01, 0x01, "On" }, + + {0 , 0xfe, 0 , 2, "Special Mode" }, + {0x00, 0x01, 0x02, 0x00, "Off" }, + {0x00, 0x01, 0x02, 0x02, "On" }, +}; + +STDDIPINFOEXT(Cv1k, Cv1k, Default) +STDDIPINFOEXT(Cv1ks, Cv1ks, Default) + +static void __fastcall main_write_long(UINT32 offset, UINT32 data) +{ + if ((offset & 0xffffff80) == 0x18000000) { // 0x18000000 - 0x18000057 + epic12_blitter_write(offset & 0xff, data); + return; + } + + if (offset > 0x03fffff) bprintf(0, _T("mwl %x %x\n"), offset, data); +} +static void __fastcall main_write_word(UINT32 offset, UINT16 data) +{ + if (offset > 0x03fffff) bprintf(0, _T("mww %x %x\n"), offset, data); +} +static void __fastcall main_write_byte(UINT32 offset, UINT8 data) +{ + if ((offset & 0xffffff80) == 0x18000000) { + epic12_blitter_write(offset & 0xff, data); + return; + } + + switch (offset) { + case 0x10000000: serflash_data_write(data); return; + case 0x10000001: serflash_cmd_write(data); return; + case 0x10000002: serflash_addr_write(data); return; + + case 0x10400000: case 0x10400001: case 0x10400002: case 0x10400003: + case 0x10400004: case 0x10400005: case 0x10400006: case 0x10400007: + ymz770_write(offset & 7, data); + return; + + + case 0x10c00001: { + rtc9701_write_bit(data & 1); + rtc9701_set_clock_line((data & 2) >> 1); + rtc9701_set_cs_line((~data & 4) >> 2); + return; + } + case 0x10c00002: /* ?? */ return; + case 0x10c00003: serflash_enab_write(data); return; + } + + if (offset > 0x03fffff) bprintf(0, _T("mwb %x %x\n"), offset, data); +} + +static UINT32 __fastcall main_read_long(UINT32 offset) +{ + if ((offset & 0xffffff80) == 0x18000000) { + return epic12_blitter_read(offset & 0xff); + } + + bprintf(0, _T("mrl %x\n"), offset); + + return 0; +} +static UINT16 __fastcall main_read_word(UINT32 offset) +{ + if ((offset & 0xffffff80) == 0x18000000) { + return epic12_blitter_read(offset & 0xff); + } + + bprintf(0, _T("mrw %x\n"), offset); + + return 0; +} +static UINT8 __fastcall main_read_byte(UINT32 offset) +{ + if ((offset & 0xffffff80) == 0x18000000) { + return epic12_blitter_read(offset & 0xff); + } + + switch (offset) { + case 0x10000000: return serflash_io_read(); + case 0x10000001: case 0x10000002: case 0x10000003: + case 0x10000004: case 0x10000005: case 0x10000006: + case 0x10000007: return 0xff; + + case 0x10c00001: return (rtc9701_read_bit() & 1) | 0xfe; + } + + bprintf(0, _T("mrb %x\n"), offset); + + return 0; +} + +static UINT32 __fastcall main_read_port(UINT32 offset) +{ + //bprintf(0, _T("before_mrp %x\n"), offset); + switch (offset & ~7) { + case SH3_PORT_C: return DrvInputs[0]; + case SH3_PORT_D: return DrvInputs[1]; + case SH3_PORT_E: return 0xdf | 0x20; // flash ready + case SH3_PORT_F: return DrvInputs[2]; + case SH3_PORT_L: return DrvInputs[3]; + case SH3_PORT_J: return 0xff; // blitter(?) + } + + bprintf(0, _T("mrp %x\n"), offset); + return 0; +} +static void __fastcall main_write_port(UINT32 offset, UINT32 data) +{ + switch (offset & ~7) { + case SH3_PORT_E: return; // "not, sure" + case SH3_PORT_J: return; // blitter(?) + } + + bprintf(0, _T("mwp %x, %x\n"), offset, data); +} + +// hacky speedhack handler +static UINT32 hacky_idle_ram; +static UINT32 hacky_idle_pc; + +static UINT32 __fastcall speedhack_read_long(UINT32 offset) +{ + UINT32 pc = Sh3GetPC(-1); + if ( offset == hacky_idle_ram && (pc == hacky_idle_pc || pc == hacky_idle_pc+2)) { + //bprintf(0, _T("l")); + Sh3BurnCycles(speedhack_burn); + } + UINT32 V = *((UINT32 *)(DrvMainRAM + (offset & 0xfffffc))); + V = (V << 16) | (V >> 16); + return V; +} + +static UINT16 __fastcall speedhack_read_word(UINT32 offset) +{ + UINT32 pc = Sh3GetPC(-1); + if ( offset == hacky_idle_ram && (pc == hacky_idle_pc || pc == hacky_idle_pc+2)) { + //bprintf(0, _T("w")); + Sh3BurnCycles(speedhack_burn); + } + return *((UINT16 *)(DrvMainRAM + (offset & 0xfffffe))); +} + +static UINT8 __fastcall speedhack_read_byte(UINT32 offset) +{ + UINT32 pc = Sh3GetPC(-1); + if ( offset == hacky_idle_ram && (pc == hacky_idle_pc || pc == hacky_idle_pc+2)) { + //bprintf(0, _T("b")); + Sh3BurnCycles(speedhack_burn); + } + return DrvMainRAM[(offset & 0xffffff) ^ 1]; +} + +static void speedhack_set(UINT32 ram, UINT32 pc) +{ + hacky_idle_ram = ram; + hacky_idle_pc = pc; + + Sh3MapHandler(1, 0xc000000, 0xc00ffff, MAP_READ); + Sh3SetReadByteHandler (1, speedhack_read_byte); + Sh3SetReadWordHandler (1, speedhack_read_word); + Sh3SetReadLongHandler (1, speedhack_read_long); +} + +static INT32 DrvDoReset() +{ + memset (AllRam, 0, RamEnd - AllRam); + + Sh3Open(0); + Sh3Reset(); + Sh3Close(); + + epic12_reset(); + serflash_reset(); + rtc9701_reset(); + ymz770_reset(); + + nExtraCycles[0] = 0; + + nPrevBurnCPUSpeedAdjust = -1; + + return 0; +} + +static INT32 MemIndex() +{ + UINT8 *Next; Next = AllMem; + + DrvMainROM = Next; Next += 0x0400100; // +0x100 overdump crud + DrvFlashROM = Next; Next += 0x8400000; + DrvSoundROM = Next; Next += 0x0800100; // +0x100 overdump crud + + AllRam = Next; + + DrvMainRAM = Next; Next += 0x1000000; + DrvCacheRAM = Next; Next += 0x1000000; + + RamEnd = Next; + + MemEnd = Next; + + return 0; +} + +static INT32 DrvLoadRoms(INT32 &type_d) +{ + struct BurnRomInfo ri; + BurnDrvGetRomInfo(&ri, 0); + + if (BurnLoadRom(DrvMainROM, 0, 1)) return 1; + if (ri.nLen == 0x200000) memcpy (DrvMainROM + 0x200000, DrvMainROM, 0x200000); + if (ri.nLen >= 0x400000) type_d = 1; + + if (BurnLoadRom(DrvFlashROM, 1, 1)) return 1; + + if (BurnLoadRom(DrvSoundROM + 0x000000, 2, 1)) return 1; + if (BurnLoadRom(DrvSoundROM + 0x400000, 3, 1)) return 1; + BurnByteswap(DrvSoundROM, 0x800000); + + return 0; +} + +struct speedy_s { + char set[16][16]; + UINT32 pc; + UINT32 ram; +}; + +static speedy_s gamelist[] = { + { {"mushisam", "mushisamb", "\0", }, 0xc04a2aa, 0xc0024d8 }, + { {"ibara", "mushisama", "\0", }, 0xc04a0aa, 0xc0022f0 }, + { {"espgal2", "\0", }, 0xc05177a, 0xc002310 }, + { {"mushitam", "mushitama", "\0", }, 0xc04a0da, 0xc0022f0 }, + { {"ibarablk", "ibarablka", "\0", }, 0xc05176a, 0xc002310 }, + { {"futari15", "futari15a", "futari10", "\0", }, 0xc05176a, 0xc002310 }, + { {"futaribl", "futariblj", "mmpork", "\0", }, 0xc05176a, 0xc002310 }, + { {"pinkswts", "pinkswtsa", "pinkswtsb", + "pinkswtsx", "pinkswtssc", "\0", }, 0xc05176a, 0xc002310 }, + { {"deathsml", "\0", }, 0xc0519a2, 0xc002310 }, + { {"dsmbl", "ddpdfk", "ddpdfk10", "dfkbl", + "akatana", "ddpsdoj", "\0", }, 0xc1d1346, 0xc002310 }, + { {"\0", }, 0, 0 }, +}; + +static void init_speedhack() +{ + UINT32 hack_ram = 0; + UINT32 hack_pc = 0; + + for (INT32 i = 0; gamelist[i].pc != 0; i++) { + for (INT32 setnum = 0; gamelist[i].set[setnum][0] != '\0'; setnum++) { + if (!strcmp(BurnDrvGetTextA(DRV_NAME), gamelist[i].set[setnum])) { + bprintf(0, _T("*** found speedhack for %S\n"),gamelist[i].set[setnum]); + hack_ram = gamelist[i].ram; + hack_pc = gamelist[i].pc; + break; + } + } + } + + if (hack_ram && hack_pc) { + bprintf(0, _T("hack_ram: %x hack_pc: %x\n"), hack_ram, hack_pc); + } else { + bprintf(0, _T("*** UHOH! Speedhack not found! ***\n")); + } + + speedhack_set(hack_ram, hack_pc); +} + +static INT32 DrvInit() +{ + INT32 is_type_d = 0; + + BurnAllocMemIndex(); + GenericTilesInit(); + + if (DrvLoadRoms(is_type_d)) { return 1; } + + Sh3Init(0, SH3_CLOCK, 0, 0, 0, 0, 0, 1, 0, 1, 0); + Sh3Open(0); + + Sh3MapMemory(DrvMainROM, 0x0000000, 0x03fffff, MAP_ROM); + if (is_type_d == 0) { + Sh3MapMemory(DrvMainRAM, 0xc000000, 0xc7fffff, MAP_RAM); + Sh3MapMemory(DrvMainRAM, 0xc800000, 0xcffffff, MAP_RAM); + } else { + Sh3MapMemory(DrvMainRAM, 0xc000000, 0xcffffff, MAP_RAM); + } + Sh3MapMemory(DrvCacheRAM, 0xf0000000, 0xf0ffffff, MAP_RAM); + + Sh3SetReadByteHandler (0, main_read_byte); + Sh3SetReadWordHandler (0, main_read_word); + Sh3SetReadLongHandler (0, main_read_long); + Sh3SetWriteByteHandler(0, main_write_byte); + Sh3SetWriteWordHandler(0, main_write_word); + Sh3SetWriteLongHandler(0, main_write_long); + + Sh3SetReadPortHandler(main_read_port); + Sh3SetWritePortHandler(main_write_port); + + init_speedhack(); // install the hacky speedhack handler + + Sh3Close(); + + epic12_init((is_type_d) ? 0x1000000 : 0x0800000, (UINT16*)DrvMainRAM, &DrvDips[0]); + serflash_init(DrvFlashROM, 0x8400000); + rtc9701_init(); + + ymz770_init(DrvSoundROM, 0x800000); + + ymz770_set_buffered(Sh3TotalCycles, SH3_CLOCK); + DrvDoReset(); + + return 0; +} + +static INT32 DrvExit() +{ + Sh3Exit(); + + epic12_exit(); + serflash_exit(); + rtc9701_exit(); + ymz770_exit(); + + BurnFreeMemIndex(); + GenericTilesExit(); + + return 0; +} + +static INT32 DrvDraw() +{ + epic12_draw_screen(); + + return 0; +} + +static INT32 DrvFrame() +{ + if (DrvReset) { + DrvDoReset(); + } + + // check if cpu rate changes here.. + if (nPrevBurnCPUSpeedAdjust != nBurnCPUSpeedAdjust) { + bprintf(0, _T("Setting CPU Clock selection.\n")); + nPrevBurnCPUSpeedAdjust = nBurnCPUSpeedAdjust; + + DriverClock = (INT32)((INT64)SH3_CLOCK * nBurnCPUSpeedAdjust / 256); + speedhack_burn = (double)((double)DriverClock / 1000000) * 10; + + Sh3SetClockCV1k(DriverClock); + ymz770_set_buffered(Sh3TotalCycles, DriverClock); + + bprintf(0, _T("Driver Clock %d\n"), DriverClock); + //bprintf(0, _T("speedhack_burn %x\n"), speedhack_burn); + } + // set blitter delay via dip setting + { + INT32 delay = DrvDips[2] & 0x1f; + + epic12_set_blitterdelay((delay) ? (delay + 50) : 0, speedhack_burn); + epic12_set_blitterthreading(DrvDips[1] & 1); + Sh3SetTimerGranularity(DrvDips[1] & 2); + } + + { + DrvInputs[0] = 0xff; + DrvInputs[1] = 0xff; + DrvInputs[2] = 0xff; + DrvInputs[3] = 0xff; + + for (INT32 i = 0; i < 8; i++) { + DrvInputs[0] ^= (DrvJoy1[i] & 1) << i; + DrvInputs[1] ^= (DrvJoy2[i] & 1) << i; + DrvInputs[2] ^= (DrvJoy3[i] & 1) << i; + DrvInputs[3] ^= (DrvJoy4[i] & 1) << i; + } + } + + Sh3NewFrame(); + + INT32 nInterleave = 240; + INT32 nCyclesTotal[1] = { DriverClock / 60 }; + INT32 nCyclesDone[1] = { nExtraCycles[0] }; + + Sh3Open(0); + + for (INT32 i = 0; i < nInterleave; i++) + { + CPU_RUN(0, Sh3); + } + + Sh3SetIRQLine(2, CPU_IRQSTATUS_HOLD); + + if (pBurnSoundOut) { + ymz770_update(pBurnSoundOut, nBurnSoundLen); + } + + nExtraCycles[0] = Sh3TotalCycles() - nCyclesTotal[0]; + + Sh3Close(); + + rtc9701_once_per_frame(); + + if (pBurnDraw) { + BurnDrvRedraw(); + } + + return 0; +} + +static INT32 DrvScan(INT32 nAction, INT32 *pnMin) +{ + if (pnMin) { + *pnMin = 0x029704; + } + + if (nAction & ACB_VOLATILE) { + ScanVar(AllRam, RamEnd - AllRam, "All RAM"); + } + + if (nAction & ACB_DRIVER_DATA) + { + Sh3Scan(nAction); + + ymz770_scan(nAction, pnMin); + epic12_scan(nAction, pnMin); + + SCAN_VAR(nExtraCycles); + } + + serflash_scan(nAction, pnMin); // writes back to flash (hiscores ddpdfk, etc) here + rtc9701_scan(nAction, pnMin); // eeprom (nvram) lives here + + return 0; +} + +// Mushihime-Sama (2004/10/12.MASTER VER.) + +static struct BurnRomInfo mushisamRomDesc[] = { + { "mushisam_u4", 0x0200000, 0x15321b30, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "mushisam_u2", 0x8400000, 0x4f0a842a, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x138e2050, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xe3d05c9f, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(mushisam) +STD_ROM_FN(mushisam) + +struct BurnDriver BurnDrvMushisam = { + "mushisam", NULL, NULL, NULL, "2004", + "Mushihime-Sama (2004/10/12.MASTER VER.)\0", NULL, "Cave (AMI license)", "CA011", + L"Mushihime-Sama\0\u866b\u59eb\u3055\u307e (2004/10/12.MASTER VER.)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, mushisamRomInfo, mushisamRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Mushihime-Sama (2004/10/12 MASTER VER.) + +static struct BurnRomInfo mushisamaRomDesc[] = { + { "mushisama_u4", 0x0200000, 0x0b5b30b2, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "mushisam_u2", 0x8400000, 0x4f0a842a, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x138e2050, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xe3d05c9f, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(mushisama) +STD_ROM_FN(mushisama) + +struct BurnDriver BurnDrvMushisama = { + "mushisama", "mushisam", NULL, NULL, "2004", + "Mushihime-Sama (2004/10/12 MASTER VER.)\0", NULL, "Cave (AMI license)", "CA011", + L"Mushihime-Sama\0\u866b\u59eb\u3055\u307e (2004/10/12 MASTER VER.)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_CLONE | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, mushisamaRomInfo, mushisamaRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Mushihime-Sama (2004/10/12 MASTER VER) + +static struct BurnRomInfo mushisambRomDesc[] = { + { "mushisamb_u4", 0x0200000, 0x9f1c7f51, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "mushisam_u2", 0x8400000, 0x4f0a842a, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x138e2050, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xe3d05c9f, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(mushisamb) +STD_ROM_FN(mushisamb) + +struct BurnDriver BurnDrvMushisamb = { + "mushisamb", "mushisam", NULL, NULL, "2004", + "Mushihime-Sama (2004/10/12 MASTER VER)\0", NULL, "Cave (AMI license)", "CA011", + L"Mushihime-Sama\0\u866b\u59eb\u3055\u307e (2004/10/12 MASTER VER)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_CLONE | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, mushisambRomInfo, mushisambRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Espgaluda II (2005/11/14 MASTER VER, newer CV1000-B PCB) + +static struct BurnRomInfo espgal2RomDesc[] = { + { "espgal2_u4", 0x0200000, 0x843608b8, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "u2", 0x8400000, 0x222f58c7, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0xb9a10c22, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xc76b1ec4, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(espgal2) +STD_ROM_FN(espgal2) + +struct BurnDriver BurnDrvEspgal2 = { + "espgal2", NULL, NULL, NULL, "2005", + "Espgaluda II (2005/11/14 MASTER VER, newer CV1000-B PCB)\0", NULL, "Cave (AMI license)", "CA013", + L"Espgaluda II\0\u30a8\u30b9\u30d7\u30ac\u30eb\u30fc\u30c0II (2005/11/14 MASTER VER, newer CV1000-B PCB)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, espgal2RomInfo, espgal2RomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Espgaluda II (2005/11/14 MASTER VER, original CV1000-B PCB) + +static struct BurnRomInfo espgal2aRomDesc[] = { + { "espgal2a_u4", 0x0200000, 0x09c908bb, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "u2", 0x8400000, 0x222f58c7, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0xb9a10c22, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xc76b1ec4, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(espgal2a) +STD_ROM_FN(espgal2a) + +struct BurnDriver BurnDrvEspgal2a = { + "espgal2a", "espgal2", NULL, NULL, "2005", + "Espgaluda II (2005/11/14 MASTER VER, original CV1000-B PCB)\0", NULL, "Cave (AMI license)", "CA013", + L"Espgaluda II\0\u30a8\u30b9\u30d7\u30ac\u30eb\u30fc\u30c0II (2005/11/14 MASTER VER, original CV1000-B PCB)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_CLONE | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, espgal2aRomInfo, espgal2aRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Puzzle! Mushihime-Tama (2005/09/09.MASTER VER) + +static struct BurnRomInfo mushitamRomDesc[] = { + { "mushitam_u4", 0x0200000, 0xc49eb6b1, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "mushitam_u2", 0x8400000, 0x8ba498ab, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x701a912a, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0x6feeb9a1, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(mushitam) +STD_ROM_FN(mushitam) + +struct BurnDriver BurnDrvMushitam = { + "mushitam", NULL, NULL, NULL, "2005", + "Puzzle! Mushihime-Tama (2005/09/09.MASTER VER)\0", NULL, "Cave (AMI license)", "CA???", + NULL, NULL, NULL, NULL, + BDF_GAME_WORKING, 2, HARDWARE_CAVE_CV1000, GBF_PUZZLE, 0, + NULL, mushitamRomInfo, mushitamRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 320, 240, 4, 3 +}; + + +// Puzzle! Mushihime-Tama (2005/09/09 MASTER VER) + +static struct BurnRomInfo mushitamaRomDesc[] = { + { "mushitama_u4", 0x0200000, 0x4a23e6c8, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "mushitam_u2", 0x8400000, 0x8ba498ab, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x701a912a, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0x6feeb9a1, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(mushitama) +STD_ROM_FN(mushitama) + +struct BurnDriver BurnDrvMushitama = { + "mushitama", "mushitam", NULL, NULL, "2005", + "Puzzle! Mushihime-Tama (2005/09/09 MASTER VER)\0", NULL, "Cave (AMI license)", "CA???", + NULL, NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_CLONE, 2, HARDWARE_CAVE_CV1000, GBF_PUZZLE, 0, + NULL, mushitamaRomInfo, mushitamaRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 320, 240, 4, 3 +}; + + +// Mushihime-Sama Futari Ver 1.5 (2006/12/8.MASTER VER. 1.54.) + +static struct BurnRomInfo futari15RomDesc[] = { + { "futari15_u4", 0x0200000, 0xe8c5f128, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "futari15_u2", 0x8400000, 0xb9eae1fc, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x39f1e1f4, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xc631a766, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(futari15) +STD_ROM_FN(futari15) + +struct BurnDriver BurnDrvFutari15 = { + "futari15", NULL, NULL, NULL, "2006", + "Mushihime-Sama Futari Ver 1.5 (2006/12/8.MASTER VER. 1.54.)\0", NULL, "Cave (AMI license)", "CA015", + L"Mushihime-Sama Futari Ver 1.5\0\u866b\u59eb\u3055\u307e\u3075\u305f\u308a Ver 1.5 (2006/12/8.MASTER VER. 1.54.)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, futari15RomInfo, futari15RomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Mushihime-Sama Futari Ver 1.5 (2006/12/8 MASTER VER 1.54) + +static struct BurnRomInfo futari15aRomDesc[] = { + { "futari15a_u4", 0x0200000, 0xa609cf89, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "futari15_u2", 0x8400000, 0xb9eae1fc, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x39f1e1f4, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xc631a766, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(futari15a) +STD_ROM_FN(futari15a) + +struct BurnDriver BurnDrvFutari15a = { + "futari15a", "futari15", NULL, NULL, "2006", + "Mushihime-Sama Futari Ver 1.5 (2006/12/8 MASTER VER 1.54)\0", NULL, "Cave (AMI license)", "CA015", + L"Mushihime-Sama Futari Ver 1.5\0\u866b\u59eb\u3055\u307e\u3075\u305f\u308a Ver 1.5 (2006/12/8 MASTER VER 1.54)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_CLONE | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, futari15aRomInfo, futari15aRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Mushihime-Sama Futari Ver 1.0 (2006/10/23 MASTER VER.) + +static struct BurnRomInfo futari10RomDesc[] = { + { "futari10_u4", 0x0200000, 0xb127dca7, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "futari10_u2", 0x8400000, 0x78ffcd0c, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x39f1e1f4, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xc631a766, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(futari10) +STD_ROM_FN(futari10) + +struct BurnDriver BurnDrvFutari10 = { + "futari10", "futari15", NULL, NULL, "2006", + "Mushihime-Sama Futari Ver 1.0 (2006/10/23 MASTER VER.)\0", NULL, "Cave (AMI license)", "CA015", + L"Mushihime-Sama Futari Ver 1.0\0\u866b\u59eb\u3055\u307e\u3075\u305f\u308a Ver 1.0 (2006/10/23 MASTER VER.)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_CLONE | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, futari10RomInfo, futari10RomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Mushihime-Sama Futari Black Label - Another Ver (2009/11/27 INTERNATIONAL BL) + +static struct BurnRomInfo futariblRomDesc[] = { + { "futaribli_u4", 0x0200000, 0x1971dd16, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "futariblk_u2", 0x8400000, 0x08c6fd62, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x39f1e1f4, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xc631a766, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(futaribl) +STD_ROM_FN(futaribl) + +struct BurnDriver BurnDrvFutaribl = { + "futaribl", NULL, NULL, NULL, "2007", + "Mushihime-Sama Futari Black Label - Another Ver (2009/11/27 INTERNATIONAL BL)\0", NULL, "Cave (AMI license)", "CA015B", + NULL, NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, futariblRomInfo, futariblRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Mushihime-Sama Futari Black Label (2007/12/11 BLACK LABEL VER) + +static struct BurnRomInfo futaribljRomDesc[] = { + { "futariblk_u4", 0x0200000, 0xb9467b6d, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "futariblk_u2", 0x8400000, 0x08c6fd62, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x39f1e1f4, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xc631a766, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(futariblj) +STD_ROM_FN(futariblj) + +struct BurnDriver BurnDrvFutariblj = { + "futariblj", "futaribl", NULL, NULL, "2007", + "Mushihime-Sama Futari Black Label (2007/12/11 BLACK LABEL VER)\0", NULL, "Cave (AMI license)", "CA015B", + NULL, NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_CLONE | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, futaribljRomInfo, futaribljRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Ibara (2005/03/22 MASTER VER..) + +static struct BurnRomInfo ibaraRomDesc[] = { + { "u4", 0x0200000, 0x8e6c155d, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "u2", 0x8400000, 0x55840976, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0xee5e585d, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xf0aa3cb6, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(ibara) +STD_ROM_FN(ibara) + +struct BurnDriver BurnDrvIbara = { + "ibara", NULL, NULL, NULL, "2005", + "Ibara (2005/03/22 MASTER VER..)\0", NULL, "Cave (AMI license)", "CA012", + L"Ibara\0\u92f3\u8594\u8587 (2005/03/22 MASTER VER..)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, ibaraRomInfo, ibaraRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1ksDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Ibara Kuro Black Label (2006/02/06. MASTER VER.) + +static struct BurnRomInfo ibarablkRomDesc[] = { + { "ibarablk_u4", 0x0200000, 0xee1f1f77, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "ibarablk_u2", 0x8400000, 0x5e46be44, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0xa436bb22, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xd11ab6b6, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(ibarablk) +STD_ROM_FN(ibarablk) + +struct BurnDriver BurnDrvIbarablk = { + "ibarablk", NULL, NULL, NULL, "2006", + "Ibara Kuro Black Label (2006/02/06. MASTER VER.)\0", NULL, "Cave (AMI license)", "CA012B", + NULL, NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, ibarablkRomInfo, ibarablkRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1ksDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Ibara Kuro Black Label (2006/02/06 MASTER VER.) + +static struct BurnRomInfo ibarablkaRomDesc[] = { + { "ibarablka_u4", 0x0200000, 0xa9d43839, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "ibarablka_u2", 0x8400000, 0x33400d96, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0xa436bb22, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xd11ab6b6, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(ibarablka) +STD_ROM_FN(ibarablka) + +struct BurnDriver BurnDrvIbarablka = { + "ibarablka", "ibarablk", NULL, NULL, "2006", + "Ibara Kuro Black Label (2006/02/06 MASTER VER.)\0", NULL, "Cave (AMI license)", "CA012B", + NULL, NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_CLONE | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, ibarablkaRomInfo, ibarablkaRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1ksDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Deathsmiles (2007/10/09 MASTER VER) + +static struct BurnRomInfo deathsmlRomDesc[] = { + { "u4", 0x0200000, 0x1a7b98bf, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "u2", 0x8400000, 0x59ef5d78, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0xaab718c8, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0x83881d84, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(deathsml) +STD_ROM_FN(deathsml) + +struct BurnDriver BurnDrvDeathsml = { + "deathsml", NULL, NULL, NULL, "2007", + "Deathsmiles (2007/10/09 MASTER VER)\0", NULL, "Cave (AMI license)", "CA017", + L"Deathsmiles\0\uc730\ub930\ub930\ua430\ueb30\uba30 (2007/10/09 MASTER VER)\0", NULL, NULL, NULL, + BDF_GAME_WORKING, 2, HARDWARE_CAVE_CV1000, GBF_HORSHOOT, 0, + NULL, deathsmlRomInfo, deathsmlRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 320, 240, 4, 3 +}; + + +// Muchi Muchi Pork! (2007/ 4/17 MASTER VER.) + +static struct BurnRomInfo mmporkRomDesc[] = { + { "u4", 0x0200000, 0xd06cfa42, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "u2", 0x8400000, 0x1ee961b8, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x4a4b36df, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xce83d07b, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(mmpork) +STD_ROM_FN(mmpork) + +struct BurnDriver BurnDrvMmpork = { + "mmpork", NULL, NULL, NULL, "2007", + "Muchi Muchi Pork! (2007/ 4/17 MASTER VER.)\0", NULL, "Cave (AMI license)", "CA016", + L"Muchi Muchi Pork!\0\u3080\u3061\u3080\u3061\u30dd\u30fc\u30af! (2007/ 4/17 MASTER VER.)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, mmporkRomInfo, mmporkRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1ksDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Medal Mahjong Moukari Bancho (2007/06/05 MASTER VER.) + +static struct BurnRomInfo mmmbancRomDesc[] = { + { "u4", 0x0200000, 0x5589d8c6, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "u2", 0x8400000, 0x2e38965a, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x4caaa1bf, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0x8e3a51ba, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(mmmbanc) +STD_ROM_FN(mmmbanc) + +struct BurnDriverD BurnDrvMmmbanc = { + "mmmbanc", NULL, NULL, NULL, "2007", + "Medal Mahjong Moukari Bancho (2007/06/05 MASTER VER.)\0", NULL, "Cave (AMI license)", "CMDL01", + NULL, NULL, NULL, NULL, + BDF_GAME_NOT_WORKING, 2, HARDWARE_CAVE_CV1000, GBF_MISC, 0, + NULL, mmmbancRomInfo, mmmbancRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 320, 240, 4, 3 +}; + + +// Pink Sweets: Ibara Sorekara (2006/04/06 MASTER VER....) + +static struct BurnRomInfo pinkswtsRomDesc[] = { + { "pinkswts_u4", 0x0200000, 0x5d812c9e, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "pinkswts_u2", 0x8400000, 0xa2fa5363, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x4b82d250, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xe93f0627, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(pinkswts) +STD_ROM_FN(pinkswts) + +struct BurnDriver BurnDrvPinkswts = { + "pinkswts", NULL, NULL, NULL, "2006", + "Pink Sweets: Ibara Sorekara (2006/04/06 MASTER VER....)\0", NULL, "Cave (AMI license)", "CA014", + L"Pink Sweets: Ibara Sorekara\0\u30d4\u30f3\u30af\u30b9\u30a6\u30a3\u30fc\u30c4 \uff5e\u92f3\u8594\u8587\u305d\u308c\u304b\u3089\uff5e (2006/04/06 MASTER VER....)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, pinkswtsRomInfo, pinkswtsRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1ksDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Pink Sweets: Ibara Sorekara (2006/04/06 MASTER VER...) + +static struct BurnRomInfo pinkswtsaRomDesc[] = { + { "pnkswtsa_u4", 0x0200000, 0xee3339b2, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "pnkswtsa_u2", 0x8400000, 0x829a862e, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x4b82d250, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xe93f0627, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(pinkswtsa) +STD_ROM_FN(pinkswtsa) + +struct BurnDriver BurnDrvPinkswtsa = { + "pinkswtsa", "pinkswts", NULL, NULL, "2006", + "Pink Sweets: Ibara Sorekara (2006/04/06 MASTER VER...)\0", NULL, "Cave (AMI license)", "CA014", + L"Pink Sweets: Ibara Sorekara\0\u30d4\u30f3\u30af\u30b9\u30a6\u30a3\u30fc\u30c4 \uff5e\u92f3\u8594\u8587\u305d\u308c\u304b\u3089\uff5e (2006/04/06 MASTER VER...)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_CLONE | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, pinkswtsaRomInfo, pinkswtsaRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1ksDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Pink Sweets: Ibara Sorekara (2006/04/06 MASTER VER.) + +static struct BurnRomInfo pinkswtsbRomDesc[] = { + { "pnkswtsb_u4", 0x0200000, 0x68bcc009, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "pnkswtsx_u2", 0x8400000, 0x91e4deb2, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x4b82d250, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xe93f0627, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(pinkswtsb) +STD_ROM_FN(pinkswtsb) + +struct BurnDriver BurnDrvPinkswtsb = { + "pinkswtsb", "pinkswts", NULL, NULL, "2006", + "Pink Sweets: Ibara Sorekara (2006/04/06 MASTER VER.)\0", NULL, "Cave (AMI license)", "CA014", + L"Pink Sweets: Ibara Sorekara\0\u30d4\u30f3\u30af\u30b9\u30a6\u30a3\u30fc\u30c4 \uff5e\u92f3\u8594\u8587\u305d\u308c\u304b\u3089\uff5e (2006/04/06 MASTER VER.)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_CLONE | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, pinkswtsbRomInfo, pinkswtsbRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1ksDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Pink Sweets: Ibara Sorekara (2006/xx/xx MASTER VER.) + +static struct BurnRomInfo pinkswtsxRomDesc[] = { + { "pnkswtsx_u4", 0x0200000, 0x8fe05bf0, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "pnkswtsx_u2", 0x8400000, 0x91e4deb2, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x4b82d250, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xe93f0627, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(pinkswtsx) +STD_ROM_FN(pinkswtsx) + +struct BurnDriver BurnDrvPinkswtsx = { + "pinkswtsx", "pinkswts", NULL, NULL, "2006", + "Pink Sweets: Ibara Sorekara (2006/xx/xx MASTER VER.)\0", NULL, "Cave (AMI license)", "CA014", + L"Pink Sweets: Ibara Sorekara\0\u30d4\u30f3\u30af\u30b9\u30a6\u30a3\u30fc\u30c4 \uff5e\u92f3\u8594\u8587\u305d\u308c\u304b\u3089\uff5e (2006/xx/xx MASTER VER.)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_CLONE | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, pinkswtsxRomInfo, pinkswtsxRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1ksDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Pink Sweets: Suicide Club (2017/10/31 SUICIDECLUB VER., bootleg) + +static struct BurnRomInfo pinkswtsscRomDesc[] = { + { "suicideclub.u4", 0x0200000, 0x5e03662f, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "suicideclub.u2", 0x8400000, 0x32324608, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x4b82d250, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xe93f0627, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(pinkswtssc) +STD_ROM_FN(pinkswtssc) + +struct BurnDriver BurnDrvPinkswtssc = { + "pinkswtssc", "pinkswts", NULL, NULL, "2017", + "Pink Sweets: Suicide Club (2017/10/31 SUICIDECLUB VER., bootleg)\0", NULL, "bootleg (Four Horsemen)", "CA014", + L"Pink Sweets: Suicide Club\0\u30d4\u30f3\u30af\u30b9\u30a6\u30a3\u30fc\u30c4 \uff5e\u92f3\u8594\u8587\u305d\u308c\u304b\u3089\uff5e (2017/10/31 SUICIDECLUB VER., bootleg)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_CLONE | BDF_BOOTLEG | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, pinkswtsscRomInfo, pinkswtsscRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1ksDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// DoDonPachi Dai-Fukkatsu Ver 1.5 (2008/06/23 MASTER VER 1.5) + +static struct BurnRomInfo ddpdfkRomDesc[] = { + { "ddpdfk_u4", 0x0400000, 0x9976d699, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "ddpdfk_u2", 0x8400000, 0x84a51a4f, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x27032cde, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xa6178c2c, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(ddpdfk) +STD_ROM_FN(ddpdfk) + +struct BurnDriver BurnDrvDdpdfk = { + "ddpdfk", NULL, NULL, NULL, "2008", + "DoDonPachi Dai-Fukkatsu Ver 1.5 (2008/06/23 MASTER VER 1.5)\0", NULL, "Cave (AMI license)", "CA019", + L"DoDonPachi Dai-Fukkatsu Ver 1.5\0\u6012\u9996\u9818\u8702 \u5927\u5fa9\u6d3b Ver 1.5 (2008/06/23 MASTER VER 1.5)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, ddpdfkRomInfo, ddpdfkRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// DoDonPachi Dai-Fukkatsu Ver 1.0 (2008/05/16 MASTER VER) + +static struct BurnRomInfo ddpdfk10RomDesc[] = { + { "ddpdfk10_u4", 0x0400000, 0xa3d650b2, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "ddpdfk10_u2", 0x8400000, 0xd349cb2a, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x27032cde, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0xa6178c2c, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(ddpdfk10) +STD_ROM_FN(ddpdfk10) + +struct BurnDriver BurnDrvDdpdfk10 = { + "ddpdfk10", "ddpdfk", NULL, NULL, "2008", + "DoDonPachi Dai-Fukkatsu Ver 1.0 (2008/05/16 MASTER VER)\0", NULL, "Cave (AMI license)", "CA019", + L"DoDonPachi Dai-Fukkatsu Ver 1.0\0\u6012\u9996\u9818\u8702 \u5927\u5fa9\u6d3b Ver 1.0 (2008/05/16 MASTER VER)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_CLONE | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, ddpdfk10RomInfo, ddpdfk10RomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Deathsmiles MegaBlack Label (2008/10/06 MEGABLACK LABEL VER) + +static struct BurnRomInfo dsmblRomDesc[] = { + { "u4", 0x0400000, 0x77fc5ad1, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "u2", 0x8400000, 0xd6b85b7a, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0xa9536a6a, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0x3b673326, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(dsmbl) +STD_ROM_FN(dsmbl) + +struct BurnDriver BurnDrvDsmbl = { + "dsmbl", NULL, NULL, NULL, "2008", + "Deathsmiles MegaBlack Label (2008/10/06 MEGABLACK LABEL VER)\0", NULL, "Cave (AMI license)", "CA017B", + NULL, NULL, NULL, NULL, + BDF_GAME_WORKING, 2, HARDWARE_CAVE_CV1000, GBF_HORSHOOT, 0, + NULL, dsmblRomInfo, dsmblRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// DoDonPachi Dai-Fukkatsu Black Label (2010/1/18 BLACK LABEL) + +static struct BurnRomInfo dfkblRomDesc[] = { + { "u4", 0x0400000, 0x8092ca9d, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "u2", 0x8400000, 0x29f9d73a, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x36d4093b, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0x31f9eb0a, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(dfkbl) +STD_ROM_FN(dfkbl) + +struct BurnDriver BurnDrvDfkbl = { + "dfkbl", NULL, NULL, NULL, "2010", + "DoDonPachi Dai-Fukkatsu Black Label (2010/1/18 BLACK LABEL)\0", NULL, "Cave", "CA019B", + L"DoDonPachi Dai-Fukkatsu Black Label\0\u6012\u9996\u9818\u8702 \u5927\u5fa9\u6d3b (2010/1/18 BLACK LABEL)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, dfkblRomInfo, dfkblRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// DoDonPachi SaiDaiOuJou (2012/ 4/20) + +static struct BurnRomInfo ddpsdojRomDesc[] = { + { "u4", 0x0400100, 0xe2a4411c, 2 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "u2", 0x8400000, 0x668e4cd6, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400100, 0xac94801c, 4 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400100, 0xf593045b, 4 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(ddpsdoj) +STD_ROM_FN(ddpsdoj) + +struct BurnDriver BurnDrvDdpsdoj = { + "ddpsdoj", NULL, NULL, NULL, "2012", + "DoDonPachi SaiDaiOuJou (2012/ 4/20)\0", NULL, "Cave", "CA???", + L"DoDonPachi SaiDaiOuJou\0\u6012\u9996\u9818\u8702 \u5927\u5fa9\u6d3b (2012/4/20)\0", NULL, NULL, NULL, + BDF_GAME_WORKING | BDF_ORIENTATION_VERTICAL, 2, HARDWARE_CAVE_CV1000, GBF_VERSHOOT, 0, + NULL, ddpsdojRomInfo, ddpsdojRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 240, 320, 3, 4 +}; + + +// Akai Katana (2010/ 8/13 MASTER VER.) + +static struct BurnRomInfo akatanaRomDesc[] = { + { "u4", 0x0400000, 0x613fd380, 1 | BRF_PRG | BRF_ESS }, // 0 SH3 Code + + { "u2", 0x8400000, 0x89a2e1a5, 2 | BRF_PRG | BRF_ESS }, // 1 Flash + + { "u23", 0x0400000, 0x34a67e24, 3 | BRF_SND }, // 2 YMZ770 Samples + { "u24", 0x0400000, 0x10760fed, 3 | BRF_SND }, // 3 +}; + +STD_ROM_PICK(akatana) +STD_ROM_FN(akatana) + +struct BurnDriver BurnDrvAkatana = { + "akatana", NULL, NULL, NULL, "2010", + "Akai Katana (2010/ 8/13 MASTER VER.)\0", NULL, "Cave", "CA021", + L"Akai Katana\0\u8d64\u3044\u5200 (2010/ 8/13 MASTER VER.)\0", NULL, NULL, NULL, + BDF_GAME_WORKING, 2, HARDWARE_CAVE_CV1000, GBF_HORSHOOT, 0, + NULL, akatanaRomInfo, akatanaRomName, NULL, NULL, NULL, NULL, Cv1kInputInfo, Cv1kDIPInfo, + DrvInit, DrvExit, DrvFrame, DrvDraw, DrvScan, &DrvRecalc, 0x10000, + 320, 240, 4, 3 +}; diff --git a/src/burner/statec.cpp b/src/burner/statec.cpp index 96cf04b0a..5980eb4e9 100644 --- a/src/burner/statec.cpp +++ b/src/burner/statec.cpp @@ -123,7 +123,7 @@ static INT32 __cdecl UncompLoadAcb(struct BurnArea* pba) // Compress a state using deflate INT32 BurnStateCompress(UINT8** pDef, INT32* pnDefLen, INT32 bAll) { - if ((BurnDrvGetHardwareCode() & 0xffff0000) == 0x06010000) { + if ((BurnDrvGetHardwareCode() & 0xffff0000) == HARDWARE_CAVE_CV1000) { // Systems with a huge amount of data can be defined here to // use this raw state handler. @@ -210,7 +210,7 @@ static INT32 __cdecl StateDecompressAcb(struct BurnArea* pba) INT32 BurnStateDecompress(UINT8* Def, INT32 nDefLen, INT32 bAll) { - if ((BurnDrvGetHardwareCode() & 0xffff0000) == 0x06010000) { + if ((BurnDrvGetHardwareCode() & 0xffff0000) == HARDWARE_CAVE_CV1000) { // Systems with a huge amount of data can be defined here to // use this raw state handler. pBufferUncomp = Def; diff --git a/src/cpu/sh4/sh3comn.h b/src/cpu/sh4/sh3comn.h new file mode 100644 index 000000000..f5212bb3c --- /dev/null +++ b/src/cpu/sh4/sh3comn.h @@ -0,0 +1,100 @@ +#pragma once + +#ifndef __SH3COMN_H__ +#define __SH3COMN_H__ + + +// actual port handling is more complex than this +// which should be considered a temporary solution +// just used some arbitrary port nubmers +#define SH3_PORT_A (0x10*8) +#define SH3_PORT_B (0x11*8) +#define SH3_PORT_C (0x12*8) +#define SH3_PORT_D (0x13*8) +#define SH3_PORT_E (0x14*8) +#define SH3_PORT_F (0x15*8) +#define SH3_PORT_G (0x16*8) +#define SH3_PORT_H (0x17*8) +/* no I */ +#define SH3_PORT_J (0x18*8) +#define SH3_PORT_K (0x19*8) +#define SH3_PORT_L (0x1a*8) + +/* SH3 lower area regs */ + +#define SH3_LOWER_REGBASE (0x04000000) +#define SH3_LOWER_REGEND (0x07ffffff) + +#define INTEVT2 ((0x4000000 - SH3_LOWER_REGBASE)/4) +#define IRR0_IRR1 ((0x4000004 - SH3_LOWER_REGBASE)/4) +#define PINTER_IPRC ((0x4000014 - SH3_LOWER_REGBASE)/4) + +#define SH3_SAR0_ADDR ((0x4000020 - SH3_LOWER_REGBASE)/4) +#define SH3_DAR0_ADDR ((0x4000024 - SH3_LOWER_REGBASE)/4) +#define SH3_DMATCR0_ADDR ((0x4000028 - SH3_LOWER_REGBASE)/4) +#define SH3_CHCR0_ADDR ((0x400002c - SH3_LOWER_REGBASE)/4) +#define SH3_SAR1_ADDR ((0x4000030 - SH3_LOWER_REGBASE)/4) +#define SH3_DAR1_ADDR ((0x4000034 - SH3_LOWER_REGBASE)/4) +#define SH3_DMATCR1_ADDR ((0x4000038 - SH3_LOWER_REGBASE)/4) +#define SH3_CHCR1_ADDR ((0x400003c - SH3_LOWER_REGBASE)/4) +#define SH3_SAR2_ADDR ((0x4000040 - SH3_LOWER_REGBASE)/4) +#define SH3_DAR2_ADDR ((0x4000044 - SH3_LOWER_REGBASE)/4) +#define SH3_DMATCR2_ADDR ((0x4000048 - SH3_LOWER_REGBASE)/4) +#define SH3_CHCR2_ADDR ((0x400004c - SH3_LOWER_REGBASE)/4) +#define SH3_SAR3_ADDR ((0x4000050 - SH3_LOWER_REGBASE)/4) +#define SH3_DAR3_ADDR ((0x4000054 - SH3_LOWER_REGBASE)/4) +#define SH3_DMATCR3_ADDR ((0x4000058 - SH3_LOWER_REGBASE)/4) +#define SH3_CHCR3_ADDR ((0x400005c - SH3_LOWER_REGBASE)/4) +#define SH3_DMAOR_ADDR ((0x4000060 - SH3_LOWER_REGBASE)/4) + + +#define PCCR_PDCR ((0x4000104 - SH3_LOWER_REGBASE)/4) +#define PECR_PFCR ((0x4000108 - SH3_LOWER_REGBASE)/4) +#define PGCR_PHCR ((0x400010c - SH3_LOWER_REGBASE)/4) +#define PJCR_PKCR ((0x4000110 - SH3_LOWER_REGBASE)/4) +#define PLCR_SCPCR ((0x4000114 - SH3_LOWER_REGBASE)/4) + +#define PADR_PBDR ((0x4000120 - SH3_LOWER_REGBASE)/4) +#define PCDR_PDDR ((0x4000124 - SH3_LOWER_REGBASE)/4) +#define PEDR_PFDR ((0x4000128 - SH3_LOWER_REGBASE)/4) +#define PGDR_PHDR ((0x400012c - SH3_LOWER_REGBASE)/4) +#define PJDR_PKDR ((0x4000130 - SH3_LOWER_REGBASE)/4) +#define PLDR_SCPDR ((0x4000134 - SH3_LOWER_REGBASE)/4) + +#define SCSMR2_SCBRR2 ((0x4000150 - SH3_LOWER_REGBASE)/4) +#define SCSCR2_SCFTDR2 ((0x4000154 - SH3_LOWER_REGBASE)/4) +#define SCSSR2_SCFRDR2 ((0x4000158 - SH3_LOWER_REGBASE)/4) +#define SCFCR2_SCFDR2 ((0x400015c - SH3_LOWER_REGBASE)/4) + + +/* SH3 upper area */ + + +#define SH3_UPPER_REGBASE (0xffffd000) +#define SH3_UPPER_REGEND (0xffffffff) + +#define SH3_ICR0_IPRA_ADDR ((0xfffffee0 - SH3_UPPER_REGBASE)/4) +#define SH3_IPRB_ADDR ((0xfffffee4 - SH3_UPPER_REGBASE)/4) + +#define SH3_TOCR_TSTR_ADDR ((0xfffffe90 - SH3_UPPER_REGBASE)/4) +#define SH3_TCOR0_ADDR ((0xfffffe94 - SH3_UPPER_REGBASE)/4) +#define SH3_TCNT0_ADDR ((0xfffffe98 - SH3_UPPER_REGBASE)/4) +#define SH3_TCR0_ADDR ((0xfffffe9c - SH3_UPPER_REGBASE)/4) +#define SH3_TCOR1_ADDR ((0xfffffea0 - SH3_UPPER_REGBASE)/4) +#define SH3_TCNT1_ADDR ((0xfffffea4 - SH3_UPPER_REGBASE)/4) +#define SH3_TCR1_ADDR ((0xfffffea8 - SH3_UPPER_REGBASE)/4) +#define SH3_TCOR2_ADDR ((0xfffffeac - SH3_UPPER_REGBASE)/4) +#define SH3_TCNT2_ADDR ((0xfffffeb0 - SH3_UPPER_REGBASE)/4) +#define SH3_TCR2_ADDR ((0xfffffeb4 - SH3_UPPER_REGBASE)/4) +#define SH3_TCPR2_ADDR ((0xfffffeb8 - SH3_UPPER_REGBASE)/4) +#define SH3_TRA_ADDR ((0xffffffd0 - SH3_UPPER_REGBASE)/4) +#define SH3_EXPEVT_ADDR ((0xffffffd4 - SH3_UPPER_REGBASE)/4) +#define SH3_INTEVT_ADDR ((0xffffffd8 - SH3_UPPER_REGBASE)/4) + +// dink +#define SH3_BSC_BCR12 ((0xffffff60 - SH3_UPPER_REGBASE)/4) +#define SH3_BSC_BCR3 ((0xffffff7e - SH3_UPPER_REGBASE)/4) +#define SH3_BSC_WCR12 ((0xffffff64 - SH3_UPPER_REGBASE)/4) +// dink + +#endif /* __SH3COMN_H__ */ diff --git a/src/cpu/sh4/sh3comn.inc b/src/cpu/sh4/sh3comn.inc new file mode 100644 index 000000000..749df6834 --- /dev/null +++ b/src/cpu/sh4/sh3comn.inc @@ -0,0 +1,732 @@ +/* Handlers for SH3 internals */ + +/*#include "emu.h" +#include "debugger.h" +#include "sh4.h" +#include "sh4comn.h" +#include "sh3comn.h" +#include "sh4tmu.h" +#include "sh4dmac.h" +*/ + +/* High internal area (ffffxxxx) */ + +static void sh3_internal_high_w(UINT32 offset, UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_sh3internal_upper[offset]); + + switch (offset) + { + case SH3_BSC_BCR12: + if (mem_mask & 0xffff0000) + { + logerror("'%s' (%08x): BCR1 internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - ICR0)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + logerror("'%s' (%08x): BCR2 internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - IPRA)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); + } + + break; + case SH3_BSC_BCR3: + if (mem_mask & 0xffff0000) + { + logerror("'%s' (%08x): BCR3h internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - ICR0)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + logerror("'%s' (%08x): BCR3l internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - IPRA)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); + } + + break; + case SH3_BSC_WCR12: + if (mem_mask & 0xffff0000) + { + logerror("'%s' (%08x): WCR1 internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - ICR0)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); + // cave-1000, area 0 (rom) and area 3 (ram) + const int WCR1_CYCLES[4] = { 1, 1, 2, 3 }; + for (INT32 i = 0; i < 7; i++) { + AreaWS1[i] = WCR1_CYCLES[(data >> (16+(i << 1))) & 3]; + //bprintf(0, _T("areaWS1[%d] = %d\n"), i, AreaWS1[i]); + } + } + + if (mem_mask & 0x0000ffff) + { + logerror("'%s' (%08x): WCR2 internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - IPRA)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); + // cave-1000, we only care about area 0 (rom) and area 3 (ram) + const int a3dram[4] = { 1, 1, 2, 3 }; + const int a0waitstates[8] = { 0, 1, 2, 3, 4, 6, 8, 10 }; + + AreaWS2[3] = a3dram[(data >> 5) & 3]; + AreaWS2[0] = a0waitstates[data & 7]; + + //logerror("Area 0 Wait States %d\n", AreaWS2[0]); + //logerror("Area 3 Wait States %d\n", AreaWS2[3]); + } + + break; + case SH3_ICR0_IPRA_ADDR: + if (mem_mask & 0xffff0000) + { + logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - ICR0)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - IPRA)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); + sh4_handler_ipra_w(data&0xffff,mem_mask&0xffff); + } + + break; + + case SH3_IPRB_ADDR: + logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_IPRB_ADDR)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); + break; + + case SH3_TOCR_TSTR_ADDR: + logerror("'%s' (%08x): TMU internal write to %08x = %08x & %08x (SH3_TOCR_TSTR_ADDR)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); + if (mem_mask&0xff000000) + { + sh4_handle_tocr_addr_w((data>>24)&0xffff, (mem_mask>>24)&0xff); + } + if (mem_mask&0x0000ff00) + { + sh4_handle_tstr_addr_w((data>>8)&0xff, (mem_mask>>8)&0xff); + } + if (mem_mask&0x00ff00ff) + { + fatalerror("SH3_TOCR_TSTR_ADDR unused bits accessed (write)\n", 0); + } + break; + case SH3_TCOR0_ADDR: sh4_handle_tcor0_addr_w(data, mem_mask);break; + case SH3_TCOR1_ADDR: sh4_handle_tcor1_addr_w(data, mem_mask);break; + case SH3_TCOR2_ADDR: sh4_handle_tcor2_addr_w(data, mem_mask);break; + case SH3_TCNT0_ADDR: sh4_handle_tcnt0_addr_w(data, mem_mask);break; + case SH3_TCNT1_ADDR: sh4_handle_tcnt1_addr_w(data, mem_mask);break; + case SH3_TCNT2_ADDR: sh4_handle_tcnt2_addr_w(data, mem_mask);break; + case SH3_TCR0_ADDR: sh4_handle_tcr0_addr_w(data>>16, mem_mask>>16);break; + case SH3_TCR1_ADDR: sh4_handle_tcr1_addr_w(data>>16, mem_mask>>16);break; + case SH3_TCR2_ADDR: sh4_handle_tcr2_addr_w(data>>16, mem_mask>>16);break; + case SH3_TCPR2_ADDR: sh4_handle_tcpr2_addr_w(data, mem_mask);break; + + default: + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (unk)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); + break; + + } + + + + +} + +static UINT32 sh3_internal_high_r(UINT32 offset, UINT32 mem_mask) +{ + UINT32 ret = 0; + + switch (offset) + { + case SH3_ICR0_IPRA_ADDR: + logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_ICR0_IPRA_ADDR - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]); + return (m_sh3internal_upper[offset] & 0xffff0000) | (m_SH4_IPRA & 0xffff); + + case SH3_IPRB_ADDR: + logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_IPRB_ADDR - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]); + return m_sh3internal_upper[offset]; + + case SH3_TOCR_TSTR_ADDR: + + if (mem_mask&0xff00000) + { + ret |= (sh4_handle_tocr_addr_r(mem_mask)&0xff)<<24; + } + if (mem_mask&0x0000ff00) + { + ret |= (sh4_handle_tstr_addr_r(mem_mask)&0xff)<<8; + } + if (mem_mask&0x00ff00ff) + { + fatalerror("SH3_TOCR_TSTR_ADDR unused bits accessed (read)\n", 0); + } + return ret; + case SH3_TCOR0_ADDR: return sh4_handle_tcor0_addr_r(mem_mask); + case SH3_TCOR1_ADDR: return sh4_handle_tcor1_addr_r(mem_mask); + case SH3_TCOR2_ADDR: return sh4_handle_tcor2_addr_r(mem_mask); + case SH3_TCNT0_ADDR: return sh4_handle_tcnt0_addr_r(mem_mask); + case SH3_TCNT1_ADDR: return sh4_handle_tcnt1_addr_r(mem_mask); + case SH3_TCNT2_ADDR: return sh4_handle_tcnt2_addr_r(mem_mask); + case SH3_TCR0_ADDR: return sh4_handle_tcr0_addr_r(mem_mask)<<16; + case SH3_TCR1_ADDR: return sh4_handle_tcr1_addr_r(mem_mask)<<16; + case SH3_TCR2_ADDR: return sh4_handle_tcr2_addr_r(mem_mask)<<16; + case SH3_TCPR2_ADDR: return sh4_handle_tcpr2_addr_r(mem_mask); + + + case SH3_TRA_ADDR: + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 TRA - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]); + return m_sh3internal_upper[offset]; + + case SH3_EXPEVT_ADDR: + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 EXPEVT - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]); + return m_sh3internal_upper[offset]; + + case SH3_INTEVT_ADDR: + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 INTEVT - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]); + fatalerror("INTEVT unsupported on SH3\n", 0); + // never executed + //return m_sh3internal_upper[offset]; + + + default: + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask); + return m_sh3internal_upper[offset]; + } +} + + +static UINT32 sh3_internal_r(UINT32 offset, UINT32 mem_mask) +{ + if (offset<0x1000) + { + switch (offset) + { + case SH3_SAR0_ADDR: return sh4_handle_sar0_addr_r(mem_mask); + case SH3_SAR1_ADDR: return sh4_handle_sar1_addr_r(mem_mask); + case SH3_SAR2_ADDR: return sh4_handle_sar2_addr_r(mem_mask); + case SH3_SAR3_ADDR: return sh4_handle_sar3_addr_r(mem_mask); + case SH3_DAR0_ADDR: return sh4_handle_dar0_addr_r(mem_mask); + case SH3_DAR1_ADDR: return sh4_handle_dar1_addr_r(mem_mask); + case SH3_DAR2_ADDR: return sh4_handle_dar2_addr_r(mem_mask); + case SH3_DAR3_ADDR: return sh4_handle_dar3_addr_r(mem_mask); + case SH3_DMATCR0_ADDR: return sh4_handle_dmatcr0_addr_r(mem_mask); + case SH3_DMATCR1_ADDR: return sh4_handle_dmatcr1_addr_r(mem_mask); + case SH3_DMATCR2_ADDR: return sh4_handle_dmatcr2_addr_r(mem_mask); + case SH3_DMATCR3_ADDR: return sh4_handle_dmatcr3_addr_r(mem_mask); + case SH3_CHCR0_ADDR: return sh4_handle_chcr0_addr_r(mem_mask); + case SH3_CHCR1_ADDR: return sh4_handle_chcr1_addr_r(mem_mask); + case SH3_CHCR2_ADDR: return sh4_handle_chcr2_addr_r(mem_mask); + case SH3_CHCR3_ADDR: return sh4_handle_chcr3_addr_r(mem_mask); + case SH3_DMAOR_ADDR: return sh4_handle_dmaor_addr_r(mem_mask)<<16; + + + case INTEVT2: + { + // logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (INTEVT2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; + } + + + case IRR0_IRR1: + { + { + if (mem_mask & 0xff000000) + { + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; + } + + if (mem_mask & 0x0000ff00) + { + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR1)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; + } + + fatalerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0/1 unused bits)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + } + } + + case PADR_PBDR: + { + if (mem_mask & 0xffff0000) + { + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PADR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + //return ReadPort(SH3_PORT_A)<<24; + return ReadPort(SH3_PORT_A)<<24; + } + + if (mem_mask & 0x0000ffff) + { + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PBDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return ReadPort(SH3_PORT_B)<<8; + } + } + break; + + case PCDR_PDDR: + { + if (mem_mask & 0xffff0000) + { + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PCDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return ReadPort(SH3_PORT_C)<<24; + } + + if (mem_mask & 0x0000ffff) + { + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PDDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return ReadPort(SH3_PORT_D)<<8; + } + } + break; + + case PEDR_PFDR: + { + if (mem_mask & 0xffff0000) + { + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PEDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return ReadPort(SH3_PORT_E)<<24; + } + + if (mem_mask & 0x0000ffff) + { + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PFDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return ReadPort(SH3_PORT_F)<<8; + } + } + break; + + case PGDR_PHDR: + { + if (mem_mask & 0xffff0000) + { + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PGDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return ReadPort(SH3_PORT_G)<<24; + } + + if (mem_mask & 0x0000ffff) + { + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PHDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return ReadPort(SH3_PORT_H)<<8; + } + } + break; + + case PJDR_PKDR: + { + if (mem_mask & 0xffff0000) + { + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PJDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return ReadPort(SH3_PORT_J)<<24; + } + + if (mem_mask & 0x0000ffff) + { + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PKDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return ReadPort(SH3_PORT_K)<<8; + } + } + break; + + case PLDR_SCPDR: + { + if (mem_mask & 0xffff0000) + { + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PLDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return ReadPort(SH3_PORT_L)<<24; + } + + if (mem_mask & 0x0000ffff) + { + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SCPDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + //return ReadPort(SH3_PORT_K)<<8; + } + } + break; + + + case SCSMR2_SCBRR2: + { + if (mem_mask & 0xff000000) + { + logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSMR2 - Serial Mode Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; + } + + if (mem_mask & 0x0000ff00) + { + logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCBRR2 - Bit Rate Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; + } + } + break; + + case SCSCR2_SCFTDR2: + { + if (mem_mask & 0xff000000) + { + logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSCR2 - Serial Control Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; + } + + if (mem_mask & 0x0000ff00) + { + logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; + } + } + break; + + case SCSSR2_SCFRDR2: + { + if (mem_mask & 0xffff0000) + { + logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSSR2 - Serial Status Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; + } + + if (mem_mask & 0x0000ff00) + { + logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; + } + } + break; + + case SCFCR2_SCFDR2: + { + if (mem_mask & 0xff000000) + { + logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFCR2 - Fifo Control Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; + } + + if (mem_mask & 0x0000ffff) + { + logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFDR2 - Fifo Data Count Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; + } + } + break; + + + default: + { + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n", + tag(), m_pc & AM, + (offset *4)+0x4000000, + mem_mask); + } + break; + + } + + } + else + { + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n", + tag(), m_pc & AM, + (offset *4)+0x4000000, + mem_mask); + } + + return 0; +} + +/* Lower internal area */ + +static void sh3_internal_w(UINT32 offset, UINT32 data, UINT32 mem_mask) +{ + if (offset<0x1000) + { + //UINT32 old = m_sh3internal_lower[offset]; + COMBINE_DATA(&m_sh3internal_lower[offset]); + + switch (offset) + { + case SH3_SAR0_ADDR: sh4_handle_sar0_addr_w(data,mem_mask); break; + case SH3_SAR1_ADDR: sh4_handle_sar1_addr_w(data,mem_mask); break; + case SH3_SAR2_ADDR: sh4_handle_sar2_addr_w(data,mem_mask); break; + case SH3_SAR3_ADDR: sh4_handle_sar3_addr_w(data,mem_mask); break; + case SH3_DAR0_ADDR: sh4_handle_dar0_addr_w(data,mem_mask); break; + case SH3_DAR1_ADDR: sh4_handle_dar1_addr_w(data,mem_mask); break; + case SH3_DAR2_ADDR: sh4_handle_dar2_addr_w(data,mem_mask); break; + case SH3_DAR3_ADDR: sh4_handle_dar3_addr_w(data,mem_mask); break; + case SH3_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(data,mem_mask); break; + case SH3_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(data,mem_mask); break; + case SH3_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(data,mem_mask); break; + case SH3_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(data,mem_mask); break; + case SH3_CHCR0_ADDR: sh4_handle_chcr0_addr_w(data,mem_mask); break; + case SH3_CHCR1_ADDR: sh4_handle_chcr1_addr_w(data,mem_mask); break; + case SH3_CHCR2_ADDR: sh4_handle_chcr2_addr_w(data,mem_mask); break; + case SH3_CHCR3_ADDR: sh4_handle_chcr3_addr_w(data,mem_mask); break; + case SH3_DMAOR_ADDR: sh4_handle_dmaor_addr_w(data>>16,mem_mask>>16); break; + + + case IRR0_IRR1: + { + { + if (mem_mask & 0xff000000) + { + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + // not sure if this is how we should clear lines in this core... + if (!(data & 0x01000000)) execute_set_input(0, CLEAR_LINE); + if (!(data & 0x02000000)) execute_set_input(1, CLEAR_LINE); + if (!(data & 0x04000000)) execute_set_input(2, CLEAR_LINE); + if (!(data & 0x08000000)) execute_set_input(3, CLEAR_LINE); + + } + if (mem_mask & 0x0000ff00) + { + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR1)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + if (mem_mask & 0x00ff00ff) + { + fatalerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0/1 unused bits)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + } + break; + + case PINTER_IPRC: + { + if (mem_mask & 0xffff0000) + { + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PINTER)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + data &= 0xffff; mem_mask &= 0xffff; + COMBINE_DATA(&m_SH4_IPRC); + logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (IPRC)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + m_exception_priority[SH4_INTC_IRL0] = INTPRI((m_SH4_IPRC & 0x000f)>>0, SH4_INTC_IRL0); + m_exception_priority[SH4_INTC_IRL1] = INTPRI((m_SH4_IPRC & 0x00f0)>>4, SH4_INTC_IRL1); + m_exception_priority[SH4_INTC_IRL2] = INTPRI((m_SH4_IPRC & 0x0f00)>>8, SH4_INTC_IRL2); + m_exception_priority[SH4_INTC_IRL3] = INTPRI((m_SH4_IPRC & 0xf000)>>12,SH4_INTC_IRL3); + sh4_exception_recompute(); + } + } + break; + + case PCCR_PDCR: + { + if (mem_mask & 0xffff0000) + { + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PCCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PDCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + break; + + case PECR_PFCR: + { + if (mem_mask & 0xffff0000) + { + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PECR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + break; + + + case PGCR_PHCR: + { + if (mem_mask & 0xffff0000) + { + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + break; + + + case PJCR_PKCR: + { + if (mem_mask & 0xffff0000) + { + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + break; + + + case PLCR_SCPCR: + { + if (mem_mask & 0xffff0000) + { + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PLCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (SCPCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + break; + + case PADR_PBDR: + { + if (mem_mask & 0xffff0000) + { + WritePort(SH3_PORT_A, (data>>24)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + WritePort(SH3_PORT_B, (data>>8)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + break; + + case PCDR_PDDR: + { + if (mem_mask & 0xffff0000) + { + WritePort(SH3_PORT_C, (data>>24)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + WritePort(SH3_PORT_D, (data>>8)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + break; + case PEDR_PFDR: + { + if (mem_mask & 0xffff0000) + { + WritePort(SH3_PORT_E, (data>>24)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PEDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + WritePort(SH3_PORT_F, (data>>8)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + break; + + case PGDR_PHDR: + { + if (mem_mask & 0xffff0000) + { + WritePort(SH3_PORT_G, (data>>24)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + WritePort(SH3_PORT_H, (data>>8)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + break; + + + case PJDR_PKDR: + { + if (mem_mask & 0xffff0000) + { + WritePort(SH3_PORT_J, (data>>24)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + WritePort(SH3_PORT_K, (data>>8)&0xff); + //logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + break; + + case SCSMR2_SCBRR2: + { + if (mem_mask & 0xff000000) + { + logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSMR2 - Serial Mode Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ff00) + { + logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCBRR2 - Bit Rate Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + break; + + case SCSCR2_SCFTDR2: + { + if (mem_mask & 0xff000000) + { + logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSCR2 - Serial Control Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ff00) + { + logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + break; + + case SCSSR2_SCFRDR2: + { + if (mem_mask & 0xffff0000) + { + logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSSR2 - Serial Status Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ff00) + { + logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + break; + + case SCFCR2_SCFDR2: + { + if (mem_mask & 0xff000000) + { + logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFCR2 - Fifo Control Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + + if (mem_mask & 0x0000ffff) + { + logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFDR2 - Fifo Data Count Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + } + } + break; + + default: + { + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x\n", + tag(), m_pc & AM, + (offset *4)+0x4000000, + data, + mem_mask); + } + break; + } + + } + else + { + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x\n", + tag(), m_pc & AM, + (offset *4)+0x4000000, + data, + mem_mask); + } + +} diff --git a/src/cpu/sh4/sh4.cpp b/src/cpu/sh4/sh4.cpp new file mode 100644 index 000000000..452641efe --- /dev/null +++ b/src/cpu/sh4/sh4.cpp @@ -0,0 +1,5138 @@ +/***************************************************************************** + * + * sh4.c + * Portable Hitachi SH-4 (SH7750 family) emulator + * + * By R. Belmont, based on sh2.c by Juergen Buchmueller, Mariusz Wojcieszek, + * Olivier Galibert, Sylvain Glaize, and James Forshaw. + * + * + * TODO: FPU + * DMA + * on-board peripherals + * + * DONE: boot/reset setup + * 64-bit data bus + * banked registers + * additional registers for supervisor mode + * FPU status and data registers + * state save for the new registers + * interrupts + * store queues + * + *****************************************************************************/ + +#include "burnint.h" +#include "sh4_intf.h" +#include +#include "sh4.h" +#include "sh4regs.h" +#include "sh4comn.h" +#include "sh3comn.h" +#include "sh4dmac.h" +#include "sh4tmu.h" +#include "math.h" + +#define COMBINE_DATA(varptr) (*(varptr) = (*(varptr) & ~mem_mask) | (data & mem_mask)) + +static int c_md2; +static int c_md1; +static int c_md0; +static int c_md6; +static int c_md4; +static int c_md3; +static int c_md5; +static int c_md7; +static int c_md8; +static int c_clock; + +static UINT32 m_ppc; +static UINT32 m_pc; +static UINT32 m_spc; +static UINT32 m_pr; +static UINT32 m_sr; +static UINT32 m_ssr; +static UINT32 m_gbr; +static UINT32 m_vbr; +static UINT32 m_mach; +static UINT32 m_macl; +static UINT32 m_r[16]; +static UINT32 m_rbnk[2][8]; +static UINT32 m_sgr; +static UINT32 m_fr[16]; +static UINT32 m_xf[16]; +static UINT32 m_ea; +static UINT32 m_delay; +static UINT32 m_cpu_off; +static UINT32 m_pending_irq; +static UINT32 m_test_irq; +static UINT32 m_fpscr; +static UINT32 m_fpul; +static UINT32 m_dbr; + +static UINT32 m_exception_priority[128]; +static int m_exception_requesting[128]; + +static UINT32 m_irq_line_state[17]; + +// sh4 internal +static UINT32 m_m[16384]; + +// timer regs handled manually for reuse +static UINT32 m_SH4_TSTR; +static UINT32 m_SH4_TCNT0; +static UINT32 m_SH4_TCNT1; +static UINT32 m_SH4_TCNT2; +static UINT32 m_SH4_TCR0; +static UINT32 m_SH4_TCR1; +static UINT32 m_SH4_TCR2; +static UINT32 m_SH4_TCOR0; +static UINT32 m_SH4_TCOR1; +static UINT32 m_SH4_TCOR2; +static UINT32 m_SH4_TOCR; +static UINT32 m_SH4_TCPR2; + +// INTC regs +static UINT32 m_SH4_IPRA; + +static UINT32 m_SH4_IPRC; + +// DMAC regs +static UINT32 m_SH4_SAR0; +static UINT32 m_SH4_SAR1; +static UINT32 m_SH4_SAR2; +static UINT32 m_SH4_SAR3; + +static UINT32 m_SH4_DAR0; +static UINT32 m_SH4_DAR1; +static UINT32 m_SH4_DAR2; +static UINT32 m_SH4_DAR3; + +static UINT32 m_SH4_CHCR0; +static UINT32 m_SH4_CHCR1; +static UINT32 m_SH4_CHCR2; +static UINT32 m_SH4_CHCR3; + +static UINT32 m_SH4_DMATCR0; +static UINT32 m_SH4_DMATCR1; +static UINT32 m_SH4_DMATCR2; +static UINT32 m_SH4_DMATCR3; + +static UINT32 m_SH4_DMAOR; + +static UINT32 m_nmi_line_state; + +static UINT32 m_sleep_mode; + +static int m_frt_input; +static int m_irln; +static int m_internal_irq_level; +static int m_internal_irq_vector; + +/*emu_timer *m_dma_timer[4]; +emu_timer *m_refresh_timer; +emu_timer *m_rtc_timer; +emu_timer *m_timer[3];*/ + +static UINT32 m_refresh_timer_base; +static int m_dma_timer_active[4]; +static UINT32 m_dma_source[4]; +static UINT32 m_dma_destination[4]; +static UINT32 m_dma_count[4]; +static int m_dma_wordsize[4]; +static int m_dma_source_increment[4]; +static int m_dma_destination_increment[4]; +static int m_dma_mode[4]; + +static int m_sh4_icount; +static int m_is_slave; +static int m_cpu_clock; +static int m_bus_clock; +static int m_pm_clock; +static int m_pm_divider; +static int m_fpu_sz; +static int m_fpu_pr; +static int m_ioport16_pullup; +static int m_ioport16_direction; +static int m_ioport4_pullup; +static int m_ioport4_direction; + +//static void (*m_ftcsr_read_callback)(UINT32 data); + +/* This MMU simulation is good for the simple remap used on Naomi GD-ROM SQ access *ONLY* */ +static UINT32 m_sh4_tlb_address[64]; +static UINT32 m_sh4_tlb_data[64]; +static UINT8 m_sh4_mmu_enabled; + +static int m_cpu_type; + +// sh3 internal +static UINT32 m_sh3internal_upper[0x3000/4]; +static UINT32 m_sh3internal_lower[0x1000]; + +static INT32 sh3_total_cycles; // used externally (drivers/etc) + +static INT32 sh3_end_run; + +static UINT32 area_last = 0; +static UINT32 area_cur = 0; +static UINT32 area_write = 0; + +// Wait state config (WCR2 -> AreaWS[7]) - see sh3comn.c +#define EAT(c) { m_sh4_icount -= c; sh3_total_cycles += c; } +static INT32 AreaWS1[7]; +static INT32 AreaWS2[7]; +//extern int counter; +#if 0 +static inline void WaitState(UINT32 a, UINT32 is_write) { + // causes too much game-lag, perhaps I messed up the impl? + extern int counter; // enabled via-debug counter (m/n keys in fbneo) + if (counter) { + area_cur = a & 0xff000000; + if (area_cur != area_last || area_write != is_write) { + EAT(AreaWS1[a >> (24+2)]); + } + area_last = area_cur; + area_write = is_write; + } +} +#else +#define WaitState +#endif + +// logging stuff +static TCHAR *tag() { static TCHAR id[10] = _T("sh-3\0"); return &id[0]; } +#define logerror //(s, ...) bprintf(0, _T(s), __VA_ARGS__); +#define fatalerror(s, ...) bprintf(0, _T(s), __VA_ARGS__); +#define INPUT_LINE_NMI 0x20 +#define CLEAR_LINE 0 +#ifdef LSB_FIRST +#define NATIVE_ENDIAN_VALUE_LE_BE(le, be) (le) +#else +#define NATIVE_ENDIAN_VALUE_LE_BE(le, be) (be) +#endif + +// timer granularity speedhack +static INT32 timer_granularity = 0; + +void Sh3SetTimerGranularity(INT32 timergransh) +{ + timer_granularity = timergransh; +} + +//-- timer jibbajabba --------------------+1 +// simple timer system -dink 2019, v2 (2022-upgreydde ver.) +struct dtimer +{ + INT32 running; + UINT32 time_trig; + UINT32 time_current; + INT32 timer_param; + INT32 timer_prescaler; + UINT32 prescale_counter; + INT32 retrig; + void (*timer_exec)(int); + + void scan() { + SCAN_VAR(running); + SCAN_VAR(time_trig); + SCAN_VAR(time_current); + SCAN_VAR(timer_param); + SCAN_VAR(timer_prescaler); + SCAN_VAR(prescale_counter); + SCAN_VAR(retrig); + } + + void start(UINT32 trig_at, INT32 tparam, INT32 run_now, INT32 retrigger) { + running = run_now; + if (tparam != -1) timer_param = tparam; + time_trig = trig_at; + time_current = 0; + prescale_counter = 0; + retrig = retrigger; + //if (counter) bprintf(0, _T("timer %d START: %d cycles - running: %d\n"), timer_param, time_trig, running); + //if (counter) bprintf(0, _T("timer %d running %d - timeleft %d time_trig %d time_current %d\n"), timer_param, running, time_trig - time_current, time_trig, time_current); + } + + void init(INT32 tparam, void (*callback)(int)) { + config(tparam, callback); + reset(); + } + + void config(INT32 tparam, void (*callback)(int)) { + timer_param = tparam; + timer_exec = callback; + timer_prescaler = 1; + } + + void set_prescaler(INT32 prescale) { + timer_prescaler = prescale; + } + + void run_prescale(INT32 cyc) { + for (INT32 i = 0; i < cyc; i++) { + prescale_counter++; + if (prescale_counter >= timer_prescaler) { + prescale_counter = 0; + run(1); + } + } + } + + void run(INT32 cyc) { + if (running && time_trig != -1) { + time_current += cyc; + + if (time_current >= time_trig) { // should be while (retrig needs this, not used by sh4) + //if (counter) bprintf(0, _T("timer %d hits @ %d\n"), timer_param, time_current); + + if (retrig == 0) { + running = 0; + //time_trig = -1; + //stop(); + //break; + } + if (timer_exec) { + timer_exec(timer_param); // NOTE: this cb _might_ re-start/init the timer! + } + //time_current -= time_trig; + } + } + } + + void reset() { + running = 0; + time_current = 0; + timer_param = 0; + } + void stop() { + reset(); + } + INT32 isrunning() { + return running; + } + UINT32 timeleft() { + return time_trig - time_current; + } +}; + +static dtimer m_timer[3]; +static dtimer m_dma_timer[4]; +static dtimer cave_blitter_delay; + +static void sh4_run_timers(INT32 cycles) { + m_timer[0].run_prescale(cycles); + m_timer[1].run_prescale(cycles); + m_timer[2].run_prescale(cycles); + + m_dma_timer[0].run(cycles); + m_dma_timer[1].run(cycles); + m_dma_timer[2].run(cycles); + m_dma_timer[3].run(cycles); + + cave_blitter_delay.run(cycles); +} + +static void (*pCaveBlitterDelayFunc)(int); + +void sh4_set_cave_blitter_delay_func(void (*pfunc)(int)) +{ + pCaveBlitterDelayFunc = pfunc; +} + +void sh4_set_cave_blitter_delay_timer(int cycles) +{ + cave_blitter_delay.start(cycles, -1, 1, 0); +} + +static void cave_blitter_delay_func(int param) +{ + if (pCaveBlitterDelayFunc) { + pCaveBlitterDelayFunc(0); + } +} + +void Sh3SetClockCV1k(INT32 clock) +{ + c_clock = clock; + m_pm_divider = clock / (12800000 * 2); + bprintf(0, _T("Sh3SetClockCV1k: %d tmu prescale %d\n"), c_clock, m_pm_divider); +} + +INT32 sh4_get_cpu_speed() { + return c_clock; +} + +INT32 Sh3Scan(INT32 nAction) +{ + SCAN_VAR(m_ppc); + SCAN_VAR(m_pc); + SCAN_VAR(m_spc); + SCAN_VAR(m_pr); + SCAN_VAR(m_sr); + SCAN_VAR(m_ssr); + SCAN_VAR(m_gbr); + SCAN_VAR(m_vbr); + SCAN_VAR(m_mach); + SCAN_VAR(m_macl); + SCAN_VAR(m_r); + SCAN_VAR(m_rbnk); + SCAN_VAR(m_sgr); + SCAN_VAR(m_fr); + SCAN_VAR(m_xf); + SCAN_VAR(m_ea); + SCAN_VAR(m_delay); + SCAN_VAR(m_cpu_off); + SCAN_VAR(m_pending_irq); + SCAN_VAR(m_test_irq); + SCAN_VAR(m_fpscr); + SCAN_VAR(m_fpul); + SCAN_VAR(m_dbr); + + SCAN_VAR(m_exception_priority); + SCAN_VAR(m_exception_requesting); + + SCAN_VAR(m_irq_line_state); + + SCAN_VAR(m_m); + + SCAN_VAR(m_SH4_TSTR); + SCAN_VAR(m_SH4_TCNT0); + SCAN_VAR(m_SH4_TCNT1); + SCAN_VAR(m_SH4_TCNT2); + SCAN_VAR(m_SH4_TCR0); + SCAN_VAR(m_SH4_TCR1); + SCAN_VAR(m_SH4_TCR2); + SCAN_VAR(m_SH4_TCOR0); + SCAN_VAR(m_SH4_TCOR1); + SCAN_VAR(m_SH4_TCOR2); + SCAN_VAR(m_SH4_TOCR); + SCAN_VAR(m_SH4_TCPR2); + + SCAN_VAR(m_SH4_IPRA); + + SCAN_VAR(m_SH4_IPRC); + + + SCAN_VAR(m_SH4_SAR0); + SCAN_VAR(m_SH4_SAR1); + SCAN_VAR(m_SH4_SAR2); + SCAN_VAR(m_SH4_SAR3); + + SCAN_VAR(m_SH4_DAR0); + SCAN_VAR(m_SH4_DAR1); + SCAN_VAR(m_SH4_DAR2); + SCAN_VAR(m_SH4_DAR3); + + SCAN_VAR(m_SH4_CHCR0); + SCAN_VAR(m_SH4_CHCR1); + SCAN_VAR(m_SH4_CHCR2); + SCAN_VAR(m_SH4_CHCR3); + + SCAN_VAR(m_SH4_DMATCR0); + SCAN_VAR(m_SH4_DMATCR1); + SCAN_VAR(m_SH4_DMATCR2); + SCAN_VAR(m_SH4_DMATCR3); + + SCAN_VAR(m_SH4_DMAOR); + + SCAN_VAR(m_nmi_line_state); + + SCAN_VAR(m_sleep_mode); + + SCAN_VAR(m_frt_input); + SCAN_VAR(m_irln); + SCAN_VAR(m_internal_irq_level); + SCAN_VAR(m_internal_irq_vector); + + SCAN_VAR(m_refresh_timer_base); + SCAN_VAR(m_dma_timer_active); + SCAN_VAR(m_dma_source); + SCAN_VAR(m_dma_destination); + SCAN_VAR(m_dma_count); + SCAN_VAR(m_dma_wordsize); + SCAN_VAR(m_dma_source_increment); + SCAN_VAR(m_dma_destination_increment); + SCAN_VAR(m_dma_mode); + + SCAN_VAR(m_sh4_icount); + SCAN_VAR(m_is_slave); + SCAN_VAR(m_cpu_clock); + SCAN_VAR(m_bus_clock); + SCAN_VAR(m_pm_clock); + SCAN_VAR(m_pm_divider); + SCAN_VAR(m_fpu_sz); + SCAN_VAR(m_fpu_pr); + SCAN_VAR(m_ioport16_pullup); + SCAN_VAR(m_ioport16_direction); + SCAN_VAR(m_ioport4_pullup); + SCAN_VAR(m_ioport4_direction); + + SCAN_VAR(m_sh4_tlb_address); + SCAN_VAR(m_sh4_tlb_data); + SCAN_VAR(m_sh4_mmu_enabled); + + SCAN_VAR(m_sh3internal_upper); + SCAN_VAR(m_sh3internal_lower); + + SCAN_VAR(sh3_total_cycles); + + SCAN_VAR(sh3_end_run); + + SCAN_VAR(AreaWS1); + SCAN_VAR(AreaWS2); + SCAN_VAR(area_last); + SCAN_VAR(area_write); + + m_timer[0].scan(); + m_timer[1].scan(); + m_timer[2].scan(); + + m_dma_timer[0].scan(); + m_dma_timer[1].scan(); + m_dma_timer[2].scan(); + m_dma_timer[3].scan(); + + cave_blitter_delay.scan(); + + return 0; +} + +//-- sh3 memory handler for Finalburn Neo --------------------- + +#define SH3_BITS (16) // 16 = 0x10000 page size +#define SH3_PAGE_COUNT (1 << (32 - SH3_BITS)) // Number of pages +#define SH3_SHIFT (SH3_BITS) // Shift value = page bits +#define SH3_PAGE_SIZE (1 << SH3_BITS) // Page size +#define SH3_PAGEM (SH3_PAGE_SIZE - 1) +#define SH3_WADD (SH3_PAGE_COUNT) // Value to add for write section = Number of pages +#define SH3_MASK (SH3_WADD - 1) + +#define SH3_MAXHANDLER (8) + +static UINT8 *MemMap[SH3_PAGE_COUNT * 3]; +static pSh3ReadByteHandler ReadByte[SH3_MAXHANDLER]; +static pSh3WriteByteHandler WriteByte[SH3_MAXHANDLER]; +static pSh3ReadWordHandler ReadWord[SH3_MAXHANDLER]; +static pSh3WriteWordHandler WriteWord[SH3_MAXHANDLER]; +static pSh3ReadLongHandler ReadLong[SH3_MAXHANDLER]; +static pSh3WriteLongHandler WriteLong[SH3_MAXHANDLER]; + +static pSh3ReadLongHandler ReadPort; +static pSh3WriteLongHandler WritePort; + +static UINT32 __fastcall Sh3DummyReadLong(UINT32) { return 0; } +static void __fastcall Sh3DummyWriteLong(UINT32, UINT32) { } + +static INT32 Sh3MapInit() +{ + bprintf(0, _T("Init Sh3 MEMMAP\n")); + memset(MemMap, 0, sizeof(MemMap)); + + return 0; +} + +INT32 Sh3MapMemory(UINT8* pMemory, UINT32 nStart, UINT32 nEnd, INT32 nType) +{ + UINT8* Ptr = pMemory - nStart; + UINT8** pMemMap = MemMap + (nStart >> SH3_SHIFT); + + for (UINT64 i = (nStart & ~SH3_PAGEM); i <= nEnd; i += SH3_PAGE_SIZE, pMemMap++) { + if (nType & MAP_READ) pMemMap[0] = Ptr + i; + if (nType & MAP_WRITE) pMemMap[SH3_WADD] = Ptr + i; + if (nType & MAP_FETCHOP) pMemMap[SH3_WADD*2] = Ptr + i; + } + + return 0; +} + +INT32 Sh3MapHandler(uintptr_t nHandler, UINT32 nStart, UINT32 nEnd, INT32 nType) +{ + UINT8** pMemMap = MemMap + (nStart >> SH3_SHIFT); + + for (UINT64 i = (nStart & ~SH3_PAGEM); i <= nEnd; i += SH3_PAGE_SIZE, pMemMap++) { + if (nType & MAP_READ) pMemMap[0] = (UINT8*)nHandler; + if (nType & MAP_WRITE) pMemMap[SH3_WADD] = (UINT8*)nHandler; + if (nType & MAP_FETCHOP) pMemMap[SH3_WADD*2] = (UINT8*)nHandler; + } + return 0; +} + +INT32 Sh3SetReadPortHandler(pSh3ReadLongHandler pHandler) +{ + ReadPort = pHandler; + return 0; +} + +INT32 Sh3SetWritePortHandler(pSh3WriteLongHandler pHandler) +{ + WritePort = pHandler; + return 0; +} + +INT32 Sh3SetReadByteHandler(INT32 i, pSh3ReadByteHandler pHandler) +{ + if (i >= SH3_MAXHANDLER) { + bprintf(PRINT_ERROR, _T("Sh3SetReadByteHandler called with invalid index %x\n"), i); + return 1; + } + + ReadByte[i] = pHandler; + return 0; +} + +INT32 Sh3SetWriteByteHandler(INT32 i, pSh3WriteByteHandler pHandler) +{ + if (i >= SH3_MAXHANDLER) { + bprintf(PRINT_ERROR, _T("Sh3SetWriteByteHandler called with invalid index %x\n"), i); + return 1; + } + + WriteByte[i] = pHandler; + return 0; +} + +INT32 Sh3SetReadWordHandler(INT32 i, pSh3ReadWordHandler pHandler) +{ + if (i >= SH3_MAXHANDLER) { + bprintf(PRINT_ERROR, _T("Sh3SetReadWordHandler called with invalid index %x\n"), i); + return 1; + } + + ReadWord[i] = pHandler; + return 0; +} + +INT32 Sh3SetWriteWordHandler(INT32 i, pSh3WriteWordHandler pHandler) +{ + if (i >= SH3_MAXHANDLER) { + bprintf(PRINT_ERROR, _T("Sh3SetWriteWordHandler called with invalid index %x\n"), i); + return 1; + } + + WriteWord[i] = pHandler; + return 0; +} + +INT32 Sh3SetReadLongHandler(INT32 i, pSh3ReadLongHandler pHandler) +{ + if (i >= SH3_MAXHANDLER) { + bprintf(PRINT_ERROR, _T("Sh3SetReadLongHandler called with invalid index %x\n"), i); + return 1; + } + + ReadLong[i] = pHandler; + return 0; +} + +INT32 Sh3SetWriteLongHandler(INT32 i, pSh3WriteLongHandler pHandler) +{ + if (i >= SH3_MAXHANDLER) { + bprintf(PRINT_ERROR, _T("Sh3SetWriteLongHandler called with invalid index %x\n"), i); + return 1; + } + + WriteLong[i] = pHandler; + return 0; +} + +UINT32 Sh3GetPC(int) +{ + return (m_delay) ? (m_delay & AM) : (m_pc & AM); +} + +void Sh3BurnUntilInt() +{ + m_cpu_off = 1; +} + +void Sh3RunEnd() +{ + sh3_end_run = 1; +} + +INT32 Sh3TotalCycles() +{ + return sh3_total_cycles; +} + +void Sh3NewFrame() +{ + sh3_total_cycles = 0; +} + +void Sh3BurnCycles(INT32 cycles) +{ + m_sh4_icount -= cycles; + sh3_total_cycles += cycles; +} + +void Sh3Idle(INT32 cycles) +{ + m_sh4_icount -= cycles; + sh3_total_cycles += cycles; +} + +static UINT8 __fastcall Sh3LowerReadByte(UINT32 a) +{ + return sh3_internal_r((a - SH3_LOWER_REGBASE)>>2, (0xff << (((~a) & 3)*8))) >> (((~a) & 3)*8); +} + +static UINT16 __fastcall Sh3LowerReadWord(UINT32 a) +{ + return sh3_internal_r((a - SH3_LOWER_REGBASE)>>2, (0xffff << (((~a) & 2)*8))) >> (((~a) & 2)*8); +} + +static UINT32 __fastcall Sh3LowerReadLong(UINT32 a) +{ + return sh3_internal_r((a - SH3_LOWER_REGBASE)>>2, 0xffffffff); +} + +static void __fastcall Sh3LowerWriteByte(UINT32 a, UINT8 d) +{ + sh3_internal_w((a - SH3_LOWER_REGBASE)>>2, d << (((~a) & 3)*8), (0xff << (((~a) & 3)*8))); +} + +static void __fastcall Sh3LowerWriteWord(UINT32 a, UINT16 d) +{ + sh3_internal_w((a - SH3_LOWER_REGBASE)>>2, d << (((~a) & 2)*8), (0xffff << (((~a) & 2)*8))); +} + +static void __fastcall Sh3LowerWriteLong(UINT32 a, UINT32 d) +{ + sh3_internal_w((a - SH3_LOWER_REGBASE)>>2, d, 0xffffffff); +} + +static UINT8 __fastcall Sh3UpperReadByte(UINT32 a) +{ + return sh3_internal_high_r((a - SH3_UPPER_REGBASE)>>2, (0xff << (((~a) & 3)*8))) >> (((~a) & 3)*8); +} + +static UINT16 __fastcall Sh3UpperReadWord(UINT32 a) +{ + return sh3_internal_high_r((a - SH3_UPPER_REGBASE)>>2, (0xffff << (((~a) & 2)*8))) >> (((~a) & 2)*8); +} + +static UINT32 __fastcall Sh3UpperReadLong(UINT32 a) +{ + return sh3_internal_high_r((a - SH3_UPPER_REGBASE)>>2, 0xffffffff); +} + +static void __fastcall Sh3UpperWriteByte(UINT32 a, UINT8 d) +{ + sh3_internal_high_w((a - SH3_UPPER_REGBASE)>>2, d << (((~a) & 3)*8), (0xff << (((~a) & 3)*8))); +} + +static void __fastcall Sh3UpperWriteWord(UINT32 a, UINT16 d) +{ + sh3_internal_high_w((a - SH3_UPPER_REGBASE)>>2, d << (((~a) & 2)*8), (0xffff << (((~a) & 2)*8))); +} + +static void __fastcall Sh3UpperWriteLong(UINT32 a, UINT32 d) +{ + sh3_internal_high_w((a - SH3_UPPER_REGBASE)>>2, d, 0xffffffff); +} + +void Sh3Init(INT32 num, INT32 hz, char md0, char md1, char md2, char md3, char md4, char md5, char md6, char md7, char md8 ) +{ + if (num != 0) { + bprintf(0, _T("--- Sh3Init(): only supports single cpu.\n")); + return; + } + + bprintf(0, _T("-- sh3 init @ %dhz\n"), hz); + + c_clock = hz; + + m_cpu_type = CPU_TYPE_SH3; + + c_md0 = md0; c_md1 = md1; c_md2 = md2; c_md3 = md3; + c_md4 = md4; c_md5 = md5; c_md6 = md6; c_md7 = md7; c_md8 = md8; + + Sh3SetReadPortHandler(Sh3DummyReadLong); + Sh3SetWritePortHandler(Sh3DummyWriteLong); + + Sh3MapInit(); + + Sh3MapHandler(SH3_MAXHANDLER - 1, SH3_LOWER_REGBASE, SH3_LOWER_REGEND, MAP_READ | MAP_WRITE); + Sh3MapHandler(SH3_MAXHANDLER - 2, SH3_UPPER_REGBASE, SH3_UPPER_REGEND, MAP_READ | MAP_WRITE); + + Sh3SetReadByteHandler (SH3_MAXHANDLER - 1, Sh3LowerReadByte); + Sh3SetReadWordHandler (SH3_MAXHANDLER - 1, Sh3LowerReadWord); + Sh3SetReadLongHandler (SH3_MAXHANDLER - 1, Sh3LowerReadLong); + Sh3SetWriteByteHandler(SH3_MAXHANDLER - 1, Sh3LowerWriteByte); + Sh3SetWriteWordHandler(SH3_MAXHANDLER - 1, Sh3LowerWriteWord); + Sh3SetWriteLongHandler(SH3_MAXHANDLER - 1, Sh3LowerWriteLong); + + Sh3SetReadByteHandler (SH3_MAXHANDLER - 2, Sh3UpperReadByte); + Sh3SetReadWordHandler (SH3_MAXHANDLER - 2, Sh3UpperReadWord); + Sh3SetReadLongHandler (SH3_MAXHANDLER - 2, Sh3UpperReadLong); + Sh3SetWriteByteHandler(SH3_MAXHANDLER - 2, Sh3UpperWriteByte); + Sh3SetWriteWordHandler(SH3_MAXHANDLER - 2, Sh3UpperWriteWord); + Sh3SetWriteLongHandler(SH3_MAXHANDLER - 2, Sh3UpperWriteLong); + + for (INT32 i = 0; i < 3; i++) { + m_timer[i].init(i, sh4_timer_callback); + } + + for (INT32 i = 0; i < 4; i++) { + m_dma_timer[i].init(i | 0x10, sh4_dmac_callback); // "| 0x10" for timer logging + } + + cave_blitter_delay.init(0 | 0x100, cave_blitter_delay_func); // "| 0x100" for timer logging + + sh4_set_cave_blitter_delay_func(NULL); + + sh4_parse_configuration(); + sh4_default_exception_priorities(); + m_irln = 15; + m_test_irq = 0; + + Sh3SetClockCV1k(c_clock); +} + +void Sh3Exit() +{ +} + +void Sh3Open(const INT32 i) +{ + if (i != 0) bprintf(0, _T("Sh3Open(%d): only supports single cpu, currently.\n")); +} + +void Sh3Close() +{ +} + +/* Called for unimplemented opcodes */ +static void TODO(const UINT16 opcode) +{ +} + +static UINT8 *pr = NULL; + +static inline UINT16 sh3_cpu_readop16(UINT32 A) +{ + WaitState(A, 0); + + pr = MemMap[(A >> SH3_SHIFT) + SH3_WADD * 2]; // MAP_FETCH + + return *((UINT16 *)(pr + (A & SH3_PAGEM))); +} + +static inline UINT8 RB(UINT32 A) +{ + if (A < 0xe0000000) { + A &= AM; + WaitState(A, 0); + } + + pr = MemMap[ A >> SH3_SHIFT ]; + if ( (uintptr_t)pr >= SH3_MAXHANDLER ) { +#ifdef LSB_FIRST + A ^= 1; +#endif + return pr[A & SH3_PAGEM]; + } + return ReadByte[(uintptr_t)pr](A); +} + +static inline UINT16 RW(UINT32 A) +{ + if (A < 0xe0000000) { + A &= AM; + WaitState(A, 0); + } + + pr = MemMap[ A >> SH3_SHIFT ]; + if ( (uintptr_t)pr >= SH3_MAXHANDLER ) { +#ifdef LSB_FIRST + // A ^= 2; +#endif + //return (pr[A & SH3_PAGEM] << 8) | pr[(A & SH3_PAGEM) + 1]; + return *((UINT16 *)(pr + (A & SH3_PAGEM))); + } + return ReadWord[(uintptr_t)pr](A); +} + +static inline UINT32 RL(UINT32 A) +{ + if (A < 0xe0000000) { + A &= AM; + WaitState(A, 0); + } + + pr = MemMap[ A >> SH3_SHIFT ]; + if ( (uintptr_t)pr >= SH3_MAXHANDLER ) { + UINT32 V = *((UINT32 *)(pr + (A & SH3_PAGEM))); + V = (V << 16) | (V >> 16); + return V; + } + return ReadLong[(uintptr_t)pr](A); +} + +static inline void WB(UINT32 A, UINT8 V) +{ + if (A < 0xe0000000) { + A &= AM; + WaitState(A, 1); + } + + pr = MemMap[(A >> SH3_SHIFT) + SH3_WADD]; + if ((uintptr_t)pr >= SH3_MAXHANDLER) { +#ifdef LSB_FIRST + A ^= 1; +#endif + pr[A & SH3_PAGEM] = (UINT8)V; + return; + } + WriteByte[(uintptr_t)pr](A, V); +} + +static inline void WW(UINT32 A, UINT16 V) +{ + if (A < 0xe0000000) { + A &= AM; + WaitState(A, 1); + } + + pr = MemMap[(A >> SH3_SHIFT) + SH3_WADD]; + if ((uintptr_t)pr >= SH3_MAXHANDLER) { +#ifdef LSB_FIRST + // A ^= 2; +#endif + *((UINT16 *)(pr + (A & SH3_PAGEM))) = (UINT16)V; + return; + } + WriteWord[(uintptr_t)pr](A, V); +} + +static inline void WL(UINT32 A, UINT32 V) +{ + if (A < 0xe0000000) { + A &= AM; + WaitState(A, 1); + } + + pr = MemMap[(A >> SH3_SHIFT) + SH3_WADD]; + if ((uintptr_t)pr >= SH3_MAXHANDLER) { + V = (V << 16) | (V >> 16); + *((UINT32 *)(pr + (A & SH3_PAGEM))) = (UINT32)V; + return; + } + WriteLong[(uintptr_t)pr](A, V); +} + +#include "sh4comn.inc" +#include "sh3comn.inc" +#include "sh4tmu.inc" +#include "sh4dmac.inc" + +/* code cycles t-bit + * 0011 nnnn mmmm 1100 1 - + * ADD Rm,Rn + */ +static inline void ADD(const UINT16 opcode) +{ + m_r[Rn] += m_r[Rm]; +} + +/* code cycles t-bit + * 0111 nnnn iiii iiii 1 - + * ADD #imm,Rn + */ +static inline void ADDI(const UINT16 opcode) +{ + m_r[Rn] += (INT32)(INT16)(INT8)(opcode&0xff); +} + +/* code cycles t-bit + * 0011 nnnn mmmm 1110 1 carry + * ADDC Rm,Rn + */ +static inline void ADDC(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + UINT32 tmp0, tmp1; + + tmp1 = m_r[n] + m_r[m]; + tmp0 = m_r[n]; + m_r[n] = tmp1 + (m_sr & T); + if (tmp0 > tmp1) + m_sr |= T; + else + m_sr &= ~T; + if (tmp1 > m_r[n]) + m_sr |= T; +} + +/* code cycles t-bit + * 0011 nnnn mmmm 1111 1 overflow + * ADDV Rm,Rn + */ +static inline void ADDV(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + INT32 dest, src, ans; + + if ((INT32) m_r[n] >= 0) + dest = 0; + else + dest = 1; + if ((INT32) m_r[m] >= 0) + src = 0; + else + src = 1; + src += dest; + m_r[n] += m_r[m]; + if ((INT32) m_r[n] >= 0) + ans = 0; + else + ans = 1; + ans += dest; + if (src == 0 || src == 2) + { + if (ans == 1) + m_sr |= T; + else + m_sr &= ~T; + } + else + m_sr &= ~T; +} + +/* code cycles t-bit + * 0010 nnnn mmmm 1001 1 - + * AND Rm,Rn + */ +static inline void AND(const UINT16 opcode) +{ + m_r[Rn] &= m_r[Rm]; +} + + +/* code cycles t-bit + * 1100 1001 iiii iiii 1 - + * AND #imm,R0 + */ +static inline void ANDI(const UINT16 opcode) +{ + m_r[0] &= (opcode&0xff); +} + +/* code cycles t-bit + * 1100 1101 iiii iiii 1 - + * AND.B #imm,@(R0,GBR) + */ +static inline void ANDM(const UINT16 opcode) +{ + UINT32 temp; + + m_ea = m_gbr + m_r[0]; + temp = (opcode&0xff) & RB( m_ea ); + WB(m_ea, temp ); + m_sh4_icount -= 2; + sh3_total_cycles += 2; +} + +/* code cycles t-bit + * 1000 1011 dddd dddd 3/1 - + * BF disp8 + */ +static inline void BF(const UINT16 opcode) +{ + if ((m_sr & T) == 0) + { + INT32 disp = ((INT32)(opcode&0xff) << 24) >> 24; + m_pc = m_ea = m_pc + disp * 2 + 2; + m_sh4_icount -= 2; + sh3_total_cycles += 2; + } +} + +/* code cycles t-bit + * 1000 1111 dddd dddd 3/1 - + * BFS disp8 + */ +static inline void BFS(const UINT16 opcode) +{ + if ((m_sr & T) == 0) + { + INT32 disp = ((INT32)(opcode&0xff) << 24) >> 24; + m_delay = m_pc; + m_pc = m_ea = m_pc + disp * 2 + 2; + m_sh4_icount--; + sh3_total_cycles += 1; + } +} + +/* code cycles t-bit + * 1010 dddd dddd dddd 2 - + * BRA disp12 + */ +static inline void BRA(const UINT16 opcode) +{ + INT32 disp = ((INT32)(opcode&0xfff) << 20) >> 20; + +#if BUSY_LOOP_HACKS + if (disp == -2) + { + UINT32 next_opcode = RW(m_ppc & AM); + /* BRA $ + * NOP + */ + if (next_opcode == 0x0009) { + m_sh4_icount %= 3; /* cycles for BRA $ and NOP taken (3) */ + } + } +#endif + m_delay = m_pc; + m_pc = m_ea = m_pc + disp * 2 + 2; + m_sh4_icount--; + sh3_total_cycles += 1; +} + +/* code cycles t-bit + * 0000 mmmm 0010 0011 2 - + * BRAF Rm + */ +static inline void BRAF(const UINT16 opcode) +{ + m_delay = m_pc; + m_pc += m_r[Rn] + 2; + m_sh4_icount--; + sh3_total_cycles += 1; +} + +/* code cycles t-bit + * 1011 dddd dddd dddd 2 - + * BSR disp12 + */ +static inline void BSR(const UINT16 opcode) +{ + INT32 disp = ((INT32)(opcode&0xfff) << 20) >> 20; + + m_pr = m_pc + 2; + m_delay = m_pc; + m_pc = m_ea = m_pc + disp * 2 + 2; + m_sh4_icount--; + sh3_total_cycles += 1; +} + +/* code cycles t-bit + * 0000 mmmm 0000 0011 2 - + * BSRF Rm + */ +static inline void BSRF(const UINT16 opcode) +{ + m_pr = m_pc + 2; + m_delay = m_pc; + m_pc += m_r[Rn] + 2; + m_sh4_icount--; + sh3_total_cycles += 1; +} + +/* code cycles t-bit + * 1000 1001 dddd dddd 3/1 - + * BT disp8 + */ +static inline void BT(const UINT16 opcode) +{ + if ((m_sr & T) != 0) + { + INT32 disp = ((INT32)(opcode&0xff) << 24) >> 24; + m_pc = m_ea = m_pc + disp * 2 + 2; + m_sh4_icount -= 2; + sh3_total_cycles += 2; + } +} + +/* code cycles t-bit + * 1000 1101 dddd dddd 2/1 - + * BTS disp8 + */ +static inline void BTS(const UINT16 opcode) +{ + if ((m_sr & T) != 0) + { + INT32 disp = ((INT32)(opcode&0xff) << 24) >> 24; + m_delay = m_pc; + m_pc = m_ea = m_pc + disp * 2 + 2; + m_sh4_icount--; + sh3_total_cycles += 1; + } +} + +/* code cycles t-bit + * 0000 0000 0010 1000 1 - + * CLRMAC + */ +static inline void CLRMAC(const UINT16 opcode) +{ + m_mach = 0; + m_macl = 0; +} + +/* code cycles t-bit + * 0000 0000 0000 1000 1 - + * CLRT + */ +static inline void CLRT(const UINT16 opcode) +{ + m_sr &= ~T; +} + +/* code cycles t-bit + * 0011 nnnn mmmm 0000 1 comparison result + * CMP_EQ Rm,Rn + */ +static inline void CMPEQ(const UINT16 opcode) +{ + if (m_r[Rn] == m_r[Rm]) + m_sr |= T; + else + m_sr &= ~T; +} + +/* code cycles t-bit + * 0011 nnnn mmmm 0011 1 comparison result + * CMP_GE Rm,Rn + */ +static inline void CMPGE(const UINT16 opcode) +{ + if ((INT32) m_r[Rn] >= (INT32) m_r[Rm]) + m_sr |= T; + else + m_sr &= ~T; +} + +/* code cycles t-bit + * 0011 nnnn mmmm 0111 1 comparison result + * CMP_GT Rm,Rn + */ +static inline void CMPGT(const UINT16 opcode) +{ + if ((INT32) m_r[Rn] > (INT32) m_r[Rm]) + m_sr |= T; + else + m_sr &= ~T; +} + +/* code cycles t-bit + * 0011 nnnn mmmm 0110 1 comparison result + * CMP_HI Rm,Rn + */ +static inline void CMPHI(const UINT16 opcode) +{ + if ((UINT32) m_r[Rn] > (UINT32) m_r[Rm]) + m_sr |= T; + else + m_sr &= ~T; +} + +/* code cycles t-bit + * 0011 nnnn mmmm 0010 1 comparison result + * CMP_HS Rm,Rn + */ +static inline void CMPHS(const UINT16 opcode) +{ + if ((UINT32) m_r[Rn] >= (UINT32) m_r[Rm]) + m_sr |= T; + else + m_sr &= ~T; +} + + +/* code cycles t-bit + * 0100 nnnn 0001 0101 1 comparison result + * CMP_PL Rn + */ +static inline void CMPPL(const UINT16 opcode) +{ + if ((INT32) m_r[Rn] > 0) + m_sr |= T; + else + m_sr &= ~T; +} + +/* code cycles t-bit + * 0100 nnnn 0001 0001 1 comparison result + * CMP_PZ Rn + */ +static inline void CMPPZ(const UINT16 opcode) +{ + if ((INT32) m_r[Rn] >= 0) + m_sr |= T; + else + m_sr &= ~T; +} + +/* code cycles t-bit + * 0010 nnnn mmmm 1100 1 comparison result + * CMP_STR Rm,Rn + */ +static inline void CMPSTR(const UINT16 opcode) +{ + UINT32 temp; + INT32 HH, HL, LH, LL; + temp = m_r[Rn] ^ m_r[Rm]; + HH = (temp >> 24) & 0xff; + HL = (temp >> 16) & 0xff; + LH = (temp >> 8) & 0xff; + LL = temp & 0xff; + if (HH && HL && LH && LL) + m_sr &= ~T; + else + m_sr |= T; + } + + +/* code cycles t-bit + * 1000 1000 iiii iiii 1 comparison result + * CMP/EQ #imm,R0 + */ +static inline void CMPIM(const UINT16 opcode) +{ + UINT32 imm = (UINT32)(INT32)(INT16)(INT8)(opcode&0xff); + + if (m_r[0] == imm) + m_sr |= T; + else + m_sr &= ~T; +} + +/* code cycles t-bit + * 0010 nnnn mmmm 0111 1 calculation result + * DIV0S Rm,Rn + */ +static inline void DIV0S(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + if ((m_r[n] & 0x80000000) == 0) + m_sr &= ~Q; + else + m_sr |= Q; + if ((m_r[m] & 0x80000000) == 0) + m_sr &= ~M; + else + m_sr |= M; + if ((m_r[m] ^ m_r[n]) & 0x80000000) + m_sr |= T; + else + m_sr &= ~T; +} + +/* code cycles t-bit + * 0000 0000 0001 1001 1 0 + * DIV0U + */ +static inline void DIV0U(const UINT16 opcode) +{ + m_sr &= ~(M | Q | T); +} + +/* code cycles t-bit + * 0011 nnnn mmmm 0100 1 calculation result + * DIV1 Rm,Rn + */ +static inline void DIV1(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + UINT32 tmp0; + UINT32 old_q; + + old_q = m_sr & Q; + if (0x80000000 & m_r[n]) + m_sr |= Q; + else + m_sr &= ~Q; + + m_r[n] = (m_r[n] << 1) | (m_sr & T); + + if (!old_q) + { + if (!(m_sr & M)) + { + tmp0 = m_r[n]; + m_r[n] -= m_r[m]; + if(!(m_sr & Q)) + if(m_r[n] > tmp0) + m_sr |= Q; + else + m_sr &= ~Q; + else + if(m_r[n] > tmp0) + m_sr &= ~Q; + else + m_sr |= Q; + } + else + { + tmp0 = m_r[n]; + m_r[n] += m_r[m]; + if(!(m_sr & Q)) + { + if(m_r[n] < tmp0) + m_sr &= ~Q; + else + m_sr |= Q; + } + else + { + if(m_r[n] < tmp0) + m_sr |= Q; + else + m_sr &= ~Q; + } + } + } + else + { + if (!(m_sr & M)) + { + tmp0 = m_r[n]; + m_r[n] += m_r[m]; + if(!(m_sr & Q)) + if(m_r[n] < tmp0) + m_sr |= Q; + else + m_sr &= ~Q; + else + if(m_r[n] < tmp0) + m_sr &= ~Q; + else + m_sr |= Q; + } + else + { + tmp0 = m_r[n]; + m_r[n] -= m_r[m]; + if(!(m_sr & Q)) + if(m_r[n] > tmp0) + m_sr &= ~Q; + else + m_sr |= Q; + else + if(m_r[n] > tmp0) + m_sr |= Q; + else + m_sr &= ~Q; + } + } + + tmp0 = (m_sr & (Q | M)); + if((!tmp0) || (tmp0 == 0x300)) /* if Q == M set T else clear T */ + m_sr |= T; + else + m_sr &= ~T; +} + +/* DMULS.L Rm,Rn */ +static inline void DMULS(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2; + UINT32 temp0, temp1, temp2, temp3; + INT32 tempm, tempn, fnLmL; + + tempn = (INT32) m_r[n]; + tempm = (INT32) m_r[m]; + if (tempn < 0) + tempn = 0 - tempn; + if (tempm < 0) + tempm = 0 - tempm; + if ((INT32) (m_r[n] ^ m_r[m]) < 0) + fnLmL = -1; + else + fnLmL = 0; + temp1 = (UINT32) tempn; + temp2 = (UINT32) tempm; + RnL = temp1 & 0x0000ffff; + RnH = (temp1 >> 16) & 0x0000ffff; + RmL = temp2 & 0x0000ffff; + RmH = (temp2 >> 16) & 0x0000ffff; + temp0 = RmL * RnL; + temp1 = RmH * RnL; + temp2 = RmL * RnH; + temp3 = RmH * RnH; + Res2 = 0; + Res1 = temp1 + temp2; + if (Res1 < temp1) + Res2 += 0x00010000; + temp1 = (Res1 << 16) & 0xffff0000; + Res0 = temp0 + temp1; + if (Res0 < temp0) + Res2++; + Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3; + if (fnLmL < 0) + { + Res2 = ~Res2; + if (Res0 == 0) + Res2++; + else + Res0 = (~Res0) + 1; + } + m_mach = Res2; + m_macl = Res0; + m_sh4_icount--; + sh3_total_cycles += 1; +} + +/* DMULU.L Rm,Rn */ +static inline void DMULU(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2; + UINT32 temp0, temp1, temp2, temp3; + + RnL = m_r[n] & 0x0000ffff; + RnH = (m_r[n] >> 16) & 0x0000ffff; + RmL = m_r[m] & 0x0000ffff; + RmH = (m_r[m] >> 16) & 0x0000ffff; + temp0 = RmL * RnL; + temp1 = RmH * RnL; + temp2 = RmL * RnH; + temp3 = RmH * RnH; + Res2 = 0; + Res1 = temp1 + temp2; + if (Res1 < temp1) + Res2 += 0x00010000; + temp1 = (Res1 << 16) & 0xffff0000; + Res0 = temp0 + temp1; + if (Res0 < temp0) + Res2++; + Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3; + m_mach = Res2; + m_macl = Res0; + m_sh4_icount--; + sh3_total_cycles += 1; +} + +/* DT Rn */ +static inline void DT(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_r[n]--; + if (m_r[n] == 0) + m_sr |= T; + else + m_sr &= ~T; +#if BUSY_LOOP_HACKS + { + UINT32 next_opcode = RW(m_ppc & AM); + /* DT Rn + * BF $-2 + */ + if (next_opcode == 0x8bfd) + { + while (m_r[n] > 1 && m_sh4_icount > 4) + { + m_r[n]--; + m_sh4_icount -= 4; /* cycles for DT (1) and BF taken (3) */ + sh3_total_cycles += 4; + } + } + } +#endif +} + +/* EXTS.B Rm,Rn */ +static inline void EXTSB(const UINT16 opcode) +{ + m_r[Rn] = ((INT32)m_r[Rm] << 24) >> 24; +} + +/* EXTS.W Rm,Rn */ +static inline void EXTSW(const UINT16 opcode) +{ + m_r[Rn] = ((INT32)m_r[Rm] << 16) >> 16; +} + +/* EXTU.B Rm,Rn */ +static inline void EXTUB(const UINT16 opcode) +{ + m_r[Rn] = m_r[Rm] & 0x000000ff; +} + +/* EXTU.W Rm,Rn */ +static inline void EXTUW(const UINT16 opcode) +{ + m_r[Rn] = m_r[Rm] & 0x0000ffff; +} + +/* JMP @Rm */ +static inline void JMP(const UINT16 opcode) +{ + m_delay = m_pc; + m_pc = m_ea = m_r[Rn]; +} + +/* JSR @Rm */ +static inline void JSR(const UINT16 opcode) +{ + m_delay = m_pc; + m_pr = m_pc + 2; + m_pc = m_ea = m_r[Rn]; + m_sh4_icount--; + sh3_total_cycles += 1; +} + + +/* LDC Rm,SR */ +static inline void LDCSR(const UINT16 opcode) +{ + UINT32 reg; + + reg = m_r[Rn]; +// if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) +// sh4_syncronize_register_bank((m_sr & sRB) >> 29); + if ((m_r[Rn] & sRB) != (m_sr & sRB)) + sh4_change_register_bank(m_r[Rn] & sRB ? 1 : 0); + m_sr = reg & FLAGS; + sh4_exception_recompute(); +} + +/* LDC Rm,GBR */ +static inline void LDCGBR(const UINT16 opcode) +{ + m_gbr = m_r[Rn]; +} + +/* LDC Rm,VBR */ +static inline void LDCVBR(const UINT16 opcode) +{ + m_vbr = m_r[Rn]; +} + +/* LDC.L @Rm+,SR */ +static inline void LDCMSR(const UINT16 opcode) +{ + UINT32 old; + + old = m_sr; + m_ea = m_r[Rn]; + m_sr = RL(m_ea ) & FLAGS; +// if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) +// sh4_syncronize_register_bank((old & sRB) >> 29); + if ((old & sRB) != (m_sr & sRB)) + sh4_change_register_bank(m_sr & sRB ? 1 : 0); + m_r[Rn] += 4; + m_sh4_icount -= 2; + sh3_total_cycles += 2; + sh4_exception_recompute(); +} + +/* LDC.L @Rm+,GBR */ +static inline void LDCMGBR(const UINT16 opcode) +{ + m_ea = m_r[Rn]; + m_gbr = RL(m_ea ); + m_r[Rn] += 4; + m_sh4_icount -= 2; + sh3_total_cycles += 2; +} + +/* LDC.L @Rm+,VBR */ +static inline void LDCMVBR(const UINT16 opcode) +{ + m_ea = m_r[Rn]; + m_vbr = RL(m_ea ); + m_r[Rn] += 4; + m_sh4_icount -= 2; + sh3_total_cycles += 2; +} + +/* LDS Rm,MACH */ +static inline void LDSMACH(const UINT16 opcode) +{ + m_mach = m_r[Rn]; +} + +/* LDS Rm,MACL */ +static inline void LDSMACL(const UINT16 opcode) +{ + m_macl = m_r[Rn]; +} + +/* LDS Rm,PR */ +static inline void LDSPR(const UINT16 opcode) +{ + m_pr = m_r[Rn]; +} + +/* LDS.L @Rm+,MACH */ +static inline void LDSMMACH(const UINT16 opcode) +{ + m_ea = m_r[Rn]; + m_mach = RL(m_ea ); + m_r[Rn] += 4; +} + +/* LDS.L @Rm+,MACL */ +static inline void LDSMMACL(const UINT16 opcode) +{ + m_ea = m_r[Rn]; + m_macl = RL(m_ea ); + m_r[Rn] += 4; +} + +/* LDS.L @Rm+,PR */ +static inline void LDSMPR(const UINT16 opcode) +{ + m_ea = m_r[Rn]; + m_pr = RL(m_ea ); + m_r[Rn] += 4; +} + +/* MAC.L @Rm+,@Rn+ */ +static inline void MAC_L(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2; + UINT32 temp0, temp1, temp2, temp3; + INT32 tempm, tempn, fnLmL; + + tempn = (INT32) RL(m_r[n] ); + m_r[n] += 4; + tempm = (INT32) RL(m_r[m] ); + m_r[m] += 4; + if ((INT32) (tempn ^ tempm) < 0) + fnLmL = -1; + else + fnLmL = 0; + if (tempn < 0) + tempn = 0 - tempn; + if (tempm < 0) + tempm = 0 - tempm; + temp1 = (UINT32) tempn; + temp2 = (UINT32) tempm; + RnL = temp1 & 0x0000ffff; + RnH = (temp1 >> 16) & 0x0000ffff; + RmL = temp2 & 0x0000ffff; + RmH = (temp2 >> 16) & 0x0000ffff; + temp0 = RmL * RnL; + temp1 = RmH * RnL; + temp2 = RmL * RnH; + temp3 = RmH * RnH; + Res2 = 0; + Res1 = temp1 + temp2; + if (Res1 < temp1) + Res2 += 0x00010000; + temp1 = (Res1 << 16) & 0xffff0000; + Res0 = temp0 + temp1; + if (Res0 < temp0) + Res2++; + Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3; + if (fnLmL < 0) + { + Res2 = ~Res2; + if (Res0 == 0) + Res2++; + else + Res0 = (~Res0) + 1; + } + if (m_sr & S) + { + Res0 = m_macl + Res0; + if (m_macl > Res0) + Res2++; + Res2 += (m_mach & 0x0000ffff); + if (((INT32) Res2 < 0) && (Res2 < 0xffff8000)) + { + Res2 = 0x00008000; + Res0 = 0x00000000; + } + else if (((INT32) Res2 > 0) && (Res2 > 0x00007fff)) + { + Res2 = 0x00007fff; + Res0 = 0xffffffff; + } + m_mach = Res2; + m_macl = Res0; + } + else + { + Res0 = m_macl + Res0; + if (m_macl > Res0) + Res2++; + Res2 += m_mach; + m_mach = Res2; + m_macl = Res0; + } + m_sh4_icount -= 2; + sh3_total_cycles += 2; +} + +/* MAC.W @Rm+,@Rn+ */ +static inline void MAC_W(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + INT32 tempm, tempn, dest, src, ans; + UINT32 templ; + + tempn = (INT32) RW(m_r[n] ); + m_r[n] += 2; + tempm = (INT32) RW(m_r[m] ); + m_r[m] += 2; + templ = m_macl; + tempm = ((INT32) (short) tempn * (INT32) (short) tempm); + if ((INT32) m_macl >= 0) + dest = 0; + else + dest = 1; + if ((INT32) tempm >= 0) + { + src = 0; + tempn = 0; + } + else + { + src = 1; + tempn = 0xffffffff; + } + src += dest; + m_macl += tempm; + if ((INT32) m_macl >= 0) + ans = 0; + else + ans = 1; + ans += dest; + if (m_sr & S) + { + if (ans == 1) + { + if (src == 0) + m_macl = 0x7fffffff; + if (src == 2) + m_macl = 0x80000000; + } + } + else + { + m_mach += tempn; + if (templ > m_macl) + m_mach += 1; + } + m_sh4_icount -= 2; + sh3_total_cycles += 2; +} + +/* MOV Rm,Rn */ +static inline void MOV(const UINT16 opcode) +{ + m_r[Rn] = m_r[Rm]; +} + +/* MOV.B Rm,@Rn */ +static inline void MOVBS(const UINT16 opcode) +{ + m_ea = m_r[Rn]; + WB(m_ea, m_r[Rm] & 0x000000ff); +} + +/* MOV.W Rm,@Rn */ +static inline void MOVWS(const UINT16 opcode) +{ + m_ea = m_r[Rn]; + WW(m_ea, m_r[Rm] & 0x0000ffff); +} + +/* MOV.L Rm,@Rn */ +static inline void MOVLS(const UINT16 opcode) +{ + m_ea = m_r[Rn]; + WL(m_ea, m_r[Rm] ); +} + +/* MOV.B @Rm,Rn */ +static inline void MOVBL(const UINT16 opcode) +{ + m_ea = m_r[Rm]; + m_r[Rn] = (UINT32)(INT32)(INT16)(INT8) RB( m_ea ); +} + +/* MOV.W @Rm,Rn */ +static inline void MOVWL(const UINT16 opcode) +{ + m_ea = m_r[Rm]; + m_r[Rn] = (UINT32)(INT32)(INT16) RW(m_ea ); +} + +/* MOV.L @Rm,Rn */ +static inline void MOVLL(const UINT16 opcode) +{ + m_ea = m_r[Rm]; + m_r[Rn] = RL(m_ea ); +} + +/* MOV.B Rm,@-Rn */ +static inline void MOVBM(const UINT16 opcode) +{ + UINT32 data = m_r[Rm] & 0x000000ff; + + m_r[Rn] -= 1; + WB(m_r[Rn], data ); +} + +/* MOV.W Rm,@-Rn */ +static inline void MOVWM(const UINT16 opcode) +{ + UINT32 data = m_r[Rm] & 0x0000ffff; + + m_r[Rn] -= 2; + WW(m_r[Rn], data ); +} + +/* MOV.L Rm,@-Rn */ +static inline void MOVLM(const UINT16 opcode) +{ + UINT32 data = m_r[Rm]; + + m_r[Rn] -= 4; + WL(m_r[Rn], data ); +} + +/* MOV.B @Rm+,Rn */ +static inline void MOVBP(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + m_r[n] = (UINT32)(INT32)(INT16)(INT8) RB( m_r[m] ); + if (n != m) + m_r[m] += 1; +} + +/* MOV.W @Rm+,Rn */ +static inline void MOVWP(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + m_r[n] = (UINT32)(INT32)(INT16) RW(m_r[m] ); + if (n != m) + m_r[m] += 2; +} + +/* MOV.L @Rm+,Rn */ +static inline void MOVLP(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + m_r[n] = RL(m_r[m] ); + if (n != m) + m_r[m] += 4; +} + +/* MOV.B Rm,@(R0,Rn) */ +static inline void MOVBS0(const UINT16 opcode) +{ + m_ea = m_r[Rn] + m_r[0]; + WB(m_ea, m_r[Rm] & 0x000000ff ); +} + +/* MOV.W Rm,@(R0,Rn) */ +static inline void MOVWS0(const UINT16 opcode) +{ + m_ea = m_r[Rn] + m_r[0]; + WW(m_ea, m_r[Rm] & 0x0000ffff ); +} + +/* MOV.L Rm,@(R0,Rn) */ +static inline void MOVLS0(const UINT16 opcode) +{ + m_ea = m_r[Rn] + m_r[0]; + WL(m_ea, m_r[Rm] ); +} + +/* MOV.B @(R0,Rm),Rn */ +static inline void MOVBL0(const UINT16 opcode) +{ + m_ea = m_r[Rm] + m_r[0]; + m_r[Rn] = (UINT32)(INT32)(INT16)(INT8) RB( m_ea ); +} + +/* MOV.W @(R0,Rm),Rn */ +static inline void MOVWL0(const UINT16 opcode) +{ + m_ea = m_r[Rm] + m_r[0]; + m_r[Rn] = (UINT32)(INT32)(INT16) RW(m_ea ); +} + +/* MOV.L @(R0,Rm),Rn */ +static inline void MOVLL0(const UINT16 opcode) +{ + m_ea = m_r[Rm] + m_r[0]; + m_r[Rn] = RL(m_ea ); +} + +/* MOV #imm,Rn */ +static inline void MOVI(const UINT16 opcode) +{ + m_r[Rn] = (UINT32)(INT32)(INT16)(INT8)(opcode&0xff); +} + +/* MOV.W @(disp8,PC),Rn */ +static inline void MOVWI(const UINT16 opcode) +{ + UINT32 disp = opcode & 0xff; + m_ea = m_pc + disp * 2 + 2; + m_r[Rn] = (UINT32)(INT32)(INT16) RW(m_ea ); +} + +/* MOV.L @(disp8,PC),Rn */ +static inline void MOVLI(const UINT16 opcode) +{ + UINT32 disp = opcode & 0xff; + m_ea = ((m_pc + 2) & ~3) + disp * 4; + m_r[Rn] = RL(m_ea ); +} + +/* MOV.B @(disp8,GBR),R0 */ +static inline void MOVBLG(const UINT16 opcode) +{ + UINT32 disp = opcode & 0xff; + m_ea = m_gbr + disp; + m_r[0] = (UINT32)(INT32)(INT16)(INT8) RB( m_ea ); +} + +/* MOV.W @(disp8,GBR),R0 */ +static inline void MOVWLG(const UINT16 opcode) +{ + UINT32 disp = opcode & 0xff; + m_ea = m_gbr + disp * 2; + m_r[0] = (INT32)(INT16) RW(m_ea ); +} + +/* MOV.L @(disp8,GBR),R0 */ +static inline void MOVLLG(const UINT16 opcode) +{ + UINT32 disp = opcode & 0xff; + m_ea = m_gbr + disp * 4; + m_r[0] = RL(m_ea ); +} + +/* MOV.B R0,@(disp8,GBR) */ +static inline void MOVBSG(const UINT16 opcode) +{ + UINT32 disp = opcode & 0xff; + m_ea = m_gbr + disp; + WB(m_ea, m_r[0] & 0x000000ff ); +} + +/* MOV.W R0,@(disp8,GBR) */ +static inline void MOVWSG(const UINT16 opcode) +{ + UINT32 disp = opcode & 0xff; + m_ea = m_gbr + disp * 2; + WW(m_ea, m_r[0] & 0x0000ffff ); +} + +/* MOV.L R0,@(disp8,GBR) */ +static inline void MOVLSG(const UINT16 opcode) +{ + UINT32 disp = opcode & 0xff; + m_ea = m_gbr + disp * 4; + WL(m_ea, m_r[0] ); +} + +/* MOV.B R0,@(disp4,Rm) */ +static inline void MOVBS4(const UINT16 opcode) +{ + UINT32 disp = opcode & 0x0f; + m_ea = m_r[Rm] + disp; + WB(m_ea, m_r[0] & 0x000000ff ); +} + +/* MOV.W R0,@(disp4,Rm) */ +static inline void MOVWS4(const UINT16 opcode) +{ + UINT32 disp = opcode & 0x0f; + m_ea = m_r[Rm] + disp * 2; + WW(m_ea, m_r[0] & 0x0000ffff ); +} + +/* MOV.L Rm,@(disp4,Rn) */ +static inline void MOVLS4(const UINT16 opcode) +{ + UINT32 disp = opcode & 0x0f; + m_ea = m_r[Rn] + disp * 4; + WL(m_ea, m_r[Rm] ); +} + +/* MOV.B @(disp4,Rm),R0 */ +static inline void MOVBL4(const UINT16 opcode) +{ + UINT32 disp = opcode & 0x0f; + m_ea = m_r[Rm] + disp; + m_r[0] = (UINT32)(INT32)(INT16)(INT8) RB( m_ea ); +} + +/* MOV.W @(disp4,Rm),R0 */ +static inline void MOVWL4(const UINT16 opcode) +{ + UINT32 disp = opcode & 0x0f; + m_ea = m_r[Rm] + disp * 2; + m_r[0] = (UINT32)(INT32)(INT16) RW(m_ea ); +} + +/* MOV.L @(disp4,Rm),Rn */ +static inline void MOVLL4(const UINT16 opcode) +{ + UINT32 disp = opcode & 0x0f; + m_ea = m_r[Rm] + disp * 4; + m_r[Rn] = RL(m_ea ); +} + +/* MOVA @(disp8,PC),R0 */ +static inline void MOVA(const UINT16 opcode) +{ + UINT32 disp = opcode & 0xff; + m_ea = ((m_pc + 2) & ~3) + disp * 4; + m_r[0] = m_ea; +} + +/* MOVT Rn */ +void MOVT(const UINT16 opcode) +{ + m_r[Rn] = m_sr & T; +} + +/* MUL.L Rm,Rn */ +static inline void MULL(const UINT16 opcode) +{ + m_macl = m_r[Rn] * m_r[Rm]; + m_sh4_icount--; + sh3_total_cycles += 1; +} + +/* MULS Rm,Rn */ +static inline void MULS(const UINT16 opcode) +{ + m_macl = (INT16) m_r[Rn] * (INT16) m_r[Rm]; +} + +/* MULU Rm,Rn */ +static inline void MULU(const UINT16 opcode) +{ + m_macl = (UINT16) m_r[Rn] * (UINT16) m_r[Rm]; +} + +/* NEG Rm,Rn */ +static inline void NEG(const UINT16 opcode) +{ + m_r[Rn] = 0 - m_r[Rm]; +} + +/* NEGC Rm,Rn */ +static inline void NEGC(const UINT16 opcode) +{ + UINT32 temp; + + temp = m_r[Rm]; + m_r[Rn] = -temp - (m_sr & T); + if (temp || (m_sr & T)) + m_sr |= T; + else + m_sr &= ~T; +} + +/* NOP */ +static inline void NOP(const UINT16 opcode) +{ +} + +/* NOT Rm,Rn */ +static inline void NOT(const UINT16 opcode) +{ + m_r[Rn] = ~m_r[Rm]; +} + +/* OR Rm,Rn */ +static inline void OR(const UINT16 opcode) +{ + m_r[Rn] |= m_r[Rm]; +} + +/* OR #imm,R0 */ +static inline void ORI(const UINT16 opcode) +{ + m_r[0] |= (opcode&0xff); + m_sh4_icount -= 2; + sh3_total_cycles += 2; +} + +/* OR.B #imm,@(R0,GBR) */ +static inline void ORM(const UINT16 opcode) +{ + UINT32 temp; + + m_ea = m_gbr + m_r[0]; + temp = RB( m_ea ); + temp |= (opcode&0xff); + WB(m_ea, temp ); +} + +/* ROTCL Rn */ +static inline void ROTCL(const UINT16 opcode) +{ + UINT32 n = Rn; + + UINT32 temp; + + temp = (m_r[n] >> 31) & T; + m_r[n] = (m_r[n] << 1) | (m_sr & T); + m_sr = (m_sr & ~T) | temp; +} + +/* ROTCR Rn */ +static inline void ROTCR(const UINT16 opcode) +{ + UINT32 n = Rn; + + UINT32 temp; + temp = (m_sr & T) << 31; + if (m_r[n] & T) + m_sr |= T; + else + m_sr &= ~T; + m_r[n] = (m_r[n] >> 1) | temp; +} + +/* ROTL Rn */ +static inline void ROTL(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_sr = (m_sr & ~T) | ((m_r[n] >> 31) & T); + m_r[n] = (m_r[n] << 1) | (m_r[n] >> 31); +} + +/* ROTR Rn */ +static inline void ROTR(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_sr = (m_sr & ~T) | (m_r[n] & T); + m_r[n] = (m_r[n] >> 1) | (m_r[n] << 31); +} + +/* RTE */ +static inline void RTE(const UINT16 opcode) +{ + m_delay = m_pc; + m_pc = m_ea = m_spc; +// if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) +// sh4_syncronize_register_bank((m_sr & sRB) >> 29); + if ((m_ssr & sRB) != (m_sr & sRB)) + sh4_change_register_bank(m_ssr & sRB ? 1 : 0); + m_sr = m_ssr; + m_sh4_icount--; + sh3_total_cycles += 1; + sh4_exception_recompute(); +} + +/* RTS */ +static inline void RTS(const UINT16 opcode) +{ + m_delay = m_pc; + m_pc = m_ea = m_pr; + m_sh4_icount--; + sh3_total_cycles += 1; +} + +/* SETT */ +static inline void SETT(const UINT16 opcode) +{ + m_sr |= T; +} + +/* SHAL Rn (same as SHLL) */ +static inline void SHAL(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_sr = (m_sr & ~T) | ((m_r[n] >> 31) & T); + m_r[n] <<= 1; +} + +/* SHAR Rn */ +static inline void SHAR(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_sr = (m_sr & ~T) | (m_r[n] & T); + m_r[n] = (UINT32)((INT32)m_r[n] >> 1); +} + +/* SHLL Rn (same as SHAL) */ +static inline void SHLL(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_sr = (m_sr & ~T) | ((m_r[n] >> 31) & T); + m_r[n] <<= 1; +} + +/* SHLL2 Rn */ +static inline void SHLL2(const UINT16 opcode) +{ + m_r[Rn] <<= 2; +} + +/* SHLL8 Rn */ +static inline void SHLL8(const UINT16 opcode) +{ + m_r[Rn] <<= 8; +} + +/* SHLL16 Rn */ +static inline void SHLL16(const UINT16 opcode) +{ + m_r[Rn] <<= 16; +} + +/* SHLR Rn */ +static inline void SHLR(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_sr = (m_sr & ~T) | (m_r[n] & T); + m_r[n] >>= 1; +} + +/* SHLR2 Rn */ +static inline void SHLR2(const UINT16 opcode) +{ + m_r[Rn] >>= 2; +} + +/* SHLR8 Rn */ +static inline void SHLR8(const UINT16 opcode) +{ + m_r[Rn] >>= 8; +} + +/* SHLR16 Rn */ +static inline void SHLR16(const UINT16 opcode) +{ + m_r[Rn] >>= 16; +} + +/* SLEEP */ +static inline void SLEEP(const UINT16 opcode) +{ + /* 0 = normal mode */ + /* 1 = enters into power-down mode */ + /* 2 = go out the power-down mode after an exception */ + if(m_sleep_mode != 2) + m_pc -= 2; + m_sh4_icount -= 2; + sh3_total_cycles += 2; + /* Wait_for_exception; */ + if(m_sleep_mode == 0) + m_sleep_mode = 1; + else if(m_sleep_mode == 2) + m_sleep_mode = 0; +} + +/* STC SR,Rn */ +static inline void STCSR(const UINT16 opcode) +{ + m_r[Rn] = m_sr; +} + +/* STC GBR,Rn */ +static inline void STCGBR(const UINT16 opcode) +{ + m_r[Rn] = m_gbr; +} + +/* STC VBR,Rn */ +static inline void STCVBR(const UINT16 opcode) +{ + m_r[Rn] = m_vbr; +} + +/* STC.L SR,@-Rn */ +static inline void STCMSR(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_sr ); + m_sh4_icount--; + sh3_total_cycles += 1; +} + +/* STC.L GBR,@-Rn */ +static inline void STCMGBR(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_gbr ); + m_sh4_icount--; + sh3_total_cycles += 1; +} + +/* STC.L VBR,@-Rn */ +static inline void STCMVBR(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_vbr ); + m_sh4_icount--; + sh3_total_cycles += 1; +} + +/* STS MACH,Rn */ +static inline void STSMACH(const UINT16 opcode) +{ + m_r[Rn] = m_mach; +} + +/* STS MACL,Rn */ +static inline void STSMACL(const UINT16 opcode) +{ + m_r[Rn] = m_macl; +} + +/* STS PR,Rn */ +static inline void STSPR(const UINT16 opcode) +{ + m_r[Rn] = m_pr; +} + +/* STS.L MACH,@-Rn */ +static inline void STSMMACH(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_mach ); +} + +/* STS.L MACL,@-Rn */ +static inline void STSMMACL(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_macl ); +} + +/* STS.L PR,@-Rn */ +static inline void STSMPR(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_pr ); +} + +/* SUB Rm,Rn */ +static inline void SUB(const UINT16 opcode) +{ + m_r[Rn] -= m_r[Rm]; +} + +/* SUBC Rm,Rn */ +static inline void SUBC(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + UINT32 tmp0, tmp1; + + tmp1 = m_r[n] - m_r[m]; + tmp0 = m_r[n]; + m_r[n] = tmp1 - (m_sr & T); + if (tmp0 < tmp1) + m_sr |= T; + else + m_sr &= ~T; + if (tmp1 < m_r[n]) + m_sr |= T; +} + +/* SUBV Rm,Rn */ +static inline void SUBV(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + INT32 dest, src, ans; + + if ((INT32) m_r[n] >= 0) + dest = 0; + else + dest = 1; + if ((INT32) m_r[m] >= 0) + src = 0; + else + src = 1; + src += dest; + m_r[n] -= m_r[m]; + if ((INT32) m_r[n] >= 0) + ans = 0; + else + ans = 1; + ans += dest; + if (src == 1) + { + if (ans == 1) + m_sr |= T; + else + m_sr &= ~T; + } + else + m_sr &= ~T; +} + +/* SWAP.B Rm,Rn */ +static inline void SWAPB(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + UINT32 temp0, temp1; + + temp0 = m_r[m] & 0xffff0000; + temp1 = (m_r[m] & 0x000000ff) << 8; + m_r[n] = (m_r[m] >> 8) & 0x000000ff; + m_r[n] = m_r[n] | temp1 | temp0; +} + +/* SWAP.W Rm,Rn */ +static inline void SWAPW(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + UINT32 temp; + + temp = (m_r[m] >> 16) & 0x0000ffff; + m_r[n] = (m_r[m] << 16) | temp; +} + +/* TAS.B @Rn */ +static inline void TAS(const UINT16 opcode) +{ + UINT32 n = Rn; + + UINT32 temp; + m_ea = m_r[n]; + /* Bus Lock enable */ + temp = RB( m_ea ); + if (temp == 0) + m_sr |= T; + else + m_sr &= ~T; + temp |= 0x80; + /* Bus Lock disable */ + WB(m_ea, temp ); + m_sh4_icount -= 3; + sh3_total_cycles += 3; +} + +/* TRAPA #imm */ +static inline void TRAPA(const UINT16 opcode) +{ + UINT32 imm = opcode & 0xff; + + if (m_cpu_type == CPU_TYPE_SH4) + { + m_m[TRA] = imm << 2; + } + else /* SH3 */ + { + m_sh3internal_upper[SH3_TRA_ADDR] = imm << 2; + } + + + m_ssr = m_sr; + m_spc = m_pc; + m_sgr = m_r[15]; + + m_sr |= MD; +// if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) +// sh4_syncronize_register_bank((m_sr & sRB) >> 29); + if (!(m_sr & sRB)) + sh4_change_register_bank(1); + m_sr |= sRB; + m_sr |= BL; + sh4_exception_recompute(); + + if (m_cpu_type == CPU_TYPE_SH4) + { + m_m[EXPEVT] = 0x00000160; + } + else /* SH3 */ + { + m_sh3internal_upper[SH3_EXPEVT_ADDR] = 0x00000160; + } + + m_pc = m_vbr + 0x00000100; + + m_sh4_icount -= 7; + sh3_total_cycles += 7; +} + +/* TST Rm,Rn */ +static inline void TST(const UINT16 opcode) +{ + if ((m_r[Rn] & m_r[Rm]) == 0) + m_sr |= T; + else + m_sr &= ~T; +} + +/* TST #imm,R0 */ +static inline void TSTI(const UINT16 opcode) +{ + UINT32 imm = opcode & 0xff; + + if ((imm & m_r[0]) == 0) + m_sr |= T; + else + m_sr &= ~T; +} + +/* TST.B #imm,@(R0,GBR) */ +static inline void TSTM(const UINT16 opcode) +{ + UINT32 imm = opcode & 0xff; + + m_ea = m_gbr + m_r[0]; + if ((imm & RB( m_ea )) == 0) + m_sr |= T; + else + m_sr &= ~T; + m_sh4_icount -= 2; + sh3_total_cycles += 2; +} + +/* XOR Rm,Rn */ +static inline void XOR(const UINT16 opcode) +{ + m_r[Rn] ^= m_r[Rm]; +} + +/* XOR #imm,R0 */ +static inline void XORI(const UINT16 opcode) +{ + UINT32 imm = opcode & 0xff; + m_r[0] ^= imm; +} + +/* XOR.B #imm,@(R0,GBR) */ +static inline void XORM(const UINT16 opcode) +{ + UINT32 imm = opcode & 0xff; + UINT32 temp; + + m_ea = m_gbr + m_r[0]; + temp = RB( m_ea ); + temp ^= imm; + WB(m_ea, temp ); + m_sh4_icount -= 2; + sh3_total_cycles += 2; +} + +/* XTRCT Rm,Rn */ +static inline void XTRCT(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + UINT32 temp; + + temp = (m_r[m] << 16) & 0xffff0000; + m_r[n] = (m_r[n] >> 16) & 0x0000ffff; + m_r[n] |= temp; +} + +/* STC SSR,Rn */ +static inline void STCSSR(const UINT16 opcode) +{ + m_r[Rn] = m_ssr; +} + +/* STC SPC,Rn */ +static inline void STCSPC(const UINT16 opcode) +{ + m_r[Rn] = m_spc; +} + +/* STC SGR,Rn */ +static inline void STCSGR(const UINT16 opcode) +{ + m_r[Rn] = m_sgr; +} + +/* STS FPUL,Rn */ +static inline void STSFPUL(const UINT16 opcode) +{ + m_r[Rn] = m_fpul; +} + +/* STS FPSCR,Rn */ +static inline void STSFPSCR(const UINT16 opcode) +{ + m_r[Rn] = m_fpscr & 0x003FFFFF; +} + +/* STC DBR,Rn */ +static inline void STCDBR(const UINT16 opcode) +{ + m_r[Rn] = m_dbr; +} + +/* STCRBANK Rm_BANK,Rn */ +static inline void STCRBANK(const UINT16 opcode) +{ + UINT32 m = Rm; + + m_r[Rn] = m_rbnk[m_sr&sRB ? 0 : 1][m & 7]; +} + +/* STCMRBANK Rm_BANK,@-Rn */ +static inline void STCMRBANK(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_rbnk[m_sr&sRB ? 0 : 1][m & 7]); + m_sh4_icount--; + sh3_total_cycles += 1; +} + +/* MOVCA.L R0,@Rn */ +static inline void MOVCAL(const UINT16 opcode) +{ + m_ea = m_r[Rn]; + WL(m_ea, m_r[0] ); +} + +static inline void CLRS(const UINT16 opcode) +{ + m_sr &= ~S; +} + +static inline void SETS(const UINT16 opcode) +{ + m_sr |= S; +} + +/* STS.L SGR,@-Rn */ +static inline void STCMSGR(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_sgr ); +} + +/* STS.L FPUL,@-Rn */ +static inline void STSMFPUL(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_fpul ); +} + +/* STS.L FPSCR,@-Rn */ +static inline void STSMFPSCR(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_fpscr & 0x003FFFFF); +} + +/* STC.L DBR,@-Rn */ +static inline void STCMDBR(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_dbr ); +} + +/* STC.L SSR,@-Rn */ +static inline void STCMSSR(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_ssr ); +} + +/* STC.L SPC,@-Rn */ +static inline void STCMSPC(const UINT16 opcode) +{ + UINT32 n = Rn; + + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_spc ); +} + +/* LDS.L @Rm+,FPUL */ +static inline void LDSMFPUL(const UINT16 opcode) +{ + m_ea = m_r[Rn]; + m_fpul = RL(m_ea ); + m_r[Rn] += 4; +} + +/* LDS.L @Rm+,FPSCR */ +static inline void LDSMFPSCR(const UINT16 opcode) +{ + UINT32 s; + + s = m_fpscr; + m_ea = m_r[Rn]; + m_fpscr = RL(m_ea ); + m_fpscr &= 0x003FFFFF; + m_r[Rn] += 4; + if ((s & FR) != (m_fpscr & FR)) + sh4_swap_fp_registers(); +#ifdef LSB_FIRST + if ((s & PR) != (m_fpscr & PR)) + sh4_swap_fp_couples(); +#endif + m_fpu_sz = (m_fpscr & SZ) ? 1 : 0; + m_fpu_pr = (m_fpscr & PR) ? 1 : 0; +} + +/* LDC.L @Rm+,DBR */ +static inline void LDCMDBR(const UINT16 opcode) +{ + m_ea = m_r[Rn]; + m_dbr = RL(m_ea ); + m_r[Rn] += 4; +} + +/* LDC.L @Rn+,Rm_BANK */ +static inline void LDCMRBANK(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + m_ea = m_r[n]; + m_rbnk[m_sr&sRB ? 0 : 1][m & 7] = RL(m_ea ); + m_r[n] += 4; +} + +/* LDC.L @Rm+,SSR */ +static inline void LDCMSSR(const UINT16 opcode) +{ + m_ea = m_r[Rn]; + m_ssr = RL(m_ea ); + m_r[Rn] += 4; +} + +/* LDC.L @Rm+,SPC */ +static inline void LDCMSPC(const UINT16 opcode) +{ + m_ea = m_r[Rn]; + m_spc = RL(m_ea ); + m_r[Rn] += 4; +} + +/* LDS Rm,FPUL */ +static inline void LDSFPUL(const UINT16 opcode) +{ + m_fpul = m_r[Rn]; +} + +/* LDS Rm,FPSCR */ +static inline void LDSFPSCR(const UINT16 opcode) +{ + UINT32 s; + + s = m_fpscr; + m_fpscr = m_r[Rn] & 0x003FFFFF; + if ((s & FR) != (m_fpscr & FR)) + sh4_swap_fp_registers(); +#ifdef LSB_FIRST + if ((s & PR) != (m_fpscr & PR)) + sh4_swap_fp_couples(); +#endif + m_fpu_sz = (m_fpscr & SZ) ? 1 : 0; + m_fpu_pr = (m_fpscr & PR) ? 1 : 0; +} + +/* LDC Rm,DBR */ +static inline void LDCDBR(const UINT16 opcode) +{ + m_dbr = m_r[Rn]; +} + +/* SHAD Rm,Rn */ +static inline void SHAD(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + if ((m_r[m] & 0x80000000) == 0) + m_r[n] = m_r[n] << (m_r[m] & 0x1F); + else if ((m_r[m] & 0x1F) == 0) { + if ((m_r[n] & 0x80000000) == 0) + m_r[n] = 0; + else + m_r[n] = 0xFFFFFFFF; + } else + m_r[n]=(INT32)m_r[n] >> ((~m_r[m] & 0x1F)+1); +} + +/* SHLD Rm,Rn */ +static inline void SHLD(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + if ((m_r[m] & 0x80000000) == 0) + m_r[n] = m_r[n] << (m_r[m] & 0x1F); + else if ((m_r[m] & 0x1F) == 0) + m_r[n] = 0; + else + m_r[n] = m_r[n] >> ((~m_r[m] & 0x1F)+1); +} + +/* LDCRBANK Rn,Rm_BANK */ +static inline void LDCRBANK(const UINT16 opcode) +{ + UINT32 m = Rm; + + m_rbnk[m_sr&sRB ? 0 : 1][m & 7] = m_r[Rn]; +} + +/* LDC Rm,SSR */ +static inline void LDCSSR(const UINT16 opcode) +{ + m_ssr = m_r[Rn]; +} + +/* LDC Rm,SPC */ +static inline void LDCSPC(const UINT16 opcode) +{ + m_spc = m_r[Rn]; +} + +/* PREF @Rn */ +static inline void PREFM(const UINT16 opcode) +{ + int a; + UINT32 addr,dest,sq; + + addr = m_r[Rn]; // address + if ((addr >= 0xE0000000) && (addr <= 0xE3FFFFFF)) + { + if (m_sh4_mmu_enabled) + { + addr = addr & 0xFFFFFFE0; + dest = sh4_getsqremap(addr); // good enough for naomi-gd rom, probably not much else + + } + else + { + sq = (addr & 0x20) >> 5; + dest = addr & 0x03FFFFE0; + if (sq == 0) + { + if (m_cpu_type == CPU_TYPE_SH4) + { + dest |= (m_m[QACR0] & 0x1C) << 24; + } + else + { + fatalerror("m_cpu_type != CPU_TYPE_SH4 but access internal regs\n", 0); + } + } + else + { + if (m_cpu_type == CPU_TYPE_SH4) + { + dest |= (m_m[QACR1] & 0x1C) << 24; + } + else + { + fatalerror("m_cpu_type != CPU_TYPE_SH4 but access internal regs\n", 0); + } + + } + addr = addr & 0xFFFFFFE0; + } + + for (a = 0;a < 4;a++) + { + // shouldn't be causing a memory read, should store sq writes in registers. + //m_program->write_qword(dest, m_program->read_qword(addr)); + WL(dest, RL(addr)); + WL(dest+4, RL(addr+4)); + addr += 8; + dest += 8; + } + } +} + +/***************************************************************************** + * OPCODE DISPATCHERS + *****************************************************************************/ + + + + + + + + + + + + + + + + + +/* FMOV.S @Rm+,FRn PR=0 SZ=0 1111nnnnmmmm1001 */ +/* FMOV @Rm+,DRn PR=0 SZ=1 1111nnn0mmmm1001 */ +/* FMOV @Rm+,XDn PR=0 SZ=1 1111nnn1mmmm1001 */ +/* FMOV @Rm+,XDn PR=1 1111nnn1mmmm1001 */ +static inline void FMOVMRIFR(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + n = n & 14; + m_ea = m_r[m]; + m_r[m] += 8; + m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(m_ea ); + m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(m_ea+4 ); + } else { /* PR = 0 */ + if (m_fpu_sz) { /* SZ = 1 */ + if (n & 1) { + n = n & 14; + m_ea = m_r[m]; + m_xf[n] = RL(m_ea ); + m_r[m] += 4; + m_xf[n+1] = RL(m_ea+4 ); + m_r[m] += 4; + } else { + m_ea = m_r[m]; + m_fr[n] = RL(m_ea ); + m_r[m] += 4; + m_fr[n+1] = RL(m_ea+4 ); + m_r[m] += 4; + } + } else { /* SZ = 0 */ + m_ea = m_r[m]; + m_fr[n] = RL(m_ea ); + m_r[m] += 4; + } + } +} + +/* FMOV.S FRm,@Rn PR=0 SZ=0 1111nnnnmmmm1010 */ +/* FMOV DRm,@Rn PR=0 SZ=1 1111nnnnmmm01010 */ +/* FMOV XDm,@Rn PR=0 SZ=1 1111nnnnmmm11010 */ +/* FMOV XDm,@Rn PR=1 1111nnnnmmm11010 */ +static inline void FMOVFRMR(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + m= m & 14; + m_ea = m_r[n]; + WL(m_ea,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] ); + WL(m_ea+4,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] ); + } else { /* PR = 0 */ + if (m_fpu_sz) { /* SZ = 1 */ + if (m & 1) { + m= m & 14; + m_ea = m_r[n]; + WL(m_ea,m_xf[m] ); + WL(m_ea+4,m_xf[m+1] ); + } else { + m_ea = m_r[n]; + WL(m_ea,m_fr[m] ); + WL(m_ea+4,m_fr[m+1] ); + } + } else { /* SZ = 0 */ + m_ea = m_r[n]; + WL(m_ea,m_fr[m] ); + } + } +} + +/* FMOV.S FRm,@-Rn PR=0 SZ=0 1111nnnnmmmm1011 */ +/* FMOV DRm,@-Rn PR=0 SZ=1 1111nnnnmmm01011 */ +/* FMOV XDm,@-Rn PR=0 SZ=1 1111nnnnmmm11011 */ +/* FMOV XDm,@-Rn PR=1 1111nnnnmmm11011 */ +static inline void FMOVFRMDR(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + m= m & 14; + m_r[n] -= 8; + m_ea = m_r[n]; + WL(m_ea,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] ); + WL(m_ea+4,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] ); + } else { /* PR = 0 */ + if (m_fpu_sz) { /* SZ = 1 */ + if (m & 1) { + m= m & 14; + m_r[n] -= 8; + m_ea = m_r[n]; + WL(m_ea,m_xf[m] ); + WL(m_ea+4,m_xf[m+1] ); + } else { + m_r[n] -= 8; + m_ea = m_r[n]; + WL(m_ea,m_fr[m] ); + WL(m_ea+4,m_fr[m+1] ); + } + } else { /* SZ = 0 */ + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea,m_fr[m] ); + } + } +} + +/* FMOV.S FRm,@(R0,Rn) PR=0 SZ=0 1111nnnnmmmm0111 */ +/* FMOV DRm,@(R0,Rn) PR=0 SZ=1 1111nnnnmmm00111 */ +/* FMOV XDm,@(R0,Rn) PR=0 SZ=1 1111nnnnmmm10111 */ +/* FMOV XDm,@(R0,Rn) PR=1 1111nnnnmmm10111 */ +static inline void FMOVFRS0(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + m= m & 14; + m_ea = m_r[0] + m_r[n]; + WL(m_ea,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] ); + WL(m_ea+4,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] ); + } else { /* PR = 0 */ + if (m_fpu_sz) { /* SZ = 1 */ + if (m & 1) { + m= m & 14; + m_ea = m_r[0] + m_r[n]; + WL(m_ea,m_xf[m] ); + WL(m_ea+4,m_xf[m+1] ); + } else { + m_ea = m_r[0] + m_r[n]; + WL(m_ea,m_fr[m] ); + WL(m_ea+4,m_fr[m+1] ); + } + } else { /* SZ = 0 */ + m_ea = m_r[0] + m_r[n]; + WL(m_ea,m_fr[m] ); + } + } +} + +/* FMOV.S @(R0,Rm),FRn PR=0 SZ=0 1111nnnnmmmm0110 */ +/* FMOV @(R0,Rm),DRn PR=0 SZ=1 1111nnn0mmmm0110 */ +/* FMOV @(R0,Rm),XDn PR=0 SZ=1 1111nnn1mmmm0110 */ +/* FMOV @(R0,Rm),XDn PR=1 1111nnn1mmmm0110 */ +static inline void FMOVS0FR(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + n= n & 14; + m_ea = m_r[0] + m_r[m]; + m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(m_ea ); + m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(m_ea+4 ); + } else { /* PR = 0 */ + if (m_fpu_sz) { /* SZ = 1 */ + if (n & 1) { + n= n & 14; + m_ea = m_r[0] + m_r[m]; + m_xf[n] = RL(m_ea ); + m_xf[n+1] = RL(m_ea+4 ); + } else { + m_ea = m_r[0] + m_r[m]; + m_fr[n] = RL(m_ea ); + m_fr[n+1] = RL(m_ea+4 ); + } + } else { /* SZ = 0 */ + m_ea = m_r[0] + m_r[m]; + m_fr[n] = RL(m_ea ); + } + } +} + +/* FMOV.S @Rm,FRn PR=0 SZ=0 1111nnnnmmmm1000 */ +/* FMOV @Rm,DRn PR=0 SZ=1 1111nnn0mmmm1000 */ +/* FMOV @Rm,XDn PR=0 SZ=1 1111nnn1mmmm1000 */ +/* FMOV @Rm,XDn PR=1 1111nnn1mmmm1000 */ +/* FMOV @Rm,DRn PR=1 1111nnn0mmmm1000 */ +static inline void FMOVMRFR(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + if (n & 1) { + n= n & 14; + m_ea = m_r[m]; + m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(m_ea ); + m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(m_ea+4 ); + } else { + n= n & 14; + m_ea = m_r[m]; + m_fr[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(m_ea ); + m_fr[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(m_ea+4 ); + } + } else { /* PR = 0 */ + if (m_fpu_sz) { /* SZ = 1 */ + if (n & 1) { + n= n & 14; + m_ea = m_r[m]; + m_xf[n] = RL(m_ea ); + m_xf[n+1] = RL(m_ea+4 ); + } else { + n= n & 14; + m_ea = m_r[m]; + m_fr[n] = RL(m_ea ); + m_fr[n+1] = RL(m_ea+4 ); + } + } else { /* SZ = 0 */ + m_ea = m_r[m]; + m_fr[n] = RL(m_ea ); + } + } +} + +/* FMOV FRm,FRn PR=0 SZ=0 FRm -> FRn 1111nnnnmmmm1100 */ +/* FMOV DRm,DRn PR=0 SZ=1 DRm -> DRn 1111nnn0mmm01100 */ +/* FMOV XDm,DRn PR=1 XDm -> DRn 1111nnn0mmm11100 */ +/* FMOV DRm,XDn PR=1 DRm -> XDn 1111nnn1mmm01100 */ +/* FMOV XDm,XDn PR=1 XDm -> XDn 1111nnn1mmm11100 */ +static inline void FMOVFR(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + if ((m_fpu_sz == 0) && (m_fpu_pr == 0)) /* SZ = 0 */ + m_fr[n] = m_fr[m]; + else { /* SZ = 1 or PR = 1 */ + if (m & 1) { + if (n & 1) { + m_xf[n & 14] = m_xf[m & 14]; + m_xf[n | 1] = m_xf[m | 1]; + } else { + m_fr[n] = m_xf[m & 14]; + m_fr[n | 1] = m_xf[m | 1]; + } + } else { + if (n & 1) { + m_xf[n & 14] = m_fr[m]; + m_xf[n | 1] = m_fr[m | 1]; // (a&14)+1 -> a|1 + } else { + m_fr[n] = m_fr[m]; + m_fr[n | 1] = m_fr[m | 1]; + } + } + } +} + +/* FLDI1 FRn 1111nnnn10011101 */ +static inline void FLDI1(const UINT16 opcode) +{ + m_fr[Rn] = 0x3F800000; +} + +/* FLDI0 FRn 1111nnnn10001101 */ +static inline void FLDI0(const UINT16 opcode) +{ + m_fr[Rn] = 0; +} + +/* FLDS FRm,FPUL 1111mmmm00011101 */ +static inline void FLDS(const UINT16 opcode) +{ + m_fpul = m_fr[Rn]; +} + +/* FSTS FPUL,FRn 1111nnnn00001101 */ +static inline void FSTS(const UINT16 opcode) +{ + m_fr[Rn] = m_fpul; +} + +/* FRCHG 1111101111111101 */ +void FRCHG() +{ + m_fpscr ^= FR; + sh4_swap_fp_registers(); +} + +/* FSCHG 1111001111111101 */ +void FSCHG() +{ + m_fpscr ^= SZ; + m_fpu_sz = (m_fpscr & SZ) ? 1 : 0; +} + +/* FTRC FRm,FPUL PR=0 1111mmmm00111101 */ +/* FTRC DRm,FPUL PR=1 1111mmm000111101 */ +static inline void FTRC(const UINT16 opcode) +{ + UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + if(n & 1) + fatalerror("SH-4: FTRC opcode used with n %d",n); + + n = n & 14; + *((INT32 *)&m_fpul) = (INT32)FP_RFD(n); + } else { /* PR = 0 */ + /* read m_fr[n] as float -> truncate -> fpul(32) */ + *((INT32 *)&m_fpul) = (INT32)FP_RFS(n); + } +} + +/* FLOAT FPUL,FRn PR=0 1111nnnn00101101 */ +/* FLOAT FPUL,DRn PR=1 1111nnn000101101 */ +static inline void FLOAT(const UINT16 opcode) +{ + UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + if(n & 1) + fatalerror("SH-4: FLOAT opcode used with n %d",n); + + n = n & 14; + FP_RFD(n) = (double)*((INT32 *)&m_fpul); + } else { /* PR = 0 */ + FP_RFS(n) = (float)*((INT32 *)&m_fpul); + } +} + +/* FNEG FRn PR=0 1111nnnn01001101 */ +/* FNEG DRn PR=1 1111nnn001001101 */ +static inline void FNEG(const UINT16 opcode) +{ + UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + FP_RFD(n) = -FP_RFD(n); + } else { /* PR = 0 */ + FP_RFS(n) = -FP_RFS(n); + } +} + +/* FABS FRn PR=0 1111nnnn01011101 */ +/* FABS DRn PR=1 1111nnn001011101 */ +static inline void FABS(const UINT16 opcode) +{ + UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ +#ifdef LSB_FIRST + n = n | 1; // n & 14 + 1 + m_fr[n] = m_fr[n] & 0x7fffffff; +#else + n = n & 14; + m_fr[n] = m_fr[n] & 0x7fffffff; +#endif + } else { /* PR = 0 */ + m_fr[n] = m_fr[n] & 0x7fffffff; + } +} + +/* FCMP/EQ FRm,FRn PR=0 1111nnnnmmmm0100 */ +/* FCMP/EQ DRm,DRn PR=1 1111nnn0mmm00100 */ +static inline void FCMP_EQ(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + n = n & 14; + m = m & 14; + if (FP_RFD(n) == FP_RFD(m)) + m_sr |= T; + else + m_sr &= ~T; + } else { /* PR = 0 */ + if (FP_RFS(n) == FP_RFS(m)) + m_sr |= T; + else + m_sr &= ~T; + } +} + +/* FCMP/GT FRm,FRn PR=0 1111nnnnmmmm0101 */ +/* FCMP/GT DRm,DRn PR=1 1111nnn0mmm00101 */ +static inline void FCMP_GT(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + n = n & 14; + m = m & 14; + if (FP_RFD(n) > FP_RFD(m)) + m_sr |= T; + else + m_sr &= ~T; + } else { /* PR = 0 */ + if (FP_RFS(n) > FP_RFS(m)) + m_sr |= T; + else + m_sr &= ~T; + } +} + +/* FCNVDS DRm,FPUL PR=1 1111mmm010111101 */ +static inline void FCNVDS(const UINT16 opcode) +{ + UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + n = n & 14; + if (m_fpscr & RM) + m_fr[n | NATIVE_ENDIAN_VALUE_LE_BE(0,1)] &= 0xe0000000; /* round toward zero*/ + *((float *)&m_fpul) = (float)FP_RFD(n); + } +} + +/* FCNVSD FPUL, DRn PR=1 1111nnn010101101 */ +static inline void FCNVSD(const UINT16 opcode) +{ + UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + n = n & 14; + FP_RFD(n) = (double)*((float *)&m_fpul); + } +} + +/* FADD FRm,FRn PR=0 1111nnnnmmmm0000 */ +/* FADD DRm,DRn PR=1 1111nnn0mmm00000 */ +static inline void FADD(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + n = n & 14; + m = m & 14; + FP_RFD(n) = FP_RFD(n) + FP_RFD(m); + } else { /* PR = 0 */ + FP_RFS(n) = FP_RFS(n) + FP_RFS(m); + } +} + +/* FSUB FRm,FRn PR=0 1111nnnnmmmm0001 */ +/* FSUB DRm,DRn PR=1 1111nnn0mmm00001 */ +static inline void FSUB(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + n = n & 14; + m = m & 14; + FP_RFD(n) = FP_RFD(n) - FP_RFD(m); + } else { /* PR = 0 */ + FP_RFS(n) = FP_RFS(n) - FP_RFS(m); + } +} + + +/* FMUL FRm,FRn PR=0 1111nnnnmmmm0010 */ +/* FMUL DRm,DRn PR=1 1111nnn0mmm00010 */ +static inline void FMUL(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + n = n & 14; + m = m & 14; + FP_RFD(n) = FP_RFD(n) * FP_RFD(m); + } else { /* PR = 0 */ + FP_RFS(n) = FP_RFS(n) * FP_RFS(m); + } +} + +/* FDIV FRm,FRn PR=0 1111nnnnmmmm0011 */ +/* FDIV DRm,DRn PR=1 1111nnn0mmm00011 */ +static inline void FDIV(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + n = n & 14; + m = m & 14; + if (FP_RFD(m) == 0) + return; + FP_RFD(n) = FP_RFD(n) / FP_RFD(m); + } else { /* PR = 0 */ + if (FP_RFS(m) == 0) + return; + FP_RFS(n) = FP_RFS(n) / FP_RFS(m); + } +} + +/* FMAC FR0,FRm,FRn PR=0 1111nnnnmmmm1110 */ +static inline void FMAC(const UINT16 opcode) +{ + UINT32 m = Rm; UINT32 n = Rn; + + if (m_fpu_pr == 0) { /* PR = 0 */ + FP_RFS(n) = (FP_RFS(0) * FP_RFS(m)) + FP_RFS(n); + } +} + +/* FSQRT FRn PR=0 1111nnnn01101101 */ +/* FSQRT DRn PR=1 1111nnnn01101101 */ +static inline void FSQRT(const UINT16 opcode) +{ + UINT32 n = Rn; + + if (m_fpu_pr) { /* PR = 1 */ + n = n & 14; + if (FP_RFD(n) < 0) + return; + FP_RFD(n) = sqrtf(FP_RFD(n)); + } else { /* PR = 0 */ + if (FP_RFS(n) < 0) + return; + FP_RFS(n) = sqrtf(FP_RFS(n)); + } +} + +/* FSRRA FRn PR=0 1111nnnn01111101 */ +static inline void FSRRA(const UINT16 opcode) +{ + UINT32 n = Rn; + + if (FP_RFS(n) < 0) + return; + FP_RFS(n) = 1.0 / sqrtf(FP_RFS(n)); +} + +/* FSSCA FPUL,FRn PR=0 1111nnn011111101 */ +void FSSCA(const UINT16 opcode) +{ + UINT32 n = Rn; + +float angle; + + angle = (((float)(m_fpul & 0xFFFF)) / 65536.0) * 2.0 * M_PI; + FP_RFS(n) = sinf(angle); + FP_RFS(n+1) = cosf(angle); +} + +/* FIPR FVm,FVn PR=0 1111nnmm11101101 */ +static inline void FIPR(const UINT16 opcode) +{ + UINT32 n = Rn; + +UINT32 m; +float ml[4]; +int a; + + m = (n & 3) << 2; + n = n & 12; + for (a = 0;a < 4;a++) + ml[a] = FP_RFS(n+a) * FP_RFS(m+a); + FP_RFS(n+3) = ml[0] + ml[1] + ml[2] + ml[3]; +} + +/* FTRV XMTRX,FVn PR=0 1111nn0111111101 */ +void FTRV(const UINT16 opcode) +{ + UINT32 n = Rn; + +int i,j; +float sum[4]; + + n = n & 12; + for (i = 0;i < 4;i++) { + sum[i] = 0; + for (j=0;j < 4;j++) + sum[i] += FP_XFS((j << 2) + i)*FP_RFS(n + j); + } + for (i = 0;i < 4;i++) + FP_RFS(n + i) = sum[i]; +} + +static inline void op1111_0xf13(const UINT16 opcode) +{ + if (opcode & 0x100) { + if (opcode & 0x200) { + switch (opcode & 0xC00) + { + case 0x000: + FSCHG(); + break; + case 0x800: + FRCHG(); + break; + default: + //debugger_break(machine()); + break; + } + } else { + FTRV(opcode); + } + } else { + FSSCA(opcode); + } +} + +static void dbreak(const UINT16 opcode) +{ + //debugger_break(machine()); +} + + +static inline void op1111_0x13(UINT16 opcode) +{ + switch((opcode >> 4) & 0x0f) + { + case 0x00: FSTS(opcode); break; + case 0x01: FLDS(opcode); break; + case 0x02: FLOAT(opcode); break; + case 0x03: FTRC(opcode); break; + case 0x04: FNEG(opcode); break; + case 0x05: FABS(opcode); break; + case 0x06: FSQRT(opcode); break; + case 0x07: FSRRA(opcode); break; + case 0x08: FLDI0(opcode); break; + case 0x09: FLDI1(opcode); break; + case 0x0a: FCNVSD(opcode); break; + case 0x0b: FCNVDS(opcode); break; + case 0x0c: dbreak(opcode); break; + case 0x0d: dbreak(opcode); break; + case 0x0e: FIPR(opcode); break; + case 0x0f: op1111_0xf13(opcode); break; + } +} + + +/***************************************************************************** + * MAME CPU INTERFACE + *****************************************************************************/ + +static void sh34_device_reset() +{ + m_ppc = 0; + m_spc = 0; + m_pr = 0; + m_sr = 0; + m_ssr = 0; + m_gbr = 0; + m_vbr = 0; + m_mach = 0; + m_macl = 0; + memset(m_r, 0, sizeof(m_r)); + memset(m_rbnk, 0, sizeof(m_rbnk)); + m_sgr = 0; + memset(m_fr, 0, sizeof(m_fr)); + memset(m_xf, 0, sizeof(m_xf)); + m_ea = 0; + m_delay = 0; + m_cpu_off = 0; + m_pending_irq = 0; + m_test_irq = 0; + memset(m_exception_priority, 0, sizeof(m_exception_priority)); + memset(m_exception_requesting, 0, sizeof(m_exception_requesting)); + memset(m_m, 0, sizeof(m_m)); + memset(m_sh3internal_upper, 0, sizeof(m_sh3internal_upper)); + memset(m_sh3internal_lower, 0, sizeof(m_sh3internal_lower)); + memset(m_irq_line_state, 0, sizeof(m_irq_line_state)); + m_SH4_TSTR = 0; + m_SH4_TCNT0 = 0; + m_SH4_TCNT1 = 0; + m_SH4_TCNT2 = 0; + m_SH4_TCR0 = 0; + m_SH4_TCR1 = 0; + m_SH4_TCR2 = 0; + m_SH4_TCOR0 = 0; + m_SH4_TCOR1 = 0; + m_SH4_TCOR2 = 0; + m_SH4_TOCR = 0; + m_SH4_TCPR2 = 0; + m_SH4_IPRA = 0; + m_SH4_IPRC = 0; + m_SH4_SAR0 = 0; + m_SH4_SAR1 = 0; + m_SH4_SAR2 = 0; + m_SH4_SAR3 = 0; + m_SH4_DAR0 = 0; + m_SH4_DAR1 = 0; + m_SH4_DAR2 = 0; + m_SH4_DAR3 = 0; + m_SH4_CHCR0 = 0; + m_SH4_CHCR1 = 0; + m_SH4_CHCR2 = 0; + m_SH4_CHCR3 = 0; + m_SH4_DMATCR0 = 0; + m_SH4_DMATCR1 = 0; + m_SH4_DMATCR2 = 0; + m_SH4_DMATCR3 = 0; + m_SH4_DMAOR = 0; + m_nmi_line_state = 0; + m_frt_input = 0; + m_internal_irq_vector = 0; + m_refresh_timer_base = 0; + memset(m_dma_timer_active, 0, sizeof(m_dma_timer_active)); + memset(m_dma_source, 0, sizeof(m_dma_source)); + memset(m_dma_destination, 0, sizeof(m_dma_destination)); + memset(m_dma_count, 0, sizeof(m_dma_count)); + memset(m_dma_wordsize, 0, sizeof(m_dma_wordsize)); + memset(m_dma_source_increment, 0, sizeof(m_dma_source_increment)); + memset(m_dma_destination_increment, 0, sizeof(m_dma_destination_increment)); + memset(m_dma_mode, 0, sizeof(m_dma_mode)); + m_ioport16_pullup = 0; + m_ioport16_direction = 0; + m_ioport4_pullup = 0; + m_ioport4_direction = 0; + + sh4_default_exception_priorities(); + + //m_rtc_timer->adjust(attotime::from_hz(128)); sh4 only. + + m_pc = 0xa0000000; + m_r[15] = RL(4); + m_sr = 0x700000f0; + m_fpscr = 0x00040001; + m_fpu_sz = (m_fpscr & SZ) ? 1 : 0; + m_fpu_pr = (m_fpscr & PR) ? 1 : 0; + m_fpul = 0; + m_dbr = 0; + + m_internal_irq_level = -1; + m_irln = 15; + m_sleep_mode = 0; + + m_sh4_mmu_enabled = 0; + + m_sh4_icount = 0; + sh3_total_cycles = 0; + sh3_end_run = 0; + + memset(AreaWS1, 0, sizeof(AreaWS1)); + memset(AreaWS2, 0, sizeof(AreaWS2)); + area_cur = 0; + area_last = 0; + area_write = 0; +} + +/*------------------------------------------------- + sh3_reset - reset the processor +-------------------------------------------------*/ + +void Sh3Reset() +{ + sh34_device_reset(); + + m_SH4_TCOR0 = 0xffffffff; + m_SH4_TCNT0 = 0xffffffff; + m_SH4_TCOR1 = 0xffffffff; + m_SH4_TCNT1 = 0xffffffff; + m_SH4_TCOR2 = 0xffffffff; + m_SH4_TCNT2 = 0xffffffff; + + m_timer[0].reset(); + m_timer[1].reset(); + m_timer[2].reset(); + + m_dma_timer[0].reset(); + m_dma_timer[1].reset(); + m_dma_timer[2].reset(); + m_dma_timer[3].reset(); + + cave_blitter_delay.reset(); +} + +#if 0 +// no sh4 -dink +void sh4_base_device::device_reset() +{ + device_reset(); + + m_m[RCR2] = 0x09; + m_SH4_TCOR0 = 0xffffffff; + m_SH4_TCNT0 = 0xffffffff; + m_SH4_TCOR1 = 0xffffffff; + m_SH4_TCNT1 = 0xffffffff; + m_SH4_TCOR2 = 0xffffffff; + m_SH4_TCNT2 = 0xffffffff; +} +#endif + +static inline void execute_one_0000(const UINT16 opcode) +{ + switch(opcode & 0xff) + { + // 0x00 + case 0x00: NOP(opcode); break; + case 0x10: NOP(opcode); break; + case 0x20: NOP(opcode); break; + case 0x30: NOP(opcode); break; + case 0x40: NOP(opcode); break; + case 0x50: NOP(opcode); break; + case 0x60: NOP(opcode); break; + case 0x70: NOP(opcode); break; + case 0x80: NOP(opcode); break; + case 0x90: NOP(opcode); break; + case 0xa0: NOP(opcode); break; + case 0xb0: NOP(opcode); break; + case 0xc0: NOP(opcode); break; + case 0xd0: NOP(opcode); break; + case 0xe0: NOP(opcode); break; + case 0xf0: NOP(opcode); break; + // 0x10 + case 0x01: NOP(opcode); break; + case 0x11: NOP(opcode); break; + case 0x21: NOP(opcode); break; + case 0x31: NOP(opcode); break; + case 0x41: NOP(opcode); break; + case 0x51: NOP(opcode); break; + case 0x61: NOP(opcode); break; + case 0x71: NOP(opcode); break; + case 0x81: NOP(opcode); break; + case 0x91: NOP(opcode); break; + case 0xa1: NOP(opcode); break; + case 0xb1: NOP(opcode); break; + case 0xc1: NOP(opcode); break; + case 0xd1: NOP(opcode); break; + case 0xe1: NOP(opcode); break; + case 0xf1: NOP(opcode); break; + // 0x20 + case 0x02: STCSR(opcode); break; + case 0x12: STCGBR(opcode); break; + case 0x22: STCVBR(opcode); break; + case 0x32: STCSSR(opcode); break; + case 0x42: STCSPC(opcode); break; + case 0x52: NOP(opcode); break; + case 0x62: NOP(opcode); break; + case 0x72: NOP(opcode); break; + case 0x82: STCRBANK(opcode); break; + case 0x92: STCRBANK(opcode); break; + case 0xa2: STCRBANK(opcode); break; + case 0xb2: STCRBANK(opcode); break; + case 0xc2: STCRBANK(opcode); break; + case 0xd2: STCRBANK(opcode); break; + case 0xe2: STCRBANK(opcode); break; + case 0xf2: STCRBANK(opcode); break; + // 0x30 + case 0x03: BSRF(opcode); break; + case 0x13: NOP(opcode); break; + case 0x23: BRAF(opcode); break; + case 0x33: NOP(opcode); break; + case 0x43: NOP(opcode); break; + case 0x53: NOP(opcode); break; + case 0x63: NOP(opcode); break; + case 0x73: NOP(opcode); break; + case 0x83: PREFM(opcode); break; + case 0x93: TODO(opcode); break; + case 0xa3: TODO(opcode); break; + case 0xb3: TODO(opcode); break; + case 0xc3: MOVCAL(opcode); break; + case 0xd3: NOP(opcode); break; + case 0xe3: NOP(opcode); break; + case 0xf3: NOP(opcode); break; + // 0x40 + case 0x04: MOVBS0(opcode); break; + case 0x14: MOVBS0(opcode); break; + case 0x24: MOVBS0(opcode); break; + case 0x34: MOVBS0(opcode); break; + case 0x44: MOVBS0(opcode); break; + case 0x54: MOVBS0(opcode); break; + case 0x64: MOVBS0(opcode); break; + case 0x74: MOVBS0(opcode); break; + case 0x84: MOVBS0(opcode); break; + case 0x94: MOVBS0(opcode); break; + case 0xa4: MOVBS0(opcode); break; + case 0xb4: MOVBS0(opcode); break; + case 0xc4: MOVBS0(opcode); break; + case 0xd4: MOVBS0(opcode); break; + case 0xe4: MOVBS0(opcode); break; + case 0xf4: MOVBS0(opcode); break; + // 0x50 + case 0x05: MOVWS0(opcode); break; + case 0x15: MOVWS0(opcode); break; + case 0x25: MOVWS0(opcode); break; + case 0x35: MOVWS0(opcode); break; + case 0x45: MOVWS0(opcode); break; + case 0x55: MOVWS0(opcode); break; + case 0x65: MOVWS0(opcode); break; + case 0x75: MOVWS0(opcode); break; + case 0x85: MOVWS0(opcode); break; + case 0x95: MOVWS0(opcode); break; + case 0xa5: MOVWS0(opcode); break; + case 0xb5: MOVWS0(opcode); break; + case 0xc5: MOVWS0(opcode); break; + case 0xd5: MOVWS0(opcode); break; + case 0xe5: MOVWS0(opcode); break; + case 0xf5: MOVWS0(opcode); break; + // 0x60 + case 0x06: MOVLS0(opcode); break; + case 0x16: MOVLS0(opcode); break; + case 0x26: MOVLS0(opcode); break; + case 0x36: MOVLS0(opcode); break; + case 0x46: MOVLS0(opcode); break; + case 0x56: MOVLS0(opcode); break; + case 0x66: MOVLS0(opcode); break; + case 0x76: MOVLS0(opcode); break; + case 0x86: MOVLS0(opcode); break; + case 0x96: MOVLS0(opcode); break; + case 0xa6: MOVLS0(opcode); break; + case 0xb6: MOVLS0(opcode); break; + case 0xc6: MOVLS0(opcode); break; + case 0xd6: MOVLS0(opcode); break; + case 0xe6: MOVLS0(opcode); break; + case 0xf6: MOVLS0(opcode); break; + // 0x70 + case 0x07: MULL(opcode); break; + case 0x17: MULL(opcode); break; + case 0x27: MULL(opcode); break; + case 0x37: MULL(opcode); break; + case 0x47: MULL(opcode); break; + case 0x57: MULL(opcode); break; + case 0x67: MULL(opcode); break; + case 0x77: MULL(opcode); break; + case 0x87: MULL(opcode); break; + case 0x97: MULL(opcode); break; + case 0xa7: MULL(opcode); break; + case 0xb7: MULL(opcode); break; + case 0xc7: MULL(opcode); break; + case 0xd7: MULL(opcode); break; + case 0xe7: MULL(opcode); break; + case 0xf7: MULL(opcode); break; + // 0x80 + case 0x08: CLRT(opcode); break; + case 0x18: SETT(opcode); break; + case 0x28: CLRMAC(opcode); break; + case 0x38: TODO(opcode); break; + case 0x48: CLRS(opcode); break; + case 0x58: SETS(opcode); break; + case 0x68: NOP(opcode); break; + case 0x78: NOP(opcode); break; + case 0x88: CLRT(opcode); break; + case 0x98: SETT(opcode); break; + case 0xa8: CLRMAC(opcode); break; + case 0xb8: TODO(opcode); break; + case 0xc8: CLRS(opcode); break; + case 0xd8: SETS(opcode); break; + case 0xe8: NOP(opcode); break; + case 0xf8: NOP(opcode); break; + // 0x90 + case 0x09: NOP(opcode); break; + case 0x19: DIV0U(opcode); break; + case 0x29: MOVT(opcode); break; + case 0x39: NOP(opcode); break; + case 0x49: NOP(opcode); break; + case 0x59: DIV0U(opcode); break; + case 0x69: MOVT(opcode); break; + case 0x79: NOP(opcode); break; + case 0x89: NOP(opcode); break; + case 0x99: DIV0U(opcode); break; + case 0xa9: MOVT(opcode); break; + case 0xb9: NOP(opcode); break; + case 0xc9: NOP(opcode); break; + case 0xd9: DIV0U(opcode); break; + case 0xe9: MOVT(opcode); break; + case 0xf9: NOP(opcode); break; + // 0xa0 + case 0x0a: STSMACH(opcode); break; + case 0x1a: STSMACL(opcode); break; + case 0x2a: STSPR(opcode); break; + case 0x3a: STCSGR(opcode); break; + case 0x4a: NOP(opcode); break; + case 0x5a: STSFPUL(opcode); break; + case 0x6a: STSFPSCR(opcode); break; + case 0x7a: STCDBR(opcode); break; + case 0x8a: STSMACH(opcode); break; + case 0x9a: STSMACL(opcode); break; + case 0xaa: STSPR(opcode); break; + case 0xba: STCSGR(opcode); break; + case 0xca: NOP(opcode); break; + case 0xda: STSFPUL(opcode); break; + case 0xea: STSFPSCR(opcode); break; + case 0xfa: STCDBR(opcode); break; + // 0xb0 + case 0x0b: RTS(opcode); break; + case 0x1b: SLEEP(opcode); break; + case 0x2b: RTE(opcode); break; + case 0x3b: NOP(opcode); break; + case 0x4b: RTS(opcode); break; + case 0x5b: SLEEP(opcode); break; + case 0x6b: RTE(opcode); break; + case 0x7b: NOP(opcode); break; + case 0x8b: RTS(opcode); break; + case 0x9b: SLEEP(opcode); break; + case 0xab: RTE(opcode); break; + case 0xbb: NOP(opcode); break; + case 0xcb: RTS(opcode); break; + case 0xdb: SLEEP(opcode); break; + case 0xeb: RTE(opcode); break; + case 0xfb: NOP(opcode); break; + // 0xc0 + case 0x0c: MOVBL0(opcode); break; + case 0x1c: MOVBL0(opcode); break; + case 0x2c: MOVBL0(opcode); break; + case 0x3c: MOVBL0(opcode); break; + case 0x4c: MOVBL0(opcode); break; + case 0x5c: MOVBL0(opcode); break; + case 0x6c: MOVBL0(opcode); break; + case 0x7c: MOVBL0(opcode); break; + case 0x8c: MOVBL0(opcode); break; + case 0x9c: MOVBL0(opcode); break; + case 0xac: MOVBL0(opcode); break; + case 0xbc: MOVBL0(opcode); break; + case 0xcc: MOVBL0(opcode); break; + case 0xdc: MOVBL0(opcode); break; + case 0xec: MOVBL0(opcode); break; + case 0xfc: MOVBL0(opcode); break; + // 0xd0 + case 0x0d: MOVWL0(opcode); break; + case 0x1d: MOVWL0(opcode); break; + case 0x2d: MOVWL0(opcode); break; + case 0x3d: MOVWL0(opcode); break; + case 0x4d: MOVWL0(opcode); break; + case 0x5d: MOVWL0(opcode); break; + case 0x6d: MOVWL0(opcode); break; + case 0x7d: MOVWL0(opcode); break; + case 0x8d: MOVWL0(opcode); break; + case 0x9d: MOVWL0(opcode); break; + case 0xad: MOVWL0(opcode); break; + case 0xbd: MOVWL0(opcode); break; + case 0xcd: MOVWL0(opcode); break; + case 0xdd: MOVWL0(opcode); break; + case 0xed: MOVWL0(opcode); break; + case 0xfd: MOVWL0(opcode); break; + // 0xe0 + case 0x0e: MOVLL0(opcode); break; + case 0x1e: MOVLL0(opcode); break; + case 0x2e: MOVLL0(opcode); break; + case 0x3e: MOVLL0(opcode); break; + case 0x4e: MOVLL0(opcode); break; + case 0x5e: MOVLL0(opcode); break; + case 0x6e: MOVLL0(opcode); break; + case 0x7e: MOVLL0(opcode); break; + case 0x8e: MOVLL0(opcode); break; + case 0x9e: MOVLL0(opcode); break; + case 0xae: MOVLL0(opcode); break; + case 0xbe: MOVLL0(opcode); break; + case 0xce: MOVLL0(opcode); break; + case 0xde: MOVLL0(opcode); break; + case 0xee: MOVLL0(opcode); break; + case 0xfe: MOVLL0(opcode); break; + // 0xf0 + case 0x0f: MAC_L(opcode); break; + case 0x1f: MAC_L(opcode); break; + case 0x2f: MAC_L(opcode); break; + case 0x3f: MAC_L(opcode); break; + case 0x4f: MAC_L(opcode); break; + case 0x5f: MAC_L(opcode); break; + case 0x6f: MAC_L(opcode); break; + case 0x7f: MAC_L(opcode); break; + case 0x8f: MAC_L(opcode); break; + case 0x9f: MAC_L(opcode); break; + case 0xaf: MAC_L(opcode); break; + case 0xbf: MAC_L(opcode); break; + case 0xcf: MAC_L(opcode); break; + case 0xdf: MAC_L(opcode); break; + case 0xef: MAC_L(opcode); break; + case 0xff: MAC_L(opcode); break; + } +} + +static inline void execute_one_4000(const UINT16 opcode) +{ + switch(opcode & 0xff) + { + // 0x00 + case 0x00: SHLL(opcode); break; + case 0x10: DT(opcode); break; + case 0x20: SHAL(opcode); break; + case 0x30: NOP(opcode); break; + case 0x40: SHLL(opcode); break; + case 0x50: DT(opcode); break; + case 0x60: SHAL(opcode); break; + case 0x70: NOP(opcode); break; + case 0x80: SHLL(opcode); break; + case 0x90: DT(opcode); break; + case 0xa0: SHAL(opcode); break; + case 0xb0: NOP(opcode); break; + case 0xc0: SHLL(opcode); break; + case 0xd0: DT(opcode); break; + case 0xe0: SHAL(opcode); break; + case 0xf0: NOP(opcode); break; + // 0x10 + case 0x01: SHLR(opcode); break; + case 0x11: CMPPZ(opcode); break; + case 0x21: SHAR(opcode); break; + case 0x31: NOP(opcode); break; + case 0x41: SHLR(opcode); break; + case 0x51: CMPPZ(opcode); break; + case 0x61: SHAR(opcode); break; + case 0x71: NOP(opcode); break; + case 0x81: SHLR(opcode); break; + case 0x91: CMPPZ(opcode); break; + case 0xa1: SHAR(opcode); break; + case 0xb1: NOP(opcode); break; + case 0xc1: SHLR(opcode); break; + case 0xd1: CMPPZ(opcode); break; + case 0xe1: SHAR(opcode); break; + case 0xf1: NOP(opcode); break; + // 0x20 + case 0x02: STSMMACH(opcode); break; + case 0x12: STSMMACL(opcode); break; + case 0x22: STSMPR(opcode); break; + case 0x32: STCMSGR(opcode); break; + case 0x42: NOP(opcode); break; + case 0x52: STSMFPUL(opcode); break; + case 0x62: STSMFPSCR(opcode); break; + case 0x72: NOP(opcode); break; + case 0x82: NOP(opcode); break; + case 0x92: NOP(opcode); break; + case 0xa2: NOP(opcode); break; + case 0xb2: NOP(opcode); break; + case 0xc2: NOP(opcode); break; + case 0xd2: NOP(opcode); break; + case 0xe2: NOP(opcode); break; + case 0xf2: STCMDBR(opcode); break; + // 0x30 + case 0x03: STCMSR(opcode); break; + case 0x13: STCMGBR(opcode); break; + case 0x23: STCMVBR(opcode); break; + case 0x33: STCMSSR(opcode); break; + case 0x43: STCMSPC(opcode); break; + case 0x53: NOP(opcode); break; + case 0x63: NOP(opcode); break; + case 0x73: NOP(opcode); break; + case 0x83: STCMRBANK(opcode); break; + case 0x93: STCMRBANK(opcode); break; + case 0xa3: STCMRBANK(opcode); break; + case 0xb3: STCMRBANK(opcode); break; + case 0xc3: STCMRBANK(opcode); break; + case 0xd3: STCMRBANK(opcode); break; + case 0xe3: STCMRBANK(opcode); break; + case 0xf3: STCMRBANK(opcode); break; + // 0x40 + case 0x04: ROTL(opcode); break; + case 0x14: NOP(opcode); break; + case 0x24: ROTCL(opcode); break; + case 0x34: NOP(opcode); break; + case 0x44: ROTL(opcode); break; + case 0x54: NOP(opcode); break; + case 0x64: ROTCL(opcode); break; + case 0x74: NOP(opcode); break; + case 0x84: ROTL(opcode); break; + case 0x94: NOP(opcode); break; + case 0xa4: ROTCL(opcode); break; + case 0xb4: NOP(opcode); break; + case 0xc4: ROTL(opcode); break; + case 0xd4: NOP(opcode); break; + case 0xe4: ROTCL(opcode); break; + case 0xf4: NOP(opcode); break; + // 0x50 + case 0x05: ROTR(opcode); break; + case 0x15: CMPPL(opcode); break; + case 0x25: ROTCR(opcode); break; + case 0x35: NOP(opcode); break; + case 0x45: ROTR(opcode); break; + case 0x55: CMPPL(opcode); break; + case 0x65: ROTCR(opcode); break; + case 0x75: NOP(opcode); break; + case 0x85: ROTR(opcode); break; + case 0x95: CMPPL(opcode); break; + case 0xa5: ROTCR(opcode); break; + case 0xb5: NOP(opcode); break; + case 0xc5: ROTR(opcode); break; + case 0xd5: CMPPL(opcode); break; + case 0xe5: ROTCR(opcode); break; + case 0xf5: NOP(opcode); break; + // 0x60 + case 0x06: LDSMMACH(opcode); break; + case 0x16: LDSMMACL(opcode); break; + case 0x26: LDSMPR(opcode); break; + case 0x36: NOP(opcode); break; + case 0x46: NOP(opcode); break; + case 0x56: LDSMFPUL(opcode); break; + case 0x66: LDSMFPSCR(opcode); break; + case 0x76: NOP(opcode); break; + case 0x86: NOP(opcode); break; + case 0x96: NOP(opcode); break; + case 0xa6: NOP(opcode); break; + case 0xb6: NOP(opcode); break; + case 0xc6: NOP(opcode); break; + case 0xd6: NOP(opcode); break; + case 0xe6: NOP(opcode); break; + case 0xf6: LDCMDBR(opcode); break; + // 0x70 + case 0x07: LDCMSR(opcode); break; + case 0x17: LDCMGBR(opcode); break; + case 0x27: LDCMVBR(opcode); break; + case 0x37: LDCMSSR(opcode); break; + case 0x47: LDCMSPC(opcode); break; + case 0x57: NOP(opcode); break; + case 0x67: NOP(opcode); break; + case 0x77: NOP(opcode); break; + case 0x87: LDCMRBANK(opcode); break; + case 0x97: LDCMRBANK(opcode); break; + case 0xa7: LDCMRBANK(opcode); break; + case 0xb7: LDCMRBANK(opcode); break; + case 0xc7: LDCMRBANK(opcode); break; + case 0xd7: LDCMRBANK(opcode); break; + case 0xe7: LDCMRBANK(opcode); break; + case 0xf7: LDCMRBANK(opcode); break; + // 0x80 + case 0x08: SHLL2(opcode); break; + case 0x18: SHLL8(opcode); break; + case 0x28: SHLL16(opcode); break; + case 0x38: NOP(opcode); break; + case 0x48: SHLL2(opcode); break; + case 0x58: SHLL8(opcode); break; + case 0x68: SHLL16(opcode); break; + case 0x78: NOP(opcode); break; + case 0x88: SHLL2(opcode); break; + case 0x98: SHLL8(opcode); break; + case 0xa8: SHLL16(opcode); break; + case 0xb8: NOP(opcode); break; + case 0xc8: SHLL2(opcode); break; + case 0xd8: SHLL8(opcode); break; + case 0xe8: SHLL16(opcode); break; + case 0xf8: NOP(opcode); break; + // 0x90 + case 0x09: SHLR2(opcode); break; + case 0x19: SHLR8(opcode); break; + case 0x29: SHLR16(opcode); break; + case 0x39: NOP(opcode); break; + case 0x49: SHLR2(opcode); break; + case 0x59: SHLR8(opcode); break; + case 0x69: SHLR16(opcode); break; + case 0x79: NOP(opcode); break; + case 0x89: SHLR2(opcode); break; + case 0x99: SHLR8(opcode); break; + case 0xa9: SHLR16(opcode); break; + case 0xb9: NOP(opcode); break; + case 0xc9: SHLR2(opcode); break; + case 0xd9: SHLR8(opcode); break; + case 0xe9: SHLR16(opcode); break; + case 0xf9: NOP(opcode); break; + // 0xa0 + case 0x0a: LDSMACH(opcode); break; + case 0x1a: LDSMACL(opcode); break; + case 0x2a: LDSPR(opcode); break; + case 0x3a: NOP(opcode); break; + case 0x4a: NOP(opcode); break; + case 0x5a: LDSFPUL(opcode); break; + case 0x6a: LDSFPSCR(opcode); break; + case 0x7a: NOP(opcode); break; + case 0x8a: NOP(opcode); break; + case 0x9a: NOP(opcode); break; + case 0xaa: NOP(opcode); break; + case 0xba: NOP(opcode); break; + case 0xca: NOP(opcode); break; + case 0xda: NOP(opcode); break; + case 0xea: NOP(opcode); break; + case 0xfa: LDCDBR(opcode); break; + // 0xb0 + case 0x0b: JSR(opcode); break; + case 0x1b: TAS(opcode); break; + case 0x2b: JMP(opcode); break; + case 0x3b: NOP(opcode); break; + case 0x4b: JSR(opcode); break; + case 0x5b: TAS(opcode); break; + case 0x6b: JMP(opcode); break; + case 0x7b: NOP(opcode); break; + case 0x8b: JSR(opcode); break; + case 0x9b: TAS(opcode); break; + case 0xab: JMP(opcode); break; + case 0xbb: NOP(opcode); break; + case 0xcb: JSR(opcode); break; + case 0xdb: TAS(opcode); break; + case 0xeb: JMP(opcode); break; + case 0xfb: NOP(opcode); break; + // 0xc0 + case 0x0c: SHAD(opcode); break; + case 0x1c: SHAD(opcode); break; + case 0x2c: SHAD(opcode); break; + case 0x3c: SHAD(opcode); break; + case 0x4c: SHAD(opcode); break; + case 0x5c: SHAD(opcode); break; + case 0x6c: SHAD(opcode); break; + case 0x7c: SHAD(opcode); break; + case 0x8c: SHAD(opcode); break; + case 0x9c: SHAD(opcode); break; + case 0xac: SHAD(opcode); break; + case 0xbc: SHAD(opcode); break; + case 0xcc: SHAD(opcode); break; + case 0xdc: SHAD(opcode); break; + case 0xec: SHAD(opcode); break; + case 0xfc: SHAD(opcode); break; + // 0xd0 + case 0x0d: SHLD(opcode); break; + case 0x1d: SHLD(opcode); break; + case 0x2d: SHLD(opcode); break; + case 0x3d: SHLD(opcode); break; + case 0x4d: SHLD(opcode); break; + case 0x5d: SHLD(opcode); break; + case 0x6d: SHLD(opcode); break; + case 0x7d: SHLD(opcode); break; + case 0x8d: SHLD(opcode); break; + case 0x9d: SHLD(opcode); break; + case 0xad: SHLD(opcode); break; + case 0xbd: SHLD(opcode); break; + case 0xcd: SHLD(opcode); break; + case 0xdd: SHLD(opcode); break; + case 0xed: SHLD(opcode); break; + case 0xfd: SHLD(opcode); break; + // 0xe0 + case 0x0e: LDCSR(opcode); break; + case 0x1e: LDCGBR(opcode); break; + case 0x2e: LDCVBR(opcode); break; + case 0x3e: LDCSSR(opcode); break; + case 0x4e: LDCSPC(opcode); break; + case 0x5e: NOP(opcode); break; + case 0x6e: NOP(opcode); break; + case 0x7e: NOP(opcode); break; + case 0x8e: LDCRBANK(opcode); break; + case 0x9e: LDCRBANK(opcode); break; + case 0xae: LDCRBANK(opcode); break; + case 0xbe: LDCRBANK(opcode); break; + case 0xce: LDCRBANK(opcode); break; + case 0xde: LDCRBANK(opcode); break; + case 0xee: LDCRBANK(opcode); break; + case 0xfe: LDCRBANK(opcode); break; + // 0xf0 + case 0x0f: MAC_W(opcode); break; + case 0x1f: MAC_W(opcode); break; + case 0x2f: MAC_W(opcode); break; + case 0x3f: MAC_W(opcode); break; + case 0x4f: MAC_W(opcode); break; + case 0x5f: MAC_W(opcode); break; + case 0x6f: MAC_W(opcode); break; + case 0x7f: MAC_W(opcode); break; + case 0x8f: MAC_W(opcode); break; + case 0x9f: MAC_W(opcode); break; + case 0xaf: MAC_W(opcode); break; + case 0xbf: MAC_W(opcode); break; + case 0xcf: MAC_W(opcode); break; + case 0xdf: MAC_W(opcode); break; + case 0xef: MAC_W(opcode); break; + case 0xff: MAC_W(opcode); break; + } +} + + +static inline void execute_one(const UINT16 opcode) +{ + switch(opcode & 0xf000) + { + case 0x0000: + execute_one_0000(opcode); + break; + + case 0x1000: + MOVLS4(opcode); + break; + + case 0x2000: + switch(opcode & 0x0f) + { + case 0x00: MOVBS(opcode); break; + case 0x01: MOVWS(opcode); break; + case 0x02: MOVLS(opcode); break; + case 0x03: NOP(opcode); break; + case 0x04: MOVBM(opcode); break; + case 0x05: MOVWM(opcode); break; + case 0x06: MOVLM(opcode); break; + case 0x07: DIV0S(opcode); break; + case 0x08: TST(opcode); break; + case 0x09: AND(opcode); break; + case 0x0a: XOR(opcode); break; + case 0x0b: OR(opcode); break; + case 0x0c: CMPSTR(opcode); break; + case 0x0d: XTRCT(opcode); break; + case 0x0e: MULU(opcode); break; + case 0x0f: MULS(opcode); break; + } + break; + + case 0x3000: + switch(opcode & 0x0f) + { + case 0x00: CMPEQ(opcode); break; + case 0x01: NOP(opcode); break; + case 0x02: CMPHS(opcode); break; + case 0x03: CMPGE(opcode); break; + case 0x04: DIV1(opcode); break; + case 0x05: DMULU(opcode); break; + case 0x06: CMPHI(opcode); break; + case 0x07: CMPGT(opcode); break; + case 0x08: SUB(opcode); break; + case 0x09: NOP(opcode); break; + case 0x0a: SUBC(opcode); break; + case 0x0b: SUBV(opcode); break; + case 0x0c: ADD(opcode); break; + case 0x0d: DMULS(opcode); break; + case 0x0e: ADDC(opcode); break; + case 0x0f: ADDV(opcode); break; + } + break; + + case 0x4000: + execute_one_4000(opcode); + break; + + case 0x5000: + MOVLL4(opcode); + break; + + case 0x6000: + switch(opcode & 0x0f) + { + case 0x00: MOVBL(opcode); break; + case 0x01: MOVWL(opcode); break; + case 0x02: MOVLL(opcode); break; + case 0x03: MOV(opcode); break; + case 0x04: MOVBP(opcode); break; + case 0x05: MOVWP(opcode); break; + case 0x06: MOVLP(opcode); break; + case 0x07: NOT(opcode); break; + case 0x08: SWAPB(opcode); break; + case 0x09: SWAPW(opcode); break; + case 0x0a: NEGC(opcode); break; + case 0x0b: NEG(opcode); break; + case 0x0c: EXTUB(opcode); break; + case 0x0d: EXTUW(opcode); break; + case 0x0e: EXTSB(opcode); break; + case 0x0f: EXTSW(opcode); break; + } + break; + + case 0x7000: + ADDI(opcode); + break; + + case 0x8000: + switch((opcode >> 8) & 0x0f) + { + case 0x00: MOVBS4(opcode); break; + case 0x01: MOVWS4(opcode); break; + case 0x02: NOP(opcode); break; + case 0x03: NOP(opcode); break; + case 0x04: MOVBL4(opcode); break; + case 0x05: MOVWL4(opcode); break; + case 0x06: NOP(opcode); break; + case 0x07: NOP(opcode); break; + case 0x08: CMPIM(opcode); break; + case 0x09: BT(opcode); break; + case 0x0a: NOP(opcode); break; + case 0x0b: BF(opcode); break; + case 0x0c: NOP(opcode); break; + case 0x0d: BTS(opcode); break; + case 0x0e: NOP(opcode); break; + case 0x0f: BFS(opcode); break; + } + break; + + case 0x9000: + MOVWI(opcode); + break; + + case 0xa000: + BRA(opcode); + break; + + case 0xb000: + BSR(opcode); + break; + + case 0xc000: + switch((opcode >> 8) & 0x0f) + { + case 0x00: MOVBSG(opcode); break; + case 0x01: MOVWSG(opcode); break; + case 0x02: MOVLSG(opcode); break; + case 0x03: TRAPA(opcode); break; + case 0x04: MOVBLG(opcode); break; + case 0x05: MOVWLG(opcode); break; + case 0x06: MOVLLG(opcode); break; + case 0x07: MOVA(opcode); break; + case 0x08: TSTI(opcode); break; + case 0x09: ANDI(opcode); break; + case 0x0a: XORI(opcode); break; + case 0x0b: ORI(opcode); break; + case 0x0c: TSTM(opcode); break; + case 0x0d: ANDM(opcode); break; + case 0x0e: XORM(opcode); break; + case 0x0f: ORM(opcode); break; + } + break; + + case 0xd000: + MOVLI(opcode); + break; + + case 0xe000: + MOVI(opcode); + break; + + case 0xf000: + switch(opcode & 0x0f) + { + case 0x00: FADD(opcode); break; + case 0x01: FSUB(opcode); break; + case 0x02: FMUL(opcode); break; + case 0x03: FDIV(opcode); break; + case 0x04: FCMP_EQ(opcode); break; + case 0x05: FCMP_GT(opcode); break; + case 0x06: FMOVS0FR(opcode); break; + case 0x07: FMOVFRS0(opcode); break; + case 0x08: FMOVMRFR(opcode); break; + case 0x09: FMOVMRIFR(opcode); break; + case 0x0a: FMOVFRMR(opcode); break; + case 0x0b: FMOVFRMDR(opcode); break; + case 0x0c: FMOVFR(opcode); break; + case 0x0d: op1111_0x13(opcode); break; + case 0x0e: FMAC(opcode); break; + case 0x0f: dbreak(opcode); break; + } + break; + } +} + + static inline void sh4_check_pending_irq(/*const char *message*/) // look for highest priority active exception and handle it + { + int a,irq,z; + + irq = 0; + z = -1; + for (a=0;a <= SH4_INTC_ROVI;a++) + { + if (m_exception_requesting[a]) + { + if ((int)m_exception_priority[a] > z) + { + z = m_exception_priority[a]; + irq = a; + } + } + } + if (z >= 0) + { + sh4_exception(/*message, */irq); + } + } + + +int Sh3Run(int cycles) +{ + m_sh4_icount = cycles; + sh3_end_run = 0; + + if (m_cpu_off) + { + m_sh4_icount = 0; + sh3_total_cycles += cycles; + return cycles; + } + + do + { + INT32 tot_cyc_start = sh3_total_cycles; + if (m_delay) + { + const UINT16 opcode = sh3_cpu_readop16((UINT32)(m_delay & AM)); + + //debugger_instruction_hook(this, m_delay & AM); + + m_delay = 0; + m_ppc = m_pc; + + execute_one(opcode); + + + if (m_test_irq && !m_delay) + { + sh4_check_pending_irq(/*"mame_sh4_execute"*/); + } + + + } + else + { + const UINT16 opcode = sh3_cpu_readop16((UINT32)(m_pc & AM)); + + //debugger_instruction_hook(this, m_pc & AM); + + m_pc += 2; + m_ppc = m_pc; + + execute_one(opcode); + + if (m_test_irq && !m_delay) + { + sh4_check_pending_irq(/*"mame_sh4_execute"*/); + } + } + m_sh4_icount-=1; + sh3_total_cycles += 1; + + if (timer_granularity == 0) { + sh4_run_timers((sh3_total_cycles - tot_cyc_start)); + } + } while( m_sh4_icount > 0 && !sh3_end_run ); + + cycles = cycles - m_sh4_icount; + + if (timer_granularity) { + sh4_run_timers(cycles); + } + + m_sh4_icount = 0; + + return cycles; +} + + +#if 0 +void device_start() +{ + for (int i=0; i<3; i++) + { + m_timer[i] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh4_timer_callback), this)); + m_timer[i]->adjust(attotime::never, i); + } + + for (int i=0; i<4; i++) + { + m_dma_timer[i] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh4_dmac_callback), this)); + m_dma_timer[i]->adjust(attotime::never, i); + } + + m_refresh_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh4_refresh_timer_callback), this)); + m_refresh_timer->adjust(attotime::never); + m_refresh_timer_base = 0; + + m_rtc_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh4_rtc_timer_callback), this)); + m_rtc_timer->adjust(attotime::never); + + sh4_parse_configuration(); + + m_internal = &space(AS_PROGRAM); + m_program = &space(AS_PROGRAM); + m_io = &space(AS_IO); + m_direct = &m_program->direct(); + sh4_default_exception_priorities(); + m_irln = 15; + m_test_irq = 0; + + save_item(NAME(m_pc)); + save_item(NAME(m_r[15])); + save_item(NAME(m_sr)); + save_item(NAME(m_pr)); + save_item(NAME(m_gbr)); + save_item(NAME(m_vbr)); + save_item(NAME(m_mach)); + save_item(NAME(m_macl)); + save_item(NAME(m_spc)); + save_item(NAME(m_ssr)); + save_item(NAME(m_sgr)); + save_item(NAME(m_fpscr)); + save_item(NAME(m_r[ 0])); + save_item(NAME(m_r[ 1])); + save_item(NAME(m_r[ 2])); + save_item(NAME(m_r[ 3])); + save_item(NAME(m_r[ 4])); + save_item(NAME(m_r[ 5])); + save_item(NAME(m_r[ 6])); + save_item(NAME(m_r[ 7])); + save_item(NAME(m_r[ 8])); + save_item(NAME(m_r[ 9])); + save_item(NAME(m_r[10])); + save_item(NAME(m_r[11])); + save_item(NAME(m_r[12])); + save_item(NAME(m_r[13])); + save_item(NAME(m_r[14])); + save_item(NAME(m_fr[ 0])); + save_item(NAME(m_fr[ 1])); + save_item(NAME(m_fr[ 2])); + save_item(NAME(m_fr[ 3])); + save_item(NAME(m_fr[ 4])); + save_item(NAME(m_fr[ 5])); + save_item(NAME(m_fr[ 6])); + save_item(NAME(m_fr[ 7])); + save_item(NAME(m_fr[ 8])); + save_item(NAME(m_fr[ 9])); + save_item(NAME(m_fr[10])); + save_item(NAME(m_fr[11])); + save_item(NAME(m_fr[12])); + save_item(NAME(m_fr[13])); + save_item(NAME(m_fr[14])); + save_item(NAME(m_fr[15])); + save_item(NAME(m_xf[ 0])); + save_item(NAME(m_xf[ 1])); + save_item(NAME(m_xf[ 2])); + save_item(NAME(m_xf[ 3])); + save_item(NAME(m_xf[ 4])); + save_item(NAME(m_xf[ 5])); + save_item(NAME(m_xf[ 6])); + save_item(NAME(m_xf[ 7])); + save_item(NAME(m_xf[ 8])); + save_item(NAME(m_xf[ 9])); + save_item(NAME(m_xf[10])); + save_item(NAME(m_xf[11])); + save_item(NAME(m_xf[12])); + save_item(NAME(m_xf[13])); + save_item(NAME(m_xf[14])); + save_item(NAME(m_xf[15])); + save_item(NAME(m_ea)); + save_item(NAME(m_fpul)); + save_item(NAME(m_dbr)); + save_item(NAME(m_exception_priority)); + save_item(NAME(m_exception_requesting)); + + save_item(NAME(m_SH4_TSTR)); + save_item(NAME(m_SH4_TCNT0)); + save_item(NAME(m_SH4_TCNT1)); + save_item(NAME(m_SH4_TCNT2)); + save_item(NAME(m_SH4_TCR0)); + save_item(NAME(m_SH4_TCR1)); + save_item(NAME(m_SH4_TCR2)); + save_item(NAME(m_SH4_TCOR0)); + save_item(NAME(m_SH4_TCOR1)); + save_item(NAME(m_SH4_TCOR2)); + save_item(NAME(m_SH4_TOCR)); + save_item(NAME(m_SH4_TCPR2)); + + save_item(NAME(m_SH4_IPRA)); + + save_item(NAME(m_SH4_IPRC)); + + // Debugger state + + state_add(SH4_PC, "PC", m_pc).formatstr("%08X").callimport(); + state_add(SH4_SR, "SR", m_sr).formatstr("%08X").callimport(); + state_add(SH4_PR, "PR", m_pr).formatstr("%08X"); + state_add(SH4_GBR, "GBR", m_gbr).formatstr("%08X"); + state_add(SH4_VBR, "VBR", m_vbr).formatstr("%08X"); + state_add(SH4_DBR, "DBR", m_dbr).formatstr("%08X"); + state_add(SH4_MACH, "MACH", m_mach).formatstr("%08X"); + state_add(SH4_MACL, "MACL", m_macl).formatstr("%08X"); + state_add(SH4_R0, "R0", m_r[ 0]).formatstr("%08X"); + state_add(SH4_R1, "R1", m_r[ 1]).formatstr("%08X"); + state_add(SH4_R2, "R2", m_r[ 2]).formatstr("%08X"); + state_add(SH4_R3, "R3", m_r[ 3]).formatstr("%08X"); + state_add(SH4_R4, "R4", m_r[ 4]).formatstr("%08X"); + state_add(SH4_R5, "R5", m_r[ 5]).formatstr("%08X"); + state_add(SH4_R6, "R6", m_r[ 6]).formatstr("%08X"); + state_add(SH4_R7, "R7", m_r[ 7]).formatstr("%08X"); + state_add(SH4_R8, "R8", m_r[ 8]).formatstr("%08X"); + state_add(SH4_R9, "R9", m_r[ 9]).formatstr("%08X"); + state_add(SH4_R10, "R10", m_r[10]).formatstr("%08X"); + state_add(SH4_R11, "R11", m_r[11]).formatstr("%08X"); + state_add(SH4_R12, "R12", m_r[12]).formatstr("%08X"); + state_add(SH4_R13, "R13", m_r[13]).formatstr("%08X"); + state_add(SH4_R14, "R14", m_r[14]).formatstr("%08X"); + state_add(SH4_R15, "R15", m_r[15]).formatstr("%08X"); + state_add(SH4_EA, "EA", m_ea).formatstr("%08X"); + state_add(SH4_R0_BK0, "R0 BK 0", m_rbnk[0][0]).formatstr("%08X"); + state_add(SH4_R1_BK0, "R1 BK 0", m_rbnk[0][1]).formatstr("%08X"); + state_add(SH4_R2_BK0, "R2 BK 0", m_rbnk[0][2]).formatstr("%08X"); + state_add(SH4_R3_BK0, "R3 BK 0", m_rbnk[0][3]).formatstr("%08X"); + state_add(SH4_R4_BK0, "R4 BK 0", m_rbnk[0][4]).formatstr("%08X"); + state_add(SH4_R5_BK0, "R5 BK 0", m_rbnk[0][5]).formatstr("%08X"); + state_add(SH4_R6_BK0, "R6 BK 0", m_rbnk[0][6]).formatstr("%08X"); + state_add(SH4_R7_BK0, "R7 BK 0", m_rbnk[0][7]).formatstr("%08X"); + state_add(SH4_R0_BK1, "R0 BK 1", m_rbnk[1][0]).formatstr("%08X"); + state_add(SH4_R1_BK1, "R1 BK 1", m_rbnk[1][1]).formatstr("%08X"); + state_add(SH4_R2_BK1, "R2 BK 1", m_rbnk[1][2]).formatstr("%08X"); + state_add(SH4_R3_BK1, "R3 BK 1", m_rbnk[1][3]).formatstr("%08X"); + state_add(SH4_R4_BK1, "R4 BK 1", m_rbnk[1][4]).formatstr("%08X"); + state_add(SH4_R5_BK1, "R5 BK 1", m_rbnk[1][5]).formatstr("%08X"); + state_add(SH4_R6_BK1, "R6 BK 1", m_rbnk[1][6]).formatstr("%08X"); + state_add(SH4_R7_BK1, "R7 BK 1", m_rbnk[1][7]).formatstr("%08X"); + state_add(SH4_SPC, "SPC", m_spc).formatstr("%08X"); + state_add(SH4_SSR, "SSR", m_ssr).formatstr("%08X"); + state_add(SH4_SGR, "SGR", m_sgr).formatstr("%08X"); + state_add(SH4_FPSCR, "FPSCR", m_fpscr).formatstr("%08X"); + state_add(SH4_FPUL, "FPUL", m_fpul).formatstr("%08X"); + + state_add(SH4_FR0, "FR0", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR1, "FR1", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR2, "FR2", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR3, "FR3", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR4, "FR4", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR5, "FR5", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR6, "FR6", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR7, "FR7", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR8, "FR8", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR9, "FR9", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR10, "FR10", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR11, "FR11", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR12, "FR12", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR13, "FR13", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR14, "FR14", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR15, "FR15", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF0, "XF0", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF1, "XF1", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF2, "XF2", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF3, "XF3", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF4, "XF4", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF5, "XF5", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF6, "XF6", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF7, "XF7", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF8, "XF8", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF9, "XF9", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF10, "XF10", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF11, "XF11", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF12, "XF12", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF13, "XF13", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF14, "XF14", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF15, "XF15", m_debugger_temp).callimport().formatstr("%25s"); + + state_add(STATE_GENPC, "GENPC", m_debugger_temp).callimport().callexport().noshow(); + state_add(STATE_GENSP, "GENSP", m_r[15]).noshow(); + state_add(STATE_GENPCBASE, "GENPCBASE", m_ppc).noshow(); + state_add(STATE_GENFLAGS, "GENFLAGS", m_sr).formatstr("%20s").noshow(); + + m_icountptr = &m_sh4_icount; +} + +void state_import(const device_state_entry &entry) +{ +#ifdef LSB_FIRST + UINT8 fpu_xor = m_fpu_pr; +#else + UINT8 fpu_xor = 0; +#endif + + switch (entry.index()) + { + case STATE_GENPC: + m_pc = m_debugger_temp; + case SH4_PC: + m_delay = 0; + break; + + case SH4_SR: + sh4_exception_recompute(); + sh4_check_pending_irq("sh4_set_info"); + break; + + case SH4_FR0: + m_fr[0 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR1: + m_fr[1 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR2: + m_fr[2 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR3: + m_fr[3 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR4: + m_fr[4 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR5: + m_fr[5 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR6: + m_fr[6 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR7: + m_fr[7 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR8: + m_fr[8 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR9: + m_fr[9 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR10: + m_fr[10 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR11: + m_fr[11 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR12: + m_fr[12 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR13: + m_fr[13 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR14: + m_fr[14 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR15: + m_fr[15 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF0: + m_xf[0 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF1: + m_xf[1 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF2: + m_xf[2 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF3: + m_xf[3 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF4: + m_xf[4 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF5: + m_xf[5 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF6: + m_xf[6 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF7: + m_xf[7 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF8: + m_xf[8 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF9: + m_xf[9 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF10: + m_xf[10 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF11: + m_xf[11 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF12: + m_xf[12 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF13: + m_xf[13 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF14: + m_xf[14 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF15: + m_xf[15 ^ fpu_xor] = m_debugger_temp; + break; + } +} + +void state_export(const device_state_entry &entry) +{ + switch (entry.index()) + { + case STATE_GENPC: + m_debugger_temp = (m_delay) ? (m_delay & AM) : (m_pc & AM); + break; + } +} + +void state_string_export(const device_state_entry &entry, astring &string) +{ +#ifdef LSB_FIRST + UINT8 fpu_xor = m_fpu_pr; +#else + UINT8 fpu_xor = 0; +#endif + + switch (entry.index()) + { + case STATE_GENFLAGS: + string.printf("%s%s%s%s%c%c%d%c%c", + m_sr & MD ? "MD ":" ", + m_sr & sRB ? "RB ":" ", + m_sr & BL ? "BL ":" ", + m_sr & FD ? "FD ":" ", + m_sr & M ? 'M':'.', + m_sr & Q ? 'Q':'.', + (m_sr & I) >> 4, + m_sr & S ? 'S':'.', + m_sr & T ? 'T':'.'); + break; + + case SH4_FR0: + string.printf("%08X %f", m_fr[0 ^ fpu_xor], (double)FP_RFS(0 ^ fpu_xor)); + break; + + case SH4_FR1: + string.printf("%08X %f", m_fr[1 ^ fpu_xor], (double)FP_RFS(1 ^ fpu_xor)); + break; + + case SH4_FR2: + string.printf("%08X %f", m_fr[2 ^ fpu_xor], (double)FP_RFS(2 ^ fpu_xor)); + break; + + case SH4_FR3: + string.printf("%08X %f", m_fr[3 ^ fpu_xor], (double)FP_RFS(3 ^ fpu_xor)); + break; + + case SH4_FR4: + string.printf("%08X %f", m_fr[4 ^ fpu_xor], (double)FP_RFS(4 ^ fpu_xor)); + break; + + case SH4_FR5: + string.printf("%08X %f", m_fr[5 ^ fpu_xor], (double)FP_RFS(5 ^ fpu_xor)); + break; + + case SH4_FR6: + string.printf("%08X %f", m_fr[6 ^ fpu_xor], (double)FP_RFS(6 ^ fpu_xor)); + break; + + case SH4_FR7: + string.printf("%08X %f", m_fr[7 ^ fpu_xor], (double)FP_RFS(7 ^ fpu_xor)); + break; + + case SH4_FR8: + string.printf("%08X %f", m_fr[8 ^ fpu_xor], (double)FP_RFS(8 ^ fpu_xor)); + break; + + case SH4_FR9: + string.printf("%08X %f", m_fr[9 ^ fpu_xor], (double)FP_RFS(9 ^ fpu_xor)); + break; + + case SH4_FR10: + string.printf("%08X %f", m_fr[10 ^ fpu_xor], (double)FP_RFS(10 ^ fpu_xor)); + break; + + case SH4_FR11: + string.printf("%08X %f", m_fr[11 ^ fpu_xor], (double)FP_RFS(11 ^ fpu_xor)); + break; + + case SH4_FR12: + string.printf("%08X %f", m_fr[12 ^ fpu_xor], (double)FP_RFS(12 ^ fpu_xor)); + break; + + case SH4_FR13: + string.printf("%08X %f", m_fr[13 ^ fpu_xor], (double)FP_RFS(13 ^ fpu_xor)); + break; + + case SH4_FR14: + string.printf("%08X %f", m_fr[14 ^ fpu_xor], (double)FP_RFS(14 ^ fpu_xor)); + break; + + case SH4_FR15: + string.printf("%08X %f", m_fr[15 ^ fpu_xor], (double)FP_RFS(15 ^ fpu_xor)); + break; + + case SH4_XF0: + string.printf("%08X %f", m_xf[0 ^ fpu_xor], (double)FP_XFS(0 ^ fpu_xor)); + break; + + case SH4_XF1: + string.printf("%08X %f", m_xf[1 ^ fpu_xor], (double)FP_XFS(1 ^ fpu_xor)); + break; + + case SH4_XF2: + string.printf("%08X %f", m_xf[2 ^ fpu_xor], (double)FP_XFS(2 ^ fpu_xor)); + break; + + case SH4_XF3: + string.printf("%08X %f", m_xf[3 ^ fpu_xor], (double)FP_XFS(3 ^ fpu_xor)); + break; + + case SH4_XF4: + string.printf("%08X %f", m_xf[4 ^ fpu_xor], (double)FP_XFS(4 ^ fpu_xor)); + break; + + case SH4_XF5: + string.printf("%08X %f", m_xf[5 ^ fpu_xor], (double)FP_XFS(5 ^ fpu_xor)); + break; + + case SH4_XF6: + string.printf("%08X %f", m_xf[6 ^ fpu_xor], (double)FP_XFS(6 ^ fpu_xor)); + break; + + case SH4_XF7: + string.printf("%08X %f", m_xf[7 ^ fpu_xor], (double)FP_XFS(7 ^ fpu_xor)); + break; + + case SH4_XF8: + string.printf("%08X %f", m_xf[8 ^ fpu_xor], (double)FP_XFS(8 ^ fpu_xor)); + break; + + case SH4_XF9: + string.printf("%08X %f", m_xf[9 ^ fpu_xor], (double)FP_XFS(9 ^ fpu_xor)); + break; + + case SH4_XF10: + string.printf("%08X %f", m_xf[10 ^ fpu_xor], (double)FP_XFS(10 ^ fpu_xor)); + break; + + case SH4_XF11: + string.printf("%08X %f", m_xf[11 ^ fpu_xor], (double)FP_XFS(11 ^ fpu_xor)); + break; + + case SH4_XF12: + string.printf("%08X %f", m_xf[12 ^ fpu_xor], (double)FP_XFS(12 ^ fpu_xor)); + break; + + case SH4_XF13: + string.printf("%08X %f", m_xf[13 ^ fpu_xor], (double)FP_XFS(13 ^ fpu_xor)); + break; + + case SH4_XF14: + string.printf("%08X %f", m_xf[14 ^ fpu_xor], (double)FP_XFS(14 ^ fpu_xor)); + break; + + case SH4_XF15: + string.printf("%08X %f", m_xf[15 ^ fpu_xor], (double)FP_XFS(15 ^ fpu_xor)); + break; + + } +} + + +void sh4_set_ftcsr_callback(sh4_ftcsr_callback callback) +{ + m_ftcsr_read_callback = callback; +} +// unnecessary -dink +#endif diff --git a/src/cpu/sh4/sh4.h b/src/cpu/sh4/sh4.h new file mode 100644 index 000000000..a895f1bdd --- /dev/null +++ b/src/cpu/sh4/sh4.h @@ -0,0 +1,817 @@ +/***************************************************************************** + * + * sh4->h + * Portable Hitachi SH-4 (SH7750 family) emulator interface + * + * By R. Belmont, based on sh2.c by Juergen Buchmueller, Mariusz Wojcieszek, + * Olivier Galibert, Sylvain Glaize, and James Forshaw. + * + *****************************************************************************/ + +#ifndef __SH4_H__ +#define __SH4_H__ + + +#define SH4_INT_NONE -1 +enum +{ + SH4_IRL0=0, SH4_IRL1, SH4_IRL2, SH4_IRL3, SH4_IRLn +}; + +enum +{ + SH4_PC=1, SH4_SR, SH4_PR, SH4_GBR, SH4_VBR, SH4_DBR, SH4_MACH, SH4_MACL, + SH4_R0, SH4_R1, SH4_R2, SH4_R3, SH4_R4, SH4_R5, SH4_R6, SH4_R7, + SH4_R8, SH4_R9, SH4_R10, SH4_R11, SH4_R12, SH4_R13, SH4_R14, SH4_R15, SH4_EA, + SH4_R0_BK0, SH4_R1_BK0, SH4_R2_BK0, SH4_R3_BK0, SH4_R4_BK0, SH4_R5_BK0, SH4_R6_BK0, SH4_R7_BK0, + SH4_R0_BK1, SH4_R1_BK1, SH4_R2_BK1, SH4_R3_BK1, SH4_R4_BK1, SH4_R5_BK1, SH4_R6_BK1, SH4_R7_BK1, + SH4_SPC, SH4_SSR, SH4_SGR, SH4_FPSCR, SH4_FPUL, SH4_FR0, SH4_FR1, SH4_FR2, SH4_FR3, SH4_FR4, SH4_FR5, + SH4_FR6, SH4_FR7, SH4_FR8, SH4_FR9, SH4_FR10, SH4_FR11, SH4_FR12, SH4_FR13, SH4_FR14, SH4_FR15, + SH4_XF0, SH4_XF1, SH4_XF2, SH4_XF3, SH4_XF4, SH4_XF5, SH4_XF6, SH4_XF7, + SH4_XF8, SH4_XF9, SH4_XF10, SH4_XF11, SH4_XF12, SH4_XF13, SH4_XF14, SH4_XF15 +}; + +enum +{ + SH4_INTC_NMI=23, + SH4_INTC_IRLn0, + SH4_INTC_IRLn1, + SH4_INTC_IRLn2, + SH4_INTC_IRLn3, + SH4_INTC_IRLn4, + SH4_INTC_IRLn5, + SH4_INTC_IRLn6, + SH4_INTC_IRLn7, + SH4_INTC_IRLn8, + SH4_INTC_IRLn9, + SH4_INTC_IRLnA, + SH4_INTC_IRLnB, + SH4_INTC_IRLnC, + SH4_INTC_IRLnD, + SH4_INTC_IRLnE, + + SH4_INTC_IRL0, + SH4_INTC_IRL1, + SH4_INTC_IRL2, + SH4_INTC_IRL3, + + SH4_INTC_HUDI, + SH4_INTC_GPOI, + + SH4_INTC_DMTE0, + SH4_INTC_DMTE1, + SH4_INTC_DMTE2, + SH4_INTC_DMTE3, + SH4_INTC_DMTE4, + SH4_INTC_DMTE5, + SH4_INTC_DMTE6, + SH4_INTC_DMTE7, + + SH4_INTC_DMAE, + + SH4_INTC_TUNI3, + SH4_INTC_TUNI4, + SH4_INTC_TUNI0, + SH4_INTC_TUNI1, + SH4_INTC_TUNI2, + SH4_INTC_TICPI2, + SH4_INTC_ATI, + SH4_INTC_PRI, + SH4_INTC_CUI, + SH4_INTC_SCI1ERI, + SH4_INTC_SCI1RXI, + + SH4_INTC_SCI1TXI, + SH4_INTC_SCI1TEI, + SH4_INTC_SCIFERI, + SH4_INTC_SCIFRXI, + SH4_INTC_SCIFBRI, + SH4_INTC_SCIFTXI, + SH4_INTC_ITI, + SH4_INTC_RCMI, + SH4_INTC_ROVI +}; + +#define SH4_FPU_PZERO 0 +#define SH4_FPU_NZERO 1 +#define SH4_FPU_DENORM 2 +#define SH4_FPU_NORM 3 +#define SH4_FPU_PINF 4 +#define SH4_FPU_NINF 5 +#define SH4_FPU_qNaN 6 +#define SH4_FPU_sNaN 7 + +enum +{ + SH4_IOPORT_16=8*0, + SH4_IOPORT_4=8*1, + SH4_IOPORT_DMA=8*2, + // future use + SH4_IOPORT_SCI=8*3, + SH4_IOPORT_SCIF=8*4 +}; + +struct sh4_device_dma +{ + UINT32 length; + UINT32 size; + void *buffer; + int channel; +}; + +struct sh4_ddt_dma +{ + UINT32 source; + UINT32 length; + UINT32 size; + UINT32 destination; + void *buffer; + int direction; + int channel; + int mode; +}; + +typedef void (*sh4_ftcsr_callback)(UINT32); + +static UINT32 sh3_internal_r(UINT32 offset, UINT32 mem_mask); +static void sh3_internal_w(UINT32 offset, UINT32 data, UINT32 mem_mask); +static UINT32 sh3_internal_high_r(UINT32 offset, UINT32 mem_mask); +static void sh3_internal_high_w(UINT32 offset, UINT32 data, UINT32 mem_mask); +static void sh4_timer_callback(int param); +static void sh4_parse_configuration(); +static void sh4_default_exception_priorities(); + + + +static void sh4_handle_tocr_addr_w(UINT32 data, UINT32 mem_mask); +static UINT32 sh4_handle_tcnt0_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_tcnt1_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_tcnt2_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_tcor0_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_tcor1_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_tcor2_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_tcr0_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_tcr1_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_tcr2_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_tstr_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_tocr_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_tcpr2_addr_r(UINT32 mem_mask); +static void sh4_handle_tstr_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_tcr0_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_tcr1_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_tcr2_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_tcor0_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_tcor1_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_tcor2_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_tcnt0_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_tcnt1_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_tcnt2_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_tocr_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_tcpr2_addr_w(UINT32 data, UINT32 mem_mask); + +#endif + +#if 0 +#define MCFG_SH4_MD0(_md0) \ + sh34_base_device::set_md0(*device, _md0); + +#define MCFG_SH4_MD1(_md1) \ + sh34_base_device::set_md1(*device, _md1); + +#define MCFG_SH4_MD2(_md2) \ + sh34_base_device::set_md2(*device, _md2); + +#define MCFG_SH4_MD3(_md3) \ + sh34_base_device::set_md3(*device, _md3); + +#define MCFG_SH4_MD4(_md4) \ + sh34_base_device::set_md4(*device, _md4); + +#define MCFG_SH4_MD5(_md5) \ + sh34_base_device::set_md5(*device, _md5); + +#define MCFG_SH4_MD6(_md6) \ + sh34_base_device::set_md6(*device, _md6); + +#define MCFG_SH4_MD7(_md7) \ + sh34_base_device::set_md7(*device, _md7); + +#define MCFG_SH4_MD8(_md8) \ + sh34_base_device::set_md8(*device, _md8); + +#define MCFG_SH4_CLOCK(_clock) \ + sh34_base_device::set_sh4_clock(*device, _clock); + + +class sh34_base_device : public cpu_device +{ +public: + // construction/destruction + sh34_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness, address_map_constructor internal); + + static void set_md0(device_t &device, int md0) { downcast(device).c_md0 = md0; } + static void set_md1(device_t &device, int md0) { downcast(device).c_md1 = md0; } + static void set_md2(device_t &device, int md0) { downcast(device).c_md2 = md0; } + static void set_md3(device_t &device, int md0) { downcast(device).c_md3 = md0; } + static void set_md4(device_t &device, int md0) { downcast(device).c_md4 = md0; } + static void set_md5(device_t &device, int md0) { downcast(device).c_md5 = md0; } + static void set_md6(device_t &device, int md0) { downcast(device).c_md6 = md0; } + static void set_md7(device_t &device, int md0) { downcast(device).c_md7 = md0; } + static void set_md8(device_t &device, int md0) { downcast(device).c_md8 = md0; } + static void set_sh4_clock(device_t &device, int clock) { downcast(device).c_clock = clock; } + + TIMER_CALLBACK_MEMBER( sh4_refresh_timer_callback ); + TIMER_CALLBACK_MEMBER( sh4_rtc_timer_callback ); + TIMER_CALLBACK_MEMBER( sh4_timer_callback ); + TIMER_CALLBACK_MEMBER( sh4_dmac_callback ); + + void sh4_set_frt_input(int state); + void sh4_set_irln_input(int value); + void sh4_set_ftcsr_callback(sh4_ftcsr_callback callback); + int sh4_dma_data(struct sh4_device_dma *s); + void sh4_dma_ddt(struct sh4_ddt_dma *s); + +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const { return 1; } + virtual UINT32 execute_max_cycles() const { return 4; } + virtual UINT32 execute_input_lines() const { return 5; } + virtual void execute_run(); + virtual void execute_set_input(int inputnum, int state); + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ((spacenum == AS_IO) ? &m_io_config : NULL); } + + // device_state_interface overrides + virtual void state_import(const device_state_entry &entry); + virtual void state_export(const device_state_entry &entry); + virtual void state_string_export(const device_state_entry &entry, astring &string); + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const { return 2; } + virtual UINT32 disasm_max_opcode_bytes() const { return 2; } + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + +protected: + address_space_config m_program_config; + address_space_config m_io_config; + + int c_md2; + int c_md1; + int c_md0; + int c_md6; + int c_md4; + int c_md3; + int c_md5; + int c_md7; + int c_md8; + int c_clock; + + UINT32 m_ppc; + UINT32 m_pc; + UINT32 m_spc; + UINT32 m_pr; + UINT32 m_sr; + UINT32 m_ssr; + UINT32 m_gbr; + UINT32 m_vbr; + UINT32 m_mach; + UINT32 m_macl; + UINT32 m_r[16]; + UINT32 m_rbnk[2][8]; + UINT32 m_sgr; + UINT32 m_fr[16]; + UINT32 m_xf[16]; + UINT32 m_ea; + UINT32 m_delay; + UINT32 m_cpu_off; + UINT32 m_pending_irq; + UINT32 m_test_irq; + UINT32 m_fpscr; + UINT32 m_fpul; + UINT32 m_dbr; + + UINT32 m_exception_priority[128]; + int m_exception_requesting[128]; + + INT8 m_irq_line_state[17]; + address_space *m_internal; + address_space *m_program; + direct_read_data *m_direct; + address_space *m_io; + + // sh4 internal + UINT32 m_m[16384]; + + // timer regs handled manually for reuse + UINT32 m_SH4_TSTR; + UINT32 m_SH4_TCNT0; + UINT32 m_SH4_TCNT1; + UINT32 m_SH4_TCNT2; + UINT32 m_SH4_TCR0; + UINT32 m_SH4_TCR1; + UINT32 m_SH4_TCR2; + UINT32 m_SH4_TCOR0; + UINT32 m_SH4_TCOR1; + UINT32 m_SH4_TCOR2; + UINT32 m_SH4_TOCR; + UINT32 m_SH4_TCPR2; + + // INTC regs + UINT32 m_SH4_IPRA; + + UINT32 m_SH4_IPRC; + + // DMAC regs + UINT32 m_SH4_SAR0; + UINT32 m_SH4_SAR1; + UINT32 m_SH4_SAR2; + UINT32 m_SH4_SAR3; + + UINT32 m_SH4_DAR0; + UINT32 m_SH4_DAR1; + UINT32 m_SH4_DAR2; + UINT32 m_SH4_DAR3; + + UINT32 m_SH4_CHCR0; + UINT32 m_SH4_CHCR1; + UINT32 m_SH4_CHCR2; + UINT32 m_SH4_CHCR3; + + UINT32 m_SH4_DMATCR0; + UINT32 m_SH4_DMATCR1; + UINT32 m_SH4_DMATCR2; + UINT32 m_SH4_DMATCR3; + + UINT32 m_SH4_DMAOR; + + INT8 m_nmi_line_state; + + UINT8 m_sleep_mode; + + int m_frt_input; + int m_irln; + int m_internal_irq_level; + int m_internal_irq_vector; + + emu_timer *m_dma_timer[4]; + emu_timer *m_refresh_timer; + emu_timer *m_rtc_timer; + emu_timer *m_timer[3]; + UINT32 m_refresh_timer_base; + int m_dma_timer_active[4]; + UINT32 m_dma_source[4]; + UINT32 m_dma_destination[4]; + UINT32 m_dma_count[4]; + int m_dma_wordsize[4]; + int m_dma_source_increment[4]; + int m_dma_destination_increment[4]; + int m_dma_mode[4]; + + int m_sh4_icount; + int m_is_slave; + int m_cpu_clock; + int m_bus_clock; + int m_pm_clock; + int m_fpu_sz; + int m_fpu_pr; + int m_ioport16_pullup; + int m_ioport16_direction; + int m_ioport4_pullup; + int m_ioport4_direction; + + void (*m_ftcsr_read_callback)(UINT32 data); + + /* This MMU simulation is good for the simple remap used on Naomi GD-ROM SQ access *ONLY* */ + UINT32 m_sh4_tlb_address[64]; + UINT32 m_sh4_tlb_data[64]; + UINT8 m_sh4_mmu_enabled; + + int m_cpu_type; + + // sh3 internal + UINT32 m_sh3internal_upper[0x3000/4]; + UINT32 m_sh3internal_lower[0x1000]; + + UINT64 m_debugger_temp; + + + void execute_one_0000(const UINT16 opcode); + void execute_one_4000(const UINT16 opcode); + void execute_one(const UINT16 opcode); + inline void sh4_check_pending_irq(const char *message) // look for highest priority active exception and handle it + { + int a,irq,z; + + irq = 0; + z = -1; + for (a=0;a <= SH4_INTC_ROVI;a++) + { + if (m_exception_requesting[a]) + { + if ((int)m_exception_priority[a] > z) + { + z = m_exception_priority[a]; + irq = a; + } + } + } + if (z >= 0) + { + sh4_exception(message, irq); + } + } + + void TODO(const UINT16 opcode); + void WB(offs_t A, UINT8 V); + void WW(offs_t A, UINT16 V); + void WL(offs_t A, UINT32 V); + void ADD(const UINT16 opcode); + void ADDI(const UINT16 opcode); + void ADDC(const UINT16 opcode); + void ADDV(const UINT16 opcode); + void AND(const UINT16 opcode); + void ANDI(const UINT16 opcode); + void ANDM(const UINT16 opcode); + void BF(const UINT16 opcode); + void BFS(const UINT16 opcode); + void BRA(const UINT16 opcode); + void BRAF(const UINT16 opcode); + void BSR(const UINT16 opcode); + void BSRF(const UINT16 opcode); + void BT(const UINT16 opcode); + void BTS(const UINT16 opcode); + void CLRMAC(const UINT16 opcode); + void CLRT(const UINT16 opcode); + void CMPEQ(const UINT16 opcode); + void CMPGE(const UINT16 opcode); + void CMPGT(const UINT16 opcode); + void CMPHI(const UINT16 opcode); + void CMPHS(const UINT16 opcode); + void CMPPL(const UINT16 opcode); + void CMPPZ(const UINT16 opcode); + void CMPSTR(const UINT16 opcode); + void CMPIM(const UINT16 opcode); + void DIV0S(const UINT16 opcode); + void DIV0U(const UINT16 opcode); + void DIV1(const UINT16 opcode); + void DMULS(const UINT16 opcode); + void DMULU(const UINT16 opcode); + void DT(const UINT16 opcode); + void EXTSB(const UINT16 opcode); + void EXTSW(const UINT16 opcode); + void EXTUB(const UINT16 opcode); + void EXTUW(const UINT16 opcode); + void JMP(const UINT16 opcode); + void JSR(const UINT16 opcode); + void LDCSR(const UINT16 opcode); + void LDCGBR(const UINT16 opcode); + void LDCVBR(const UINT16 opcode); + void LDCMSR(const UINT16 opcode); + void LDCMGBR(const UINT16 opcode); + void LDCMVBR(const UINT16 opcode); + void LDSMACH(const UINT16 opcode); + void LDSMACL(const UINT16 opcode); + void LDSPR(const UINT16 opcode); + void LDSMMACH(const UINT16 opcode); + void LDSMMACL(const UINT16 opcode); + void LDSMPR(const UINT16 opcode); + void MAC_L(const UINT16 opcode); + void MAC_W(const UINT16 opcode); + void MOV(const UINT16 opcode); + void MOVBS(const UINT16 opcode); + void MOVWS(const UINT16 opcode); + void MOVLS(const UINT16 opcode); + void MOVBL(const UINT16 opcode); + void MOVWL(const UINT16 opcode); + void MOVLL(const UINT16 opcode); + void MOVBM(const UINT16 opcode); + void MOVWM(const UINT16 opcode); + void MOVLM(const UINT16 opcode); + void MOVBP(const UINT16 opcode); + void MOVWP(const UINT16 opcode); + void MOVLP(const UINT16 opcode); + void MOVBS0(const UINT16 opcode); + void MOVWS0(const UINT16 opcode); + void MOVLS0(const UINT16 opcode); + void MOVBL0(const UINT16 opcode); + void MOVWL0(const UINT16 opcode); + void MOVLL0(const UINT16 opcode); + void MOVI(const UINT16 opcode); + void MOVWI(const UINT16 opcode); + void MOVLI(const UINT16 opcode); + void MOVBLG(const UINT16 opcode); + void MOVWLG(const UINT16 opcode); + void MOVLLG(const UINT16 opcode); + void MOVBSG(const UINT16 opcode); + void MOVWSG(const UINT16 opcode); + void MOVLSG(const UINT16 opcode); + void MOVBS4(const UINT16 opcode); + void MOVWS4(const UINT16 opcode); + void MOVLS4(const UINT16 opcode); + void MOVBL4(const UINT16 opcode); + void MOVWL4(const UINT16 opcode); + void MOVLL4(const UINT16 opcode); + void MOVA(const UINT16 opcode); + void MOVT(const UINT16 opcode); + void MULL(const UINT16 opcode); + void MULS(const UINT16 opcode); + void MULU(const UINT16 opcode); + void NEG(const UINT16 opcode); + void NEGC(const UINT16 opcode); + void NOP(const UINT16 opcode); + void NOT(const UINT16 opcode); + void OR(const UINT16 opcode); + void ORI(const UINT16 opcode); + void ORM(const UINT16 opcode); + void ROTCL(const UINT16 opcode); + void ROTCR(const UINT16 opcode); + void ROTL(const UINT16 opcode); + void ROTR(const UINT16 opcode); + void RTE(const UINT16 opcode); + void RTS(const UINT16 opcode); + void SETT(const UINT16 opcode); + void SHAL(const UINT16 opcode); + void SHAR(const UINT16 opcode); + void SHLL(const UINT16 opcode); + void SHLL2(const UINT16 opcode); + void SHLL8(const UINT16 opcode); + void SHLL16(const UINT16 opcode); + void SHLR(const UINT16 opcode); + void SHLR2(const UINT16 opcode); + void SHLR8(const UINT16 opcode); + void SHLR16(const UINT16 opcode); + void SLEEP(const UINT16 opcode); + void STCSR(const UINT16 opcode); + void STCGBR(const UINT16 opcode); + void STCVBR(const UINT16 opcode); + void STCMSR(const UINT16 opcode); + void STCMGBR(const UINT16 opcode); + void STCMVBR(const UINT16 opcode); + void STSMACH(const UINT16 opcode); + void STSMACL(const UINT16 opcode); + void STSPR(const UINT16 opcode); + void STSMMACH(const UINT16 opcode); + void STSMMACL(const UINT16 opcode); + void STSMPR(const UINT16 opcode); + void SUB(const UINT16 opcode); + void SUBC(const UINT16 opcode); + void SUBV(const UINT16 opcode); + void SWAPB(const UINT16 opcode); + void SWAPW(const UINT16 opcode); + void TAS(const UINT16 opcode); + void TRAPA(const UINT16 opcode); + void TST(const UINT16 opcode); + void TSTI(const UINT16 opcode); + void TSTM(const UINT16 opcode); + void XOR(const UINT16 opcode); + void XORI(const UINT16 opcode); + void XORM(const UINT16 opcode); + void XTRCT(const UINT16 opcode); + void STCSSR(const UINT16 opcode); + void STCSPC(const UINT16 opcode); + void STCSGR(const UINT16 opcode); + void STSFPUL(const UINT16 opcode); + void STSFPSCR(const UINT16 opcode); + void STCDBR(const UINT16 opcode); + void STCRBANK(const UINT16 opcode); + void STCMRBANK(const UINT16 opcode); + void MOVCAL(const UINT16 opcode); + void CLRS(const UINT16 opcode); + void SETS(const UINT16 opcode); + void STCMSGR(const UINT16 opcode); + void STSMFPUL(const UINT16 opcode); + void STSMFPSCR(const UINT16 opcode); + void STCMDBR(const UINT16 opcode); + void STCMSSR(const UINT16 opcode); + void STCMSPC(const UINT16 opcode); + void LDSMFPUL(const UINT16 opcode); + void LDSMFPSCR(const UINT16 opcode); + void LDCMDBR(const UINT16 opcode); + void LDCMRBANK(const UINT16 opcode); + void LDCMSSR(const UINT16 opcode); + void LDCMSPC(const UINT16 opcode); + void LDSFPUL(const UINT16 opcode); + void LDSFPSCR(const UINT16 opcode); + void LDCDBR(const UINT16 opcode); + void SHAD(const UINT16 opcode); + void SHLD(const UINT16 opcode); + void LDCRBANK(const UINT16 opcode); + void LDCSSR(const UINT16 opcode); + void LDCSPC(const UINT16 opcode); + void PREFM(const UINT16 opcode); + void FMOVMRIFR(const UINT16 opcode); + void FMOVFRMR(const UINT16 opcode); + void FMOVFRMDR(const UINT16 opcode); + void FMOVFRS0(const UINT16 opcode); + void FMOVS0FR(const UINT16 opcode); + void FMOVMRFR(const UINT16 opcode); + void FMOVFR(const UINT16 opcode); + void FLDI1(const UINT16 opcode); + void FLDI0(const UINT16 opcode); + void FLDS(const UINT16 opcode); + void FSTS(const UINT16 opcode); + void FRCHG(); + void FSCHG(); + void FTRC(const UINT16 opcode); + void FLOAT(const UINT16 opcode); + void FNEG(const UINT16 opcode); + void FABS(const UINT16 opcode); + void FCMP_EQ(const UINT16 opcode); + void FCMP_GT(const UINT16 opcode); + void FCNVDS(const UINT16 opcode); + void FCNVSD(const UINT16 opcode); + void FADD(const UINT16 opcode); + void FSUB(const UINT16 opcode); + void FMUL(const UINT16 opcode); + void FDIV(const UINT16 opcode); + void FMAC(const UINT16 opcode); + void FSQRT(const UINT16 opcode); + void FSRRA(const UINT16 opcode); + void FSSCA(const UINT16 opcode); + void FIPR(const UINT16 opcode); + void FTRV(const UINT16 opcode); + void op1111_0xf13(const UINT16 opcode); + void dbreak(const UINT16 opcode); + void op1111_0x13(UINT16 opcode); + UINT8 RB(offs_t A); + UINT16 RW(offs_t A); + UINT32 RL(offs_t A); + void sh4_change_register_bank(int to); + void sh4_swap_fp_registers(); + void sh4_swap_fp_couples(); + void sh4_syncronize_register_bank(int to); + void sh4_default_exception_priorities(); + void sh4_exception_recompute(); + void sh4_exception_request(int exception); + void sh4_exception_unrequest(int exception); + void sh4_exception_checkunrequest(int exception); + void sh4_exception(const char *message, int exception); + UINT32 compute_ticks_refresh_timer(emu_timer *timer, int hertz, int base, int divisor); + void sh4_refresh_timer_recompute(); + void increment_rtc_time(int mode); + void sh4_dmac_nmi(); + void sh4_handler_ipra_w(UINT32 data, UINT32 mem_mask); + UINT32 sh4_getsqremap(UINT32 address); + void sh4_parse_configuration(); + void sh4_timer_recompute(int which); + UINT32 sh4_handle_tcnt0_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcnt1_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcnt2_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcor0_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcor1_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcor2_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcr0_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcr1_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcr2_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tstr_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tocr_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcpr2_addr_r(UINT32 mem_mask); + void sh4_handle_tstr_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcr0_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcr1_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcr2_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcor0_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcor1_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcor2_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcnt0_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcnt1_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcnt2_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tocr_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcpr2_addr_w(UINT32 data, UINT32 mem_mask); + int sh4_dma_transfer(int channel, int timermode, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr); + int sh4_dma_transfer_device(int channel, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr); + void sh4_dmac_check(int channel); + void sh4_handle_sar0_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_sar1_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_sar2_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_sar3_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dar0_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dar1_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dar2_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dar3_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dmatcr0_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dmatcr1_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dmatcr2_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dmatcr3_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_chcr0_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_chcr1_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_chcr2_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_chcr3_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dmaor_addr_w(UINT32 data, UINT32 mem_mask); + UINT32 sh4_handle_sar0_addr_r(UINT32 mem_mask) { return m_SH4_SAR0; } + UINT32 sh4_handle_sar1_addr_r(UINT32 mem_mask) { return m_SH4_SAR1; } + UINT32 sh4_handle_sar2_addr_r(UINT32 mem_mask) { return m_SH4_SAR2; } + UINT32 sh4_handle_sar3_addr_r(UINT32 mem_mask) { return m_SH4_SAR3; } + UINT32 sh4_handle_dar0_addr_r(UINT32 mem_mask) { return m_SH4_DAR0; } + UINT32 sh4_handle_dar1_addr_r(UINT32 mem_mask) { return m_SH4_DAR1; } + UINT32 sh4_handle_dar2_addr_r(UINT32 mem_mask) { return m_SH4_DAR2; } + UINT32 sh4_handle_dar3_addr_r(UINT32 mem_mask) { return m_SH4_DAR3; } + UINT32 sh4_handle_dmatcr0_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR0; } + UINT32 sh4_handle_dmatcr1_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR1; } + UINT32 sh4_handle_dmatcr2_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR2; } + UINT32 sh4_handle_dmatcr3_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR3; } + UINT32 sh4_handle_chcr0_addr_r(UINT32 mem_mask) { return m_SH4_CHCR0; } + UINT32 sh4_handle_chcr1_addr_r(UINT32 mem_mask) { return m_SH4_CHCR1; } + UINT32 sh4_handle_chcr2_addr_r(UINT32 mem_mask) { return m_SH4_CHCR2; } + UINT32 sh4_handle_chcr3_addr_r(UINT32 mem_mask) { return m_SH4_CHCR3; } + UINT32 sh4_handle_dmaor_addr_r(UINT32 mem_mask) { return m_SH4_DMAOR; } + +}; + + +class sh3_base_device : public sh34_base_device +{ +public: + // construction/destruction + sh3_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness); + + DECLARE_WRITE32_MEMBER( sh3_internal_w ); + DECLARE_READ32_MEMBER( sh3_internal_r ); + + DECLARE_WRITE32_MEMBER( sh3_internal_high_w ); + DECLARE_READ32_MEMBER( sh3_internal_high_r ); + +protected: + virtual void device_reset(); +}; + + +class sh4_base_device : public sh34_base_device +{ +public: + // construction/destruction + sh4_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness); + + DECLARE_WRITE32_MEMBER( sh4_internal_w ); + DECLARE_READ32_MEMBER( sh4_internal_r ); + + DECLARE_READ64_MEMBER( sh4_tlb_r ); + DECLARE_WRITE64_MEMBER( sh4_tlb_w ); + +protected: + virtual void device_reset(); +}; + + +class sh3_device : public sh3_base_device +{ +public: + sh3_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + + +class sh3be_device : public sh3_base_device +{ +public: + sh3be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + +protected: + virtual void execute_run(); + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); +}; + + +class sh4_device : public sh4_base_device +{ +public: + sh4_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + + +class sh4be_device : public sh4_base_device +{ +public: + sh4be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + +protected: + virtual void execute_run(); + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); +}; + + +extern const device_type SH3LE; +extern const device_type SH3BE; +extern const device_type SH4LE; +extern const device_type SH4BE; + + +/*************************************************************************** + COMPILER-SPECIFIC OPTIONS +***************************************************************************/ + +#define SH4DRC_STRICT_VERIFY 0x0001 /* verify all instructions */ +#define SH4DRC_FLUSH_PC 0x0002 /* flush the PC value before each memory access */ +#define SH4DRC_STRICT_PCREL 0x0004 /* do actual loads on MOVLI/MOVWI instead of collapsing to immediates */ + +#define SH4DRC_COMPATIBLE_OPTIONS (SH4DRC_STRICT_VERIFY | SH4DRC_FLUSH_PC | SH4DRC_STRICT_PCREL) +#define SH4DRC_FASTEST_OPTIONS (0) + +void sh4drc_set_options(device_t *device, UINT32 options); +void sh4drc_add_pcflush(device_t *device, offs_t address); + +#endif /* __SH4_H__ */ diff --git a/src/cpu/sh4/sh4_intf.h b/src/cpu/sh4/sh4_intf.h new file mode 100644 index 000000000..013d529f3 --- /dev/null +++ b/src/cpu/sh4/sh4_intf.h @@ -0,0 +1,71 @@ +#include + +#ifndef FASTCALL + #undef __fastcall + #define __fastcall +#endif + +typedef UINT8 (__fastcall *pSh3ReadByteHandler)(UINT32 a); +typedef void (__fastcall *pSh3WriteByteHandler)(UINT32 a, UINT8 d); +typedef UINT16 (__fastcall *pSh3ReadWordHandler)(UINT32 a); +typedef void (__fastcall *pSh3WriteWordHandler)(UINT32 a, UINT16 d); +typedef UINT32 (__fastcall *pSh3ReadLongHandler)(UINT32 a); +typedef void (__fastcall *pSh3WriteLongHandler)(UINT32 a, UINT32 d); + +void __fastcall Sh3WriteByte(UINT32 a, UINT8 d); +UINT8 __fastcall Sh3ReadByte(UINT32 a); + +void Sh3Init(INT32 num, INT32 hz, char md0, char md1, char md2, char md3, char md4, char md5, char md6, char md7, char md8 ); +void Sh3Exit(); + +void sh4_set_cave_blitter_delay_func(void (*pfunc)(int)); +void sh4_set_cave_blitter_delay_timer(int cycles); +INT32 sh4_get_cpu_speed(); +void Sh3SetClockCV1k(INT32 clock); + +void Sh3SetTimerGranularity(INT32 timergransh); // speedhack + +void Sh3Open(const INT32 i); +void Sh3Close(); +INT32 Sh3GetActive(); + +void Sh3Reset(); +INT32 Sh3Run(INT32 cycles); + +void Sh3SetIRQLine(INT32 line, INT32 state); + +INT32 Sh3MapMemory(UINT8* pMemory, UINT32 nStart, UINT32 nEnd, INT32 nType); +INT32 Sh3MapHandler(uintptr_t nHandler, UINT32 nStart, UINT32 nEnd, INT32 nType); + +INT32 Sh3SetReadPortHandler(pSh3ReadLongHandler pHandler); +INT32 Sh3SetWritePortHandler(pSh3WriteLongHandler pHandler); + +INT32 Sh3SetReadByteHandler(INT32 i, pSh3ReadByteHandler pHandler); +INT32 Sh3SetWriteByteHandler(INT32 i, pSh3WriteByteHandler pHandler); +INT32 Sh3SetReadWordHandler(INT32 i, pSh3ReadWordHandler pHandler); +INT32 Sh3SetWriteWordHandler(INT32 i, pSh3WriteWordHandler pHandler); +INT32 Sh3SetReadLongHandler(INT32 i, pSh3ReadLongHandler pHandler); +INT32 Sh3SetWriteLongHandler(INT32 i, pSh3WriteLongHandler pHandler); + +UINT32 Sh3GetPC(INT32 n); +void Sh3RunEnd(); + +void Sh3BurnUntilInt(); + +INT32 Sh3TotalCycles(); +void Sh3NewFrame(); +void Sh3BurnCycles(INT32 cycles); +void Sh3Idle(INT32 cycles); +void Sh3SetEatCycles(INT32 i); + +INT32 Sh3Scan(INT32 nAction); + + +void Sh3CheatWriteByte(UINT32 a, UINT8 d); // cheat core +UINT8 Sh3CheatReadByte(UINT32 a); + +extern struct cpu_core_config Sh3Config; + +// depreciate this and use BurnTimerAttach directly! +#define BurnTimerAttachSh3(clock) \ + BurnTimerAttach(&Sh3Config, clock) diff --git a/src/cpu/sh4/sh4comn.h b/src/cpu/sh4/sh4comn.h new file mode 100644 index 000000000..9d981849b --- /dev/null +++ b/src/cpu/sh4/sh4comn.h @@ -0,0 +1,172 @@ +/***************************************************************************** + * + * sh4comn.h + * + * SH-4 non-specific components + * + *****************************************************************************/ + +#pragma once + +#ifndef __SH4COMN_H__ +#define __SH4COMN_H__ + +//#define USE_SH4DRC + +/* speed up delay loops, bail out of tight loops */ +#define BUSY_LOOP_HACKS 1 + +#define VERBOSE 0 + +#ifdef USE_SH4DRC +#include "cpu/drcfe.h" +#include "cpu/drcuml.h" +#include "cpu/drcumlsh.h" + +class sh4_frontend; +#endif + +#define CPU_TYPE_SH3 (2) +#define CPU_TYPE_SH4 (3) + +#define LOG(x) do { if (VERBOSE) logerror x; } while (0) + +#define EXPPRI(pl,po,p,n) (((4-(pl)) << 24) | ((15-(po)) << 16) | ((p) << 8) | (255-(n))) +#define NMIPRI() EXPPRI(3,0,16,SH4_INTC_NMI) +#define INTPRI(p,n) EXPPRI(4,2,p,n) + +#define FP_RS(r) m_fr[(r)] // binary representation of single precision floating point register r +#define FP_RFS(r) *( (float *)(m_fr+(r)) ) // single precision floating point register r +#define FP_RFD(r) *( (double *)(m_fr+(r)) ) // double precision floating point register r +#define FP_XS(r) m_xf[(r)] // binary representation of extended single precision floating point register r +#define FP_XFS(r) *( (float *)(m_xf+(r)) ) // single precision extended floating point register r +#define FP_XFD(r) *( (double *)(m_xf+(r)) ) // double precision extended floating point register r +#ifdef LSB_FIRST +#define FP_RS2(r) m_fr[(r) ^ m_fpu_pr] +#define FP_RFS2(r) *( (float *)(m_fr+((r) ^ m_fpu_pr)) ) +#define FP_XS2(r) m_xf[(r) ^ m_fpu_pr] +#define FP_XFS2(r) *( (float *)(m_xf+((r) ^ m_fpu_pr)) ) +#endif + + +#ifdef USE_SH4DRC +struct sh4_state +{ + int icount; + + int pcfsel; // last pcflush entry set + int maxpcfsel; // highest valid pcflush entry + UINT32 pcflushes[16]; // pcflush entries + + drc_cache * cache; /* pointer to the DRC code cache */ + drcuml_state * drcuml; /* DRC UML generator state */ + sh4_frontend * drcfe; /* pointer to the DRC front-end class */ + UINT32 drcoptions; /* configurable DRC options */ + + /* internal stuff */ + UINT8 cache_dirty; /* true if we need to flush the cache */ + + /* parameters for subroutines */ + UINT64 numcycles; /* return value from gettotalcycles */ + UINT32 arg0; /* print_debug argument 1 */ + UINT32 arg1; /* print_debug argument 2 */ + UINT32 irq; /* irq we're taking */ + + /* register mappings */ + uml::parameter regmap[16]; /* parameter to register mappings for all 16 integer registers */ + + uml::code_handle * entry; /* entry point */ + uml::code_handle * read8; /* read byte */ + uml::code_handle * write8; /* write byte */ + uml::code_handle * read16; /* read half */ + uml::code_handle * write16; /* write half */ + uml::code_handle * read32; /* read word */ + uml::code_handle * write32; /* write word */ + + uml::code_handle * interrupt; /* interrupt */ + uml::code_handle * nocode; /* nocode */ + uml::code_handle * out_of_cycles; /* out of cycles exception handler */ + + UINT32 prefadr; + UINT32 target; +}; +#endif + +#ifdef USE_SH4DRC +class sh4_frontend : public drc_frontend +{ +public: + sh4_frontend(sh4_state &state, UINT32 window_start, UINT32 window_end, UINT32 max_sequence); + +protected: + virtual bool describe(opcode_desc &desc, const opcode_desc *prev); + +private: + bool describe_group_0(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode); + bool describe_group_2(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode); + bool describe_group_3(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode); + bool describe_group_4(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode); + bool describe_group_6(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode); + bool describe_group_8(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode); + bool describe_group_12(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode); + bool describe_group_15(opcode_desc &desc, const opcode_desc *prev, UINT16 opcode); + + sh4_state &m_context; +}; +#endif + + +enum +{ + ICF = 0x00800000, + OCFA = 0x00080000, + OCFB = 0x00040000, + OVF = 0x00020000 +}; + +/* Bits in SR */ +#define T 0x00000001 +#define S 0x00000002 +#define I 0x000000f0 +#define Q 0x00000100 +#define M 0x00000200 +#define FD 0x00008000 +#define BL 0x10000000 +#define sRB 0x20000000 +#define MD 0x40000000 + +/* 29 bits */ +#define AM 0x1fffffff + +#define FLAGS (MD|sRB|BL|FD|M|Q|I|S|T) + +/* Bits in FPSCR */ +#define RM 0x00000003 +#define DN 0x00040000 +#define PR 0x00080000 +#define SZ 0x00100000 +#define FR 0x00200000 + +#define Rn ((opcode>>8)&15) +#define Rm ((opcode>>4)&15) + +#define REGFLAG_R(n) (1 << (n)) +#define REGFLAG_FR(n) (1 << (n)) +#define REGFLAG_XR(n) (1 << (n)) + +/* register flags 1 */ +#define REGFLAG_PR (1 << 0) +#define REGFLAG_MACL (1 << 1) +#define REGFLAG_MACH (1 << 2) +#define REGFLAG_GBR (1 << 3) +#define REGFLAG_VBR (1 << 4) +#define REGFLAG_SR (1 << 5) +#define REGFLAG_SGR (1 << 6) +#define REGFLAG_FPUL (1 << 7) +#define REGFLAG_FPSCR (1 << 8) +#define REGFLAG_DBR (1 << 9) +#define REGFLAG_SSR (1 << 10) +#define REGFLAG_SPC (1 << 11) + + +#endif /* __SH4COMN_H__ */ diff --git a/src/cpu/sh4/sh4comn.inc b/src/cpu/sh4/sh4comn.inc new file mode 100644 index 000000000..56e670133 --- /dev/null +++ b/src/cpu/sh4/sh4comn.inc @@ -0,0 +1,1285 @@ +/***************************************************************************** + * + * sh4comn.c + * + * SH-4 non-specific components + * + *****************************************************************************/ + +/* +#include "burnint.h" +#include "debugger.h" +#include "sh4.h" +#include "sh4regs.h" +#include "sh4comn.h" +#include "sh3comn.h" +#include "sh4tmu.h" +#include "sh4dmac.h" +*/ + +static const int rtcnt_div[8] = { 0, 4, 16, 64, 256, 1024, 2048, 4096 }; +static const int daysmonth[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; + + + +static const UINT32 exception_priority_default[] = { + EXPPRI(1,1,0,0), /* Power-on Reset */ + EXPPRI(1,2,0,1), /* Manual Reset */ + EXPPRI(1,1,0,2), /* H-UDI Reset */ + EXPPRI(1,3,0,3), /* Inst TLB Multiple Hit */ + EXPPRI(1,4,0,4), /* Data TLB Multiple Hit */ + + EXPPRI(2,0,0,5), /* User break Before Instruction */ + EXPPRI(2,1,0,6), /* Inst Address Error */ + EXPPRI(2,2,0,7), /* Inst TLB Miss */ + EXPPRI(2,3,0,8), /* Inst TLB Protection Violation */ + EXPPRI(2,4,0,9), /* Illegal Instruction */ + EXPPRI(2,4,0,10), /* Slot Illegal Instruction */ + EXPPRI(2,4,0,11), /* FPU Disable */ + EXPPRI(2,4,0,12), /* Slot FPU Disable */ + EXPPRI(2,5,0,13), /* Data Address Error (Read) */ + EXPPRI(2,5,0,14), /* Data Address Error (Write) */ + EXPPRI(2,6,0,15), /* Data TBL Miss Read */ + EXPPRI(2,6,0,16), /* Data TBL Miss Write */ + EXPPRI(2,7,0,17), /* Data TBL Protection Violation Read */ + EXPPRI(2,7,0,18), /* Data TBL Protection Violation Write */ + EXPPRI(2,8,0,19), /* FPU Exception */ + EXPPRI(2,9,0,20), /* Initial Page Write exception */ + + EXPPRI(2,4,0,21), /* Unconditional TRAP */ + EXPPRI(2,10,0,22), /* User break After Instruction */ + + EXPPRI(3,0,16,SH4_INTC_NMI) /* NMI */ + /* This is copied to a table, and the IRQ priorities filled in later */ +}; + +static const int exception_codes[] = + +{ 0x000, /* Power-on Reset */ + 0x020, /* Manual Reset */ + 0x000, /* H-UDI Reset */ + 0x140, /* Inst TLB Multiple Hit */ + 0x140, /* Data TLB Multiple Hit */ + + 0x1E0, /* User break Before Instruction */ + 0x0E0, /* Inst Address Error */ + 0x040, /* Inst TLB Miss */ + 0x0A0, /* Inst TLB Protection Violation */ + 0x180, /* Illegal Instruction */ + 0x1A0, /* Slot Illegal Instruction */ + 0x800, /* FPU Disable */ + 0x820, /* Slot FPU Disable */ + 0x0E0, /* Data Address Error (Read) */ + 0x100, /* Data Address Error (Write) */ + 0x040, /* Data TBL Miss Read */ + 0x060, /* Data TBL Miss Write */ + 0x0A0, /* Data TBL Protection Violation Read */ + 0x0C0, /* Data TBL Protection Violation Write */ + 0x120, /* FPU Exception */ + 0x080, /* Initial Page Write exception */ + + 0x160, /* Unconditional TRAP */ + 0x1E0, /* User break After Instruction */ + + 0x1C0, /* NMI */ /* SH4_INTC_NMI=23 represents this location in this list.. */ + + 0x200, /* EX Irq 0 */ + 0x220, /* 1 */ + 0x240, /* 2 */ + 0x260, /* 3 */ + 0x280, /* 4 */ + 0x2A0, /* 5 */ + 0x2C0, /* 6 */ + 0x2E0, /* 7 */ + 0x300, /* 8 */ + 0x320, /* 9 */ + 0x340, /* A */ + 0x360, /* B */ + 0x380, /* C */ + 0x3A0, /* D */ + 0x3C0, /* E */ + + 0x240, /* SH4_INTC_IRL0 */ + 0x2A0, /* SH4_INTC_IRL1 */ + 0x300, /* SH4_INTC_IRL2 */ + 0x360, /* SH4_INTC_IRL3 */ + + 0x600, /* HUDI */ + 0x620, /* SH4_INTC_GPOI */ + 0x640, /* SH4_INTC_DMTE0 */ + 0x660, /* SH4_INTC_DMTE1 */ + 0x680, /* SH4_INTC_DMTE2 */ + 0x6A0, /* SH4_INTC_DMTE3 */ + + 0x780, /* SH4_INTC_DMTE4 */ + 0x7A0, /* SH4_INTC_DMTE5 */ + 0x7C0, /* SH4_INTC_DMTE6 */ + 0x7E0, /* SH4_INTC_DMTE7 */ + + 0x6C0, /* SH4_INTC_DMAE */ + + 0xB00, /* SH4_INTC_TUNI3 */ + 0xB80, /* SH4_INTC_TUNI4 */ + 0x400, /* SH4_INTC_TUNI0 */ + 0x420, /* SH4_INTC_TUNI1 */ + 0x440, /* SH4_INTC_TUNI2 */ + 0x460, /* SH4_INTC_TICPI2 */ + 0x480, /* SH4_INTC_ATI */ + 0x4A0, /* SH4_INTC_PRI */ + 0x4C0, /* SH4_INTC_CUI */ + 0x4E0, /* SH4_INTC_SCI1ERI */ + 0x500, /* SH4_INTC_SCI1RXI */ + 0x520, /* SH4_INTC_SCI1TXI */ + 0x540, /* SH4_INTC_SCI1TEI */ + + 0x700, /* SH4_INTC_SCIFERI */ + 0x720, /* SH4_INTC_SCIFRXI */ + 0x740, /* SH4_INTC_SCIFBRI */ + 0x760, /* SH4_INTC_SCIFTXI */ + 0x560, /* SH4_INTC_ITI */ + 0x580, /* SH4_INTC_RCMI */ + 0x5A0 /* SH4_INTC_ROVI */ +}; + +/* SH3 INTEVT2 uses a different table - values of -1 aren't filled in yet, some may not exist on the sh3. */ +/* The above table should differ too, some things depend on the interrupt level rather than beign fixed values */ + +static const int sh3_intevt2_exception_codes[] = + +{ 0x000, /* Power-on Reset */ + -1, /* Manual Reset */ + -1, /* H-UDI Reset */ + -1, /* Inst TLB Multiple Hit */ + -1, /* Data TLB Multiple Hit */ + + -1, /* User break Before Instruction */ + -1, /* Inst Address Error */ + -1, /* Inst TLB Miss */ + -1, /* Inst TLB Protection Violation */ + -1, /* Illegal Instruction */ + -1, /* Slot Illegal Instruction */ + -1, /* FPU Disable */ + -1, /* Slot FPU Disable */ + -1, /* Data Address Error (Read) */ + -1, /* Data Address Error (Write) */ + -1, /* Data TBL Miss Read */ + -1, /* Data TBL Miss Write */ + -1, /* Data TBL Protection Violation Read */ + -1, /* Data TBL Protection Violation Write */ + -1, /* FPU Exception */ + -1, /* Initial Page Write exception */ + + -1, /* Unconditional TRAP */ + -1, /* User break After Instruction */ + + -1, /* NMI */ /* SH4_INTC_NMI=23 represents this location in this list.. */ + + -1, /* EX Irq 0 */ + -1, /* 1 */ + -1, /* 2 */ + -1, /* 3 */ + -1, /* 4 */ + -1, /* 5 */ + -1, /* 6 */ + -1, /* 7 */ + -1, /* 8 */ + -1, /* 9 */ + -1, /* A */ + -1, /* B */ + -1, /* C */ + -1, /* D */ + -1, /* E */ + + 0x600, /* SH4_INTC_IRL0 */ + 0x620, /* SH4_INTC_IRL1 */ + 0x640, /* SH4_INTC_IRL2 */ + 0x660, /* SH4_INTC_IRL3 */ + /* todo: SH3 should have lines 4+5 too? */ + + -1, /* HUDI */ + -1, /* SH4_INTC_GPOI */ + -1, /* SH4_INTC_DMTE0 */ + -1, /* SH4_INTC_DMTE1 */ + -1, /* SH4_INTC_DMTE2 */ + -1, /* SH4_INTC_DMTE3 */ + + -1, /* SH4_INTC_DMTE4 */ + -1, /* SH4_INTC_DMTE5 */ + -1, /* SH4_INTC_DMTE6 */ + -1, /* SH4_INTC_DMTE7 */ + + -1, /* SH4_INTC_DMAE */ + + -1, /* SH4_INTC_TUNI3 */ + -1, /* SH4_INTC_TUNI4 */ + 0x400, /* SH4_INTC_TUNI0 */ + 0x420, /* SH4_INTC_TUNI1 */ + 0x440, /* SH4_INTC_TUNI2 */ + 0x460, /* SH4_INTC_TICPI2 */ + -1, /* SH4_INTC_ATI */ + -1, /* SH4_INTC_PRI */ + -1, /* SH4_INTC_CUI */ + -1, /* SH4_INTC_SCI1ERI */ + -1, /* SH4_INTC_SCI1RXI */ + -1, /* SH4_INTC_SCI1TXI */ + -1, /* SH4_INTC_SCI1TEI */ + + -1, /* SH4_INTC_SCIFERI */ + -1, /* SH4_INTC_SCIFRXI */ + -1, /* SH4_INTC_SCIFBRI */ + -1, /* SH4_INTC_SCIFTXI */ + -1, /* SH4_INTC_ITI */ + -1, /* SH4_INTC_RCMI */ + -1 /* SH4_INTC_ROVI */ +}; + + + +static void sh4_change_register_bank(int to) +{ + int s; + + if (to) // 0 -> 1 + { + for (s = 0;s < 8;s++) + { + m_rbnk[0][s] = m_r[s]; + m_r[s] = m_rbnk[1][s]; + } + } + else // 1 -> 0 + { + for (s = 0;s < 8;s++) + { + m_rbnk[1][s] = m_r[s]; + m_r[s] = m_rbnk[0][s]; + } + } +} + +static void sh4_swap_fp_registers() +{ + int s; + UINT32 z; + + for (s = 0;s <= 15;s++) + { + z = m_fr[s]; + m_fr[s] = m_xf[s]; + m_xf[s] = z; + } +} + +static void sh4_swap_fp_couples() +{ + int s; + UINT32 z; + + for (s = 0;s <= 15;s = s+2) + { + z = m_fr[s]; + m_fr[s] = m_fr[s + 1]; + m_fr[s + 1] = z; + z = m_xf[s]; + m_xf[s] = m_xf[s + 1]; + m_xf[s + 1] = z; + } +} + +#if 0 +static void sh4_syncronize_register_bank(int to) // for debugger +{ + int s; + + for (s = 0;s < 8;s++) + { + m_rbnk[to][s] = m_r[s]; + } +} +#endif + +static void sh4_default_exception_priorities() // setup default priorities for exceptions +{ + int a; + + for (a=0;a <= SH4_INTC_NMI;a++) + m_exception_priority[a] = exception_priority_default[a]; + for (a=SH4_INTC_IRLn0;a <= SH4_INTC_IRLnE;a++) + m_exception_priority[a] = INTPRI(15-(a-SH4_INTC_IRLn0), a); + m_exception_priority[SH4_INTC_IRL0] = INTPRI(13, SH4_INTC_IRL0); + m_exception_priority[SH4_INTC_IRL1] = INTPRI(10, SH4_INTC_IRL1); + m_exception_priority[SH4_INTC_IRL2] = INTPRI(7, SH4_INTC_IRL2); + m_exception_priority[SH4_INTC_IRL3] = INTPRI(4, SH4_INTC_IRL3); + for (a=SH4_INTC_HUDI;a <= SH4_INTC_ROVI;a++) + m_exception_priority[a] = INTPRI(0, a); +} + +static void sh4_exception_recompute() // checks if there is any interrupt with high enough priority +{ + int a,z; + + m_test_irq = 0; + if ((!m_pending_irq) || ((m_sr & BL) && (m_exception_requesting[SH4_INTC_NMI] == 0))) + return; + z = (m_sr >> 4) & 15; + for (a=0;a <= SH4_INTC_ROVI;a++) + { + if (m_exception_requesting[a]) + { + int pri = (((int)m_exception_priority[a] >> 8) & 255); + //logerror("pri is %02x z is %02x\n",pri,z); + if (pri > z) + { + //logerror("will test\n"); + m_test_irq = 1; // will check for exception at end of instructions + break; + } + } + } +} + +static void sh4_exception_request(int exception) // start requesting an exception +{ + m_cpu_off = 0; //dink + //logerror("sh4_exception_request a\n"); + if (!m_exception_requesting[exception]) + { + //logerror("sh4_exception_request b\n"); + m_exception_requesting[exception] = 1; + m_pending_irq++; + sh4_exception_recompute(); + } +} + +static void sh4_exception_unrequest(int exception) // stop requesting an exception +{ + if (m_exception_requesting[exception]) + { + m_exception_requesting[exception] = 0; + m_pending_irq--; + sh4_exception_recompute(); + } +} + +static void sh4_exception_checkunrequest(int exception) +{ + if (exception == SH4_INTC_NMI) + sh4_exception_unrequest(exception); + if ((exception == SH4_INTC_DMTE0) || (exception == SH4_INTC_DMTE1) || + (exception == SH4_INTC_DMTE2) || (exception == SH4_INTC_DMTE3)) + sh4_exception_unrequest(exception); +} + +static void sh4_exception(/*const char *message,*/ int exception) // handle exception +{ + UINT32 vector; + + + if (m_cpu_type == CPU_TYPE_SH4) + { + if (exception < SH4_INTC_NMI) + return; // Not yet supported + if (exception == SH4_INTC_NMI) { + if ((m_sr & BL) && (!(m_m[ICR] & 0x200))) + return; + + m_m[ICR] &= ~0x200; + m_m[INTEVT] = 0x1c0; + + + vector = 0x600; + //standard_irq_callback(INPUT_LINE_NMI); + //LOG(("SH-4 '%s' nmi exception after [%s]\n", tag(), message)); + } else { + // if ((m_m[ICR] & 0x4000) && (m_nmi_line_state == ASSERT_LINE)) + // return; + if (m_sr & BL) + return; + if (((m_exception_priority[exception] >> 8) & 255) <= ((m_sr >> 4) & 15)) + return; + m_m[INTEVT] = exception_codes[exception]; + vector = 0x600; + if ((exception >= SH4_INTC_IRL0) && (exception <= SH4_INTC_IRL3)) + { + //standard_irq_callback((exception-SH4_INTC_IRL0)+SH4_IRL0); + } + else + { + //standard_irq_callback(SH4_IRL3+1); + } + //LOG(("SH-4 '%s' interrupt exception #%d after [%s]\n", tag(), exception, message)); + } + } + else /* SH3 exceptions */ + { + /***** ASSUME THIS TO BE WRONG FOR NOW *****/ + + if (exception < SH4_INTC_NMI) + return; // Not yet supported + if (exception == SH4_INTC_NMI) + { + return; + } + else + { + if (m_sr & BL) + return; + if (((m_exception_priority[exception] >> 8) & 255) <= ((m_sr >> 4) & 15)) + return; + + + vector = 0x600; + + if ((exception >= SH4_INTC_IRL0) && (exception <= SH4_INTC_IRL3)) + { + int irq = (exception-SH4_INTC_IRL0)+SH4_IRL0; + if (m_irq_line_state[irq] == CPU_IRQSTATUS_HOLD) { + Sh3SetIRQLine(irq, 0); + } + //standard_irq_callback((exception-SH4_INTC_IRL0)+SH4_IRL0); + } + else + { + //standard_irq_callback(SH4_IRL3+1); + } + + if (sh3_intevt2_exception_codes[exception]==-1) + fatalerror("sh3_intevt2_exception_codes unpopulated for exception %02x\n", exception); + + m_sh3internal_lower[INTEVT2] = sh3_intevt2_exception_codes[exception]; + m_sh3internal_upper[SH3_EXPEVT_ADDR] = exception_codes[exception]; + + + //LOG(("SH-3 '%s' interrupt exception #%d after [%s]\n", tag(), exception, message)); + } + + /***** END ASSUME THIS TO BE WRONG FOR NOW *****/ + } + sh4_exception_checkunrequest(exception); + + m_spc = m_pc; + m_ssr = m_sr; + m_sgr = m_r[15]; + + m_sr |= MD; +// if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) +// sh4_syncronize_register_bank((m_sr & sRB) >> 29); + if (!(m_sr & sRB)) + sh4_change_register_bank(1); + m_sr |= sRB; + m_sr |= BL; + sh4_exception_recompute(); + + /* fetch PC */ + m_pc = m_vbr + vector; + //bprintf(0, _T("irq exception: %x vector: %x\n"), exception, m_pc); + /* wake up if a sleep opcode is triggered */ + if(m_sleep_mode == 1) { m_sleep_mode = 2; } +} + +#if 0 +// no sh4 -dink +static UINT32 compute_ticks_refresh_timer(emu_timer *timer, int hertz, int base, int divisor) +{ + // elapsed:total = x : ticks + // x=elapsed*tics/total -> x=elapsed*(double)100000000/rtcnt_div[(m_m[RTCSR] >> 3) & 7] + // ticks/total=ticks / ((rtcnt_div[(m_m[RTCSR] >> 3) & 7] * ticks) / 100000000)=1/((rtcnt_div[(m_m[RTCSR] >> 3) & 7] / 100000000)=100000000/rtcnt_div[(m_m[RTCSR] >> 3) & 7] + return base + (UINT32)((timer->elapsed().as_double() * (double)hertz) / (double)divisor); +} + +static void sh4_refresh_timer_recompute() +{ + UINT32 ticks; + + if (m_cpu_type != CPU_TYPE_SH4) + fatalerror("sh4_refresh_timer_recompute uses m_m[] with SH3\n", 0); + + + //if rtcnt < rtcor then rtcor-rtcnt + //if rtcnt >= rtcor then 256-rtcnt+rtcor=256+rtcor-rtcnt + ticks = m_m[RTCOR]-m_m[RTCNT]; + if (ticks <= 0) + ticks = 256 + ticks; + m_refresh_timer->adjust(attotime::from_hz(m_bus_clock) * rtcnt_div[(m_m[RTCSR] >> 3) & 7] * ticks); + m_refresh_timer_base = m_m[RTCNT]; +} + + +TIMER_CALLBACK_MEMBER( sh4_refresh_timer_callback ) +{ + if (m_cpu_type != CPU_TYPE_SH4) + fatalerror("sh4_refresh_timer_callback uses m_m[] with SH3\n", 0); + + m_m[RTCNT] = 0; + sh4_refresh_timer_recompute(); + m_m[RTCSR] |= 128; + if ((m_m[MCR] & 4) && !(m_m[MCR] & 2)) + { + m_m[RFCR] = (m_m[RFCR] + 1) & 1023; + if (((m_m[RTCSR] & 1) && (m_m[RFCR] == 512)) || (m_m[RFCR] == 0)) + { + m_m[RFCR] = 0; + m_m[RTCSR] |= 4; + } + } +} + +static void increment_rtc_time(int mode) +{ + int carry, year, leap, days; + + if (m_cpu_type != CPU_TYPE_SH4) + fatalerror("increment_rtc_time uses m_m[] with SH3\n", 0); + + if (mode == 0) + { + carry = 0; + m_m[RSECCNT] = m_m[RSECCNT] + 1; + if ((m_m[RSECCNT] & 0xf) == 0xa) + m_m[RSECCNT] = m_m[RSECCNT] + 6; + if (m_m[RSECCNT] == 0x60) + { + m_m[RSECCNT] = 0; + carry=1; + } + else + return; + } + else + carry = 1; + + m_m[RMINCNT] = m_m[RMINCNT] + carry; + if ((m_m[RMINCNT] & 0xf) == 0xa) + m_m[RMINCNT] = m_m[RMINCNT] + 6; + carry=0; + if (m_m[RMINCNT] == 0x60) + { + m_m[RMINCNT] = 0; + carry = 1; + } + + m_m[RHRCNT] = m_m[RHRCNT] + carry; + if ((m_m[RHRCNT] & 0xf) == 0xa) + m_m[RHRCNT] = m_m[RHRCNT] + 6; + carry = 0; + if (m_m[RHRCNT] == 0x24) + { + m_m[RHRCNT] = 0; + carry = 1; + } + + m_m[RWKCNT] = m_m[RWKCNT] + carry; + if (m_m[RWKCNT] == 0x7) + { + m_m[RWKCNT] = 0; + } + + days = 0; + year = (m_m[RYRCNT] & 0xf) + ((m_m[RYRCNT] & 0xf0) >> 4)*10 + ((m_m[RYRCNT] & 0xf00) >> 8)*100 + ((m_m[RYRCNT] & 0xf000) >> 12)*1000; + leap = 0; + if (!(year%100)) + { + if (!(year%400)) + leap = 1; + } + else if (!(year%4)) + leap = 1; + if (m_m[RMONCNT] != 2) + leap = 0; + if (m_m[RMONCNT]) + days = daysmonth[(m_m[RMONCNT] & 0xf) + ((m_m[RMONCNT] & 0xf0) >> 4)*10 - 1]; + + m_m[RDAYCNT] = m_m[RDAYCNT] + carry; + if ((m_m[RDAYCNT] & 0xf) == 0xa) + m_m[RDAYCNT] = m_m[RDAYCNT] + 6; + carry = 0; + if (m_m[RDAYCNT] > (days+leap)) + { + m_m[RDAYCNT] = 1; + carry = 1; + } + + m_m[RMONCNT] = m_m[RMONCNT] + carry; + if ((m_m[RMONCNT] & 0xf) == 0xa) + m_m[RMONCNT] = m_m[RMONCNT] + 6; + carry=0; + if (m_m[RMONCNT] == 0x13) + { + m_m[RMONCNT] = 1; + carry = 1; + } + + m_m[RYRCNT] = m_m[RYRCNT] + carry; + if ((m_m[RYRCNT] & 0xf) >= 0xa) + m_m[RYRCNT] = m_m[RYRCNT] + 6; + if ((m_m[RYRCNT] & 0xf0) >= 0xa0) + m_m[RYRCNT] = m_m[RYRCNT] + 0x60; + if ((m_m[RYRCNT] & 0xf00) >= 0xa00) + m_m[RYRCNT] = m_m[RYRCNT] + 0x600; + if ((m_m[RYRCNT] & 0xf000) >= 0xa000) + m_m[RYRCNT] = 0; +} + +TIMER_CALLBACK_MEMBER( sh4_rtc_timer_callback ) +{ + if (m_cpu_type != CPU_TYPE_SH4) + { + logerror("sh4_rtc_timer_callback uses m_m[] with SH3\n"); + return; + } + + m_rtc_timer->adjust(attotime::from_hz(128)); + m_m[R64CNT] = (m_m[R64CNT]+1) & 0x7f; + if (m_m[R64CNT] == 64) + { + m_m[RCR1] |= 0x80; + increment_rtc_time(0); + //sh4_exception_request(SH4_INTC_NMI); // TEST + } +} + + +void sh4_dmac_nmi() // manage dma when nmi gets asserted +{ + int s; + + m_SH4_DMAOR |= DMAOR_NMIF; + for (s = 0;s < 4;s++) + { + if (m_dma_timer_active[s]) + { + logerror("SH4: DMA %d cancelled due to NMI but all data transferred", s); + m_dma_timer[s]->adjust(attotime::never, s); + m_dma_timer_active[s] = 0; + } + } +} +// end sh4 stuff -dink +#endif + +static void sh4_handler_ipra_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_IPRA); + /* 15 - 12 TMU0 */ + /* 11 - 8 TMU1 */ + /* 7 - 4 TMU2 */ + /* 3 - 0 RTC */ + m_exception_priority[SH4_INTC_ATI] = INTPRI(m_SH4_IPRA & 0x000f, SH4_INTC_ATI); + m_exception_priority[SH4_INTC_PRI] = INTPRI(m_SH4_IPRA & 0x000f, SH4_INTC_PRI); + m_exception_priority[SH4_INTC_CUI] = INTPRI(m_SH4_IPRA & 0x000f, SH4_INTC_CUI); + + m_exception_priority[SH4_INTC_TUNI2] = INTPRI((m_SH4_IPRA & 0x00f0) >> 4, SH4_INTC_TUNI2); + m_exception_priority[SH4_INTC_TICPI2] = INTPRI((m_SH4_IPRA & 0x00f0) >> 4, SH4_INTC_TICPI2); + + m_exception_priority[SH4_INTC_TUNI1] = INTPRI((m_SH4_IPRA & 0x0f00) >> 8, SH4_INTC_TUNI1); + + m_exception_priority[SH4_INTC_TUNI0] = INTPRI((m_SH4_IPRA & 0xf000) >> 12, SH4_INTC_TUNI0); + + logerror("setting priorities TMU0 %01x TMU1 %01x TMU2 %01x RTC %01x\n", (m_SH4_IPRA & 0xf000)>>12, (m_SH4_IPRA & 0x0f00)>>8, (m_SH4_IPRA & 0x00f0)>>4, (m_SH4_IPRA & 0x000f)>>0); + + sh4_exception_recompute(); +} + +#if 0 +// no sh4 -dink +WRITE32_MEMBER( sh4_base_device::sh4_internal_w ) +{ + int a; + UINT32 addr = (offset << 2) + 0xfe000000; + offset = ((addr & 0xfc) >> 2) | ((addr & 0x1fe0000) >> 11); + + if (m_cpu_type != CPU_TYPE_SH4) + fatalerror("sh4_internal_w uses m_m[] with SH3\n", 0); + + UINT32 old = m_m[offset]; + COMBINE_DATA(m_m+offset); + +// printf("sh4_internal_w: Write %08x (%x), %08x @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), offset, data, mem_mask); + + switch( offset ) + { + case MMUCR: // MMU Control + if (data & MMUCR_AT) + { + printf("SH4 MMU Enabled\n"); + printf("If you're seeing this, but running something other than a Naomi GD-ROM game then chances are it won't work\n"); + printf("The MMU emulation is a hack specific to that system\n"); + m_sh4_mmu_enabled = 1; + + // should be a different bit! + { + int i; + for (i=0;i<64;i++) + { + m_sh4_tlb_address[i] = 0; + m_sh4_tlb_data[i] = 0; + } + + } + } + else + { + m_sh4_mmu_enabled = 0; + } + + break; + + // Memory refresh + case RTCSR: + m_m[RTCSR] &= 255; + if ((old >> 3) & 7) + m_m[RTCNT] = compute_ticks_refresh_timer(m_refresh_timer, m_bus_clock, m_refresh_timer_base, rtcnt_div[(old >> 3) & 7]) & 0xff; + if ((m_m[RTCSR] >> 3) & 7) + { // activated + sh4_refresh_timer_recompute(); + } + else + { + m_refresh_timer->adjust(attotime::never); + } + break; + + case RTCNT: + m_m[RTCNT] &= 255; + if ((m_m[RTCSR] >> 3) & 7) + { // active + sh4_refresh_timer_recompute(); + } + break; + + case RTCOR: + m_m[RTCOR] &= 255; + if ((m_m[RTCSR] >> 3) & 7) + { // active + m_m[RTCNT] = compute_ticks_refresh_timer(m_refresh_timer, m_bus_clock, m_refresh_timer_base, rtcnt_div[(m_m[RTCSR] >> 3) & 7]) & 0xff; + sh4_refresh_timer_recompute(); + } + break; + + case RFCR: + m_m[RFCR] &= 1023; + break; + + // RTC + case RCR1: + if ((m_m[RCR1] & 8) && (~old & 8)) // 0 -> 1 + m_m[RCR1] ^= 1; + break; + + case RCR2: + if (m_m[RCR2] & 2) + { + m_m[R64CNT] = 0; + m_m[RCR2] ^= 2; + } + if (m_m[RCR2] & 4) + { + m_m[R64CNT] = 0; + if (m_m[RSECCNT] >= 30) + increment_rtc_time(1); + m_m[RSECCNT] = 0; + } + if ((m_m[RCR2] & 8) && (~old & 8)) + { // 0 -> 1 + m_rtc_timer->adjust(attotime::from_hz(128)); + } + else if (~(m_m[RCR2]) & 8) + { // 0 + m_rtc_timer->adjust(attotime::never); + } + break; + +/********************************************************************************************************************* + TMU (Timer Unit) +*********************************************************************************************************************/ + case SH4_TSTR_ADDR: sh4_handle_tstr_addr_w(data,mem_mask); break; + case SH4_TCR0_ADDR: sh4_handle_tcr0_addr_w(data,mem_mask); break; + case SH4_TCR1_ADDR: sh4_handle_tcr1_addr_w(data,mem_mask); break; + case SH4_TCR2_ADDR: sh4_handle_tcr2_addr_w(data,mem_mask); break; + case SH4_TCOR0_ADDR: sh4_handle_tcor0_addr_w(data,mem_mask); break; + case SH4_TCNT0_ADDR: sh4_handle_tcnt0_addr_w(data,mem_mask); break; + case SH4_TCOR1_ADDR: sh4_handle_tcor1_addr_w(data,mem_mask); break; + case SH4_TCNT1_ADDR: sh4_handle_tcnt1_addr_w(data,mem_mask); break; + case SH4_TCOR2_ADDR: sh4_handle_tcor2_addr_w(data,mem_mask); break; + case SH4_TCNT2_ADDR: sh4_handle_tcnt2_addr_w(data,mem_mask); break; + case SH4_TOCR_ADDR: sh4_handle_tocr_addr_w(data,mem_mask); break; // not supported + case SH4_TCPR2_ADDR: sh4_handle_tcpr2_addr_w(data,mem_mask); break; // not supported +/********************************************************************************************************************* + INTC (Interrupt Controller) +*********************************************************************************************************************/ + case ICR: + m_m[ICR] = (m_m[ICR] & 0x7fff) | (old & 0x8000); + break; + case IPRA: sh4_handler_ipra_w(data, mem_mask); break; + case IPRB: + m_exception_priority[SH4_INTC_SCI1ERI] = INTPRI((m_m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1ERI); + m_exception_priority[SH4_INTC_SCI1RXI] = INTPRI((m_m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1RXI); + m_exception_priority[SH4_INTC_SCI1TXI] = INTPRI((m_m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1TXI); + m_exception_priority[SH4_INTC_SCI1TEI] = INTPRI((m_m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1TEI); + m_exception_priority[SH4_INTC_RCMI] = INTPRI((m_m[IPRB] & 0x0f00) >> 8, SH4_INTC_RCMI); + m_exception_priority[SH4_INTC_ROVI] = INTPRI((m_m[IPRB] & 0x0f00) >> 8, SH4_INTC_ROVI); + m_exception_priority[SH4_INTC_ITI] = INTPRI((m_m[IPRB] & 0xf000) >> 12, SH4_INTC_ITI); + sh4_exception_recompute(); + break; + case IPRC: + m_exception_priority[SH4_INTC_HUDI] = INTPRI(m_m[IPRC] & 0x000f, SH4_INTC_HUDI); + m_exception_priority[SH4_INTC_SCIFERI] = INTPRI((m_m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFERI); + m_exception_priority[SH4_INTC_SCIFRXI] = INTPRI((m_m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFRXI); + m_exception_priority[SH4_INTC_SCIFBRI] = INTPRI((m_m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFBRI); + m_exception_priority[SH4_INTC_SCIFTXI] = INTPRI((m_m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFTXI); + m_exception_priority[SH4_INTC_DMTE0] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE0); + m_exception_priority[SH4_INTC_DMTE1] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE1); + m_exception_priority[SH4_INTC_DMTE2] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE2); + m_exception_priority[SH4_INTC_DMTE3] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE3); + m_exception_priority[SH4_INTC_DMAE] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMAE); + m_exception_priority[SH4_INTC_GPOI] = INTPRI((m_m[IPRC] & 0xf000) >> 12, SH4_INTC_GPOI); + sh4_exception_recompute(); + break; +/********************************************************************************************************************* + DMAC (DMA Controller) +*********************************************************************************************************************/ + case SH4_SAR0_ADDR: sh4_handle_sar0_addr_w(data,mem_mask); break; + case SH4_SAR1_ADDR: sh4_handle_sar1_addr_w(data,mem_mask); break; + case SH4_SAR2_ADDR: sh4_handle_sar2_addr_w(data,mem_mask); break; + case SH4_SAR3_ADDR: sh4_handle_sar3_addr_w(data,mem_mask); break; + case SH4_DAR0_ADDR: sh4_handle_dar0_addr_w(data,mem_mask); break; + case SH4_DAR1_ADDR: sh4_handle_dar1_addr_w(data,mem_mask); break; + case SH4_DAR2_ADDR: sh4_handle_dar2_addr_w(data,mem_mask); break; + case SH4_DAR3_ADDR: sh4_handle_dar3_addr_w(data,mem_mask); break; + case SH4_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(data,mem_mask); break; + case SH4_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(data,mem_mask); break; + case SH4_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(data,mem_mask); break; + case SH4_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(data,mem_mask); break; + case SH4_CHCR0_ADDR: sh4_handle_chcr0_addr_w(data,mem_mask); break; + case SH4_CHCR1_ADDR: sh4_handle_chcr1_addr_w(data,mem_mask); break; + case SH4_CHCR2_ADDR: sh4_handle_chcr2_addr_w(data,mem_mask); break; + case SH4_CHCR3_ADDR: sh4_handle_chcr3_addr_w(data,mem_mask); break; + case SH4_DMAOR_ADDR: sh4_handle_dmaor_addr_w(data,mem_mask); break; +/********************************************************************************************************************* + Store Queues +*********************************************************************************************************************/ + case QACR0: + case QACR1: + break; +/********************************************************************************************************************* + I/O +*********************************************************************************************************************/ + case PCTRA: + m_ioport16_pullup = 0; + m_ioport16_direction = 0; + for (a=0;a < 16;a++) { + m_ioport16_direction |= (m_m[PCTRA] & (1 << (a*2))) >> a; + m_ioport16_pullup |= (m_m[PCTRA] & (1 << (a*2+1))) >> (a+1); + } + m_ioport16_direction &= 0xffff; + m_ioport16_pullup = (m_ioport16_pullup | m_ioport16_direction) ^ 0xffff; + if (m_m[BCR2] & 1) + m_io->write_dword(SH4_IOPORT_16, (UINT64)(m_m[PDTRA] & m_ioport16_direction) | ((UINT64)m_m[PCTRA] << 16)); + break; + case PDTRA: + if (m_m[BCR2] & 1) + m_io->write_dword(SH4_IOPORT_16, (UINT64)(m_m[PDTRA] & m_ioport16_direction) | ((UINT64)m_m[PCTRA] << 16)); + break; + case PCTRB: + m_ioport4_pullup = 0; + m_ioport4_direction = 0; + for (a=0;a < 4;a++) { + m_ioport4_direction |= (m_m[PCTRB] & (1 << (a*2))) >> a; + m_ioport4_pullup |= (m_m[PCTRB] & (1 << (a*2+1))) >> (a+1); + } + m_ioport4_direction &= 0xf; + m_ioport4_pullup = (m_ioport4_pullup | m_ioport4_direction) ^ 0xf; + if (m_m[BCR2] & 1) + m_io->write_dword(SH4_IOPORT_4, (m_m[PDTRB] & m_ioport4_direction) | (m_m[PCTRB] << 16)); + break; + case PDTRB: + if (m_m[BCR2] & 1) + m_io->write_dword(SH4_IOPORT_4, (m_m[PDTRB] & m_ioport4_direction) | (m_m[PCTRB] << 16)); + break; + + case SCBRR2: + break; + + case SCSPTR2: //trips often in aristocrat mk-6 + break; + + default: + logerror("sh4_internal_w: Unmapped write %08x, %08x @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), data, mem_mask); + break; + } +} + +READ32_MEMBER( sh4_base_device::sh4_internal_r ) +{ + if (m_cpu_type != CPU_TYPE_SH4) + fatalerror("sh4_internal_r uses m_m[] with SH3\n", 0); + + UINT32 addr = (offset << 2) + 0xfe000000; + offset = ((addr & 0xfc) >> 2) | ((addr & 0x1fe0000) >> 11); + +// printf("sh4_internal_r: Read %08x (%x) @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), offset, mem_mask); + + switch( offset ) + { + case VERSION: + return PVR_SH7091; // 0x040205c1, this is what a real SH7091 in a Dreamcast returns - the later Naomi BIOSes check and care! + case PRR: + return 0; + case IPRD: + return 0x00000000; // SH7750 ignores writes here and always returns zero + case RTCNT: + if ((m_m[RTCSR] >> 3) & 7) + { // activated + //((double)rtcnt_div[(m_m[RTCSR] >> 3) & 7] / (double)100000000) + //return (refresh_timer_base + (m_refresh_timer->elapsed() * (double)100000000) / (double)rtcnt_div[(m_m[RTCSR] >> 3) & 7]) & 0xff; + return compute_ticks_refresh_timer(m_refresh_timer, m_bus_clock, m_refresh_timer_base, rtcnt_div[(m_m[RTCSR] >> 3) & 7]) & 0xff; + } + else + return m_m[RTCNT]; + +/********************************************************************************************************************* + INTC (Interrupt Controller) +*********************************************************************************************************************/ + + case IPRA: + return m_SH4_IPRA; + +/********************************************************************************************************************* + TMU (Timer Unit) +*********************************************************************************************************************/ + case SH4_TSTR_ADDR: return sh4_handle_tstr_addr_r(mem_mask); + case SH4_TCR0_ADDR: return sh4_handle_tcr0_addr_r(mem_mask); + case SH4_TCR1_ADDR: return sh4_handle_tcr1_addr_r(mem_mask); + case SH4_TCR2_ADDR: return sh4_handle_tcr2_addr_r(mem_mask); + case SH4_TCNT0_ADDR: return sh4_handle_tcnt0_addr_r(mem_mask); + case SH4_TCNT1_ADDR: return sh4_handle_tcnt1_addr_r(mem_mask); + case SH4_TCNT2_ADDR: return sh4_handle_tcnt2_addr_r(mem_mask); + case SH4_TCOR0_ADDR: return sh4_handle_tcor0_addr_r(mem_mask); + case SH4_TCOR1_ADDR: return sh4_handle_tcor1_addr_r(mem_mask); + case SH4_TCOR2_ADDR: return sh4_handle_tcor2_addr_r(mem_mask); + case SH4_TOCR_ADDR: return sh4_handle_tocr_addr_r(mem_mask); // not supported + case SH4_TCPR2_ADDR: return sh4_handle_tcpr2_addr_r(mem_mask); // not supported +/********************************************************************************************************************* + DMAC (DMA Controller) +*********************************************************************************************************************/ + case SH4_SAR0_ADDR: return sh4_handle_sar0_addr_r(mem_mask); + case SH4_SAR1_ADDR: return sh4_handle_sar1_addr_r(mem_mask); + case SH4_SAR2_ADDR: return sh4_handle_sar2_addr_r(mem_mask); + case SH4_SAR3_ADDR: return sh4_handle_sar3_addr_r(mem_mask); + case SH4_DAR0_ADDR: return sh4_handle_dar0_addr_r(mem_mask); + case SH4_DAR1_ADDR: return sh4_handle_dar1_addr_r(mem_mask); + case SH4_DAR2_ADDR: return sh4_handle_dar2_addr_r(mem_mask); + case SH4_DAR3_ADDR: return sh4_handle_dar3_addr_r(mem_mask); + case SH4_DMATCR0_ADDR: return sh4_handle_dmatcr0_addr_r(mem_mask); + case SH4_DMATCR1_ADDR: return sh4_handle_dmatcr1_addr_r(mem_mask); + case SH4_DMATCR2_ADDR: return sh4_handle_dmatcr2_addr_r(mem_mask); + case SH4_DMATCR3_ADDR: return sh4_handle_dmatcr3_addr_r(mem_mask); + case SH4_CHCR0_ADDR: return sh4_handle_chcr0_addr_r(mem_mask); + case SH4_CHCR1_ADDR: return sh4_handle_chcr1_addr_r(mem_mask); + case SH4_CHCR2_ADDR: return sh4_handle_chcr2_addr_r(mem_mask); + case SH4_CHCR3_ADDR: return sh4_handle_chcr3_addr_r(mem_mask); + case SH4_DMAOR_ADDR: return sh4_handle_dmaor_addr_r(mem_mask); +/********************************************************************************************************************* + I/O Ports +*********************************************************************************************************************/ + + case PDTRA: + if (m_m[BCR2] & 1) + return (m_io->read_dword(SH4_IOPORT_16) & ~m_ioport16_direction) | (m_m[PDTRA] & m_ioport16_direction); + break; + case PDTRB: + if (m_m[BCR2] & 1) + return (m_io->read_dword(SH4_IOPORT_4) & ~m_ioport4_direction) | (m_m[PDTRB] & m_ioport4_direction); + break; + + // SCIF (UART with FIFO) + case SCFSR2: + return 0x60; //read-only status register + } + return m_m[offset]; +} + +void sh4_set_frt_input(int state) +{ + if (m_cpu_type != CPU_TYPE_SH4) + fatalerror("sh4_set_frt_input uses m_m[] with SH3\n", 0); + + if(state == PULSE_LINE) + { + sh4_set_frt_input(ASSERT_LINE); + sh4_set_frt_input(CLEAR_LINE); + return; + } + + if(m_frt_input == state) { + return; + } + + m_frt_input = state; + + if (m_cpu_type == CPU_TYPE_SH4) + { + if(m_m[5] & 0x8000) { + if(state == CLEAR_LINE) { + return; + } + } else { + if(state == ASSERT_LINE) { + return; + } + } + } + else + { + fatalerror("sh4_set_frt_input uses m_m[] with SH3\n", 0); + } + +#if 0 + sh4_timer_resync(); + m_icr = m_frc; + m_m[4] |= ICF; + logerror("SH4 '%s': ICF activated (%x)\n", tag(), m_pc & AM); + sh4_recalc_irq(); +#endif +} + +static void sh4_set_irln_input(int value) +{ + if (m_irln == value) + return; + m_irln = value; + set_input_line(SH4_IRLn, ASSERT_LINE); + set_input_line(SH4_IRLn, CLEAR_LINE); +} + +// end no sh4 -dink +#endif + +static void execute_set_input(int irqline, int state) // set state of external interrupt line +{ + m_cpu_off = 0; //dink + if (m_cpu_type == CPU_TYPE_SH3) + { + /***** ASSUME THIS TO BE WRONG FOR NOW *****/ + + if (irqline == INPUT_LINE_NMI) + { + fatalerror("SH3 NMI Unimplemented\n", 0); + } + else + { + //bprintf(0, _T("IRQ: execute_set_input( %d, %d );\n"), irqline, state); + //if (irqline > SH4_IRL3) + // return; + if (m_irq_line_state[irqline] == state) + return; + m_irq_line_state[irqline] = state; + + if( state == CLEAR_LINE ) + { + LOG(("SH-4 '%s' cleared external irq IRL%d\n", tag(), irqline)); + sh4_exception_unrequest(SH4_INTC_IRL0+irqline-SH4_IRL0); + } + else + { + LOG(("SH-4 '%s' assert external irq IRL%d\n", tag(), irqline)); + sh4_exception_request(SH4_INTC_IRL0+irqline-SH4_IRL0); + } + + } + + /***** END ASSUME THIS TO BE WRONG FOR NOW *****/ + } + else + { +#if 0 + // no sh4 -dink + int s; + + if (irqline == INPUT_LINE_NMI) + { + if (m_nmi_line_state == state) + return; + if (m_m[ICR] & 0x100) + { + if ((state == CLEAR_LINE) && (m_nmi_line_state == ASSERT_LINE)) // rising + { + LOG(("SH-4 '%s' assert nmi\n", tag())); + sh4_exception_request(SH4_INTC_NMI); + sh4_dmac_nmi(); + } + } + else + { + if ((state == ASSERT_LINE) && (m_nmi_line_state == CLEAR_LINE)) // falling + { + LOG(("SH-4 '%s' assert nmi\n", tag())); + sh4_exception_request(SH4_INTC_NMI); + sh4_dmac_nmi(); + } + } + if (state == CLEAR_LINE) + m_m[ICR] ^= 0x8000; + else + m_m[ICR] |= 0x8000; + m_nmi_line_state = state; + } + else + { + if (m_m[ICR] & 0x80) // four independent external interrupt sources + { + if (irqline > SH4_IRL3) + return; + if (m_irq_line_state[irqline] == state) + return; + m_irq_line_state[irqline] = state; + + if( state == CLEAR_LINE ) + { + LOG(("SH-4 '%s' cleared external irq IRL%d\n", tag(), irqline)); + sh4_exception_unrequest(SH4_INTC_IRL0+irqline-SH4_IRL0); + } + else + { + LOG(("SH-4 '%s' assert external irq IRL%d\n", tag(), irqline)); + sh4_exception_request(SH4_INTC_IRL0+irqline-SH4_IRL0); + } + } + else // level-encoded interrupt + { + if (irqline != SH4_IRLn) + return; + if ((m_irln > 15) || (m_irln < 0)) + return; + for (s = 0; s < 15; s++) + sh4_exception_unrequest(SH4_INTC_IRLn0+s); + if (m_irln < 15) + sh4_exception_request(SH4_INTC_IRLn0+m_irln); + LOG(("SH-4 '%s' IRLn0-IRLn3 level #%d\n", tag(), m_irln)); + } + } + if (m_test_irq && (!m_delay)) + sh4_check_pending_irq(/*"sh4_set_irq_line"*/); + +// end no sh4 -dink +#endif + } +} + +void Sh3SetIRQLine(INT32 line, INT32 state) +{ + // state supports: ACK, NONE, HOLD -dink + execute_set_input(line, state); +} + +static void sh4_parse_configuration() +{ + if(c_clock > 0) + { + switch((c_md2 << 2) | (c_md1 << 1) | (c_md0)) + { + case 0: + m_cpu_clock = c_clock; + m_bus_clock = c_clock / 4; + m_pm_clock = c_clock / 4; + m_pm_divider = 4; + break; + case 1: + m_cpu_clock = c_clock; + m_bus_clock = c_clock / 6; + m_pm_clock = c_clock / 6; + m_pm_divider = 6; + break; + case 2: + m_cpu_clock = c_clock; + m_bus_clock = c_clock / 3; + m_pm_clock = c_clock / 6; + m_pm_divider = 6; + break; + case 3: + m_cpu_clock = c_clock; + m_bus_clock = c_clock / 3; + m_pm_clock = c_clock / 6; + m_pm_divider = 6; + break; + case 4: + m_cpu_clock = c_clock; + m_bus_clock = c_clock / 2; + m_pm_clock = c_clock / 4; + m_pm_divider = 4; + break; + case 5: + m_cpu_clock = c_clock; + m_bus_clock = c_clock / 2; + m_pm_clock = c_clock / 4; + m_pm_divider = 4; + break; + } + m_is_slave = (~(c_md7)) & 1; + } + else + { + m_cpu_clock = 200000000; + m_bus_clock = 100000000; + m_pm_clock = 50000000; + m_pm_divider = 4; + m_is_slave = 0; + } +} + +static UINT32 sh4_getsqremap(UINT32 address) +{ + if (!m_sh4_mmu_enabled) + return address; + else + { + int i; + UINT32 topaddr = address&0xfff00000; + + for (i=0;i<64;i++) + { + UINT32 topcmp = m_sh4_tlb_address[i]&0xfff00000; + if (topcmp==topaddr) + return (address&0x000fffff) | ((m_sh4_tlb_data[i])&0xfff00000); + } + + } + + return address; +} + +#if 0 +// no sh4 -dink + +READ64_MEMBER( sh4_base_device::sh4_tlb_r ) +{ + int offs = offset*8; + + if (offs >= 0x01000000) + { + UINT8 i = (offs>>8)&63; + return m_sh4_tlb_data[i]; + } + else + { + UINT8 i = (offs>>8)&63; + return m_sh4_tlb_address[i]; + } +} + +WRITE64_MEMBER( sh4_base_device::sh4_tlb_w ) +{ + int offs = offset*8; + + if (offs >= 0x01000000) + { + UINT8 i = (offs>>8)&63; + m_sh4_tlb_data[i] = data&0xffffffff; + } + else + { + UINT8 i = (offs>>8)&63; + m_sh4_tlb_address[i] = data&0xffffffff; + } +} +#endif diff --git a/src/cpu/sh4/sh4dmac.h b/src/cpu/sh4/sh4dmac.h new file mode 100644 index 000000000..27e56f348 --- /dev/null +++ b/src/cpu/sh4/sh4dmac.h @@ -0,0 +1,63 @@ +/* SHA3/4 DMA Controller */ + +/* bit definitions */ +#define CHCR_SSA 0xe0000000 +#define CHCR_STC 0x10000000 +#define CHCR_DSA 0x0e000000 +#define CHCR_DTC 0x01000000 +#define CHCR_DS 0x00080000 +#define CHCR_RL 0x00040000 +#define CHCR_AM 0x00020000 +#define CHCR_AL 0x00010000 +#define CHCR_DM 0x0000c000 +#define CHCR_SM 0x00003000 +#define CHCR_RS 0x00000f00 +#define CHCR_TM 0x00000080 +#define CHCR_TS 0x00000070 +#define CHCR_IE 0x00000004 +#define CHCR_TE 0x00000002 +#define CHCR_DE 0x00000001 + +#define DMAOR_DDT 0x8000 +#define DMAOR_PR 0x0300 +#define DMAOR_COD 0x0010 +#define DMAOR_AE 0x0004 +#define DMAOR_NMIF 0x0002 +#define DMAOR_DME 0x0001 + +static void sh4_dmac_callback(INT32 param); + +static void sh4_handle_sar0_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_sar1_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_sar2_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_sar3_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_dar0_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_dar1_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_dar2_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_dar3_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_dmatcr0_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_dmatcr1_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_dmatcr2_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_dmatcr3_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_chcr0_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_chcr1_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_chcr2_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_chcr3_addr_w(UINT32 data, UINT32 mem_mask); +static void sh4_handle_dmaor_addr_w(UINT32 data, UINT32 mem_mask); +static UINT32 sh4_handle_sar0_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_sar1_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_sar2_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_sar3_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_dar0_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_dar1_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_dar2_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_dar3_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_dmatcr0_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_dmatcr1_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_dmatcr2_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_dmatcr3_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_chcr0_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_chcr1_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_chcr2_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_chcr3_addr_r(UINT32 mem_mask); +static UINT32 sh4_handle_dmaor_addr_r(UINT32 mem_mask); diff --git a/src/cpu/sh4/sh4dmac.inc b/src/cpu/sh4/sh4dmac.inc new file mode 100644 index 000000000..63cca44c9 --- /dev/null +++ b/src/cpu/sh4/sh4dmac.inc @@ -0,0 +1,704 @@ +/* SHA3/4 DMA Controller */ + +/* +#include "emu.h" +#include "debugger.h" +#include "sh4.h" +#include "sh4comn.h" +#include "sh3comn.h" +#include "sh4dmac.h" +*/ + +static const int dmasize[8] = { 8, 1, 2, 4, 32, 0, 0, 0 }; + +static const int sh3_dmasize[4] = { 1, 2, 4, 16 }; + +static UINT32 sh4_handle_sar0_addr_r(UINT32 mem_mask) { return m_SH4_SAR0; } +static UINT32 sh4_handle_sar1_addr_r(UINT32 mem_mask) { return m_SH4_SAR1; } +static UINT32 sh4_handle_sar2_addr_r(UINT32 mem_mask) { return m_SH4_SAR2; } +static UINT32 sh4_handle_sar3_addr_r(UINT32 mem_mask) { return m_SH4_SAR3; } +static UINT32 sh4_handle_dar0_addr_r(UINT32 mem_mask) { return m_SH4_DAR0; } +static UINT32 sh4_handle_dar1_addr_r(UINT32 mem_mask) { return m_SH4_DAR1; } +static UINT32 sh4_handle_dar2_addr_r(UINT32 mem_mask) { return m_SH4_DAR2; } +static UINT32 sh4_handle_dar3_addr_r(UINT32 mem_mask) { return m_SH4_DAR3; } +static UINT32 sh4_handle_dmatcr0_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR0; } +static UINT32 sh4_handle_dmatcr1_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR1; } +static UINT32 sh4_handle_dmatcr2_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR2; } +static UINT32 sh4_handle_dmatcr3_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR3; } +static UINT32 sh4_handle_chcr0_addr_r(UINT32 mem_mask) { return m_SH4_CHCR0; } +static UINT32 sh4_handle_chcr1_addr_r(UINT32 mem_mask) { return m_SH4_CHCR1; } +static UINT32 sh4_handle_chcr2_addr_r(UINT32 mem_mask) { return m_SH4_CHCR2; } +static UINT32 sh4_handle_chcr3_addr_r(UINT32 mem_mask) { return m_SH4_CHCR3; } +static UINT32 sh4_handle_dmaor_addr_r(UINT32 mem_mask) { return m_SH4_DMAOR; } + +static void sh4_dmac_callback(INT32 param) +{ + int channel = param & 0xf; + + LOG(("SH4 '%s': DMA %d complete\n", tag(), channel)); + m_dma_timer_active[channel] = 0; + switch (channel) + { + case 0: + m_SH4_DMATCR0 = 0; + m_SH4_CHCR0 |= CHCR_TE; + if (m_SH4_CHCR0 & CHCR_IE) + sh4_exception_request(SH4_INTC_DMTE0); + break; + case 1: + m_SH4_DMATCR1 = 0; + m_SH4_CHCR1 |= CHCR_TE; + if (m_SH4_CHCR1 & CHCR_IE) + sh4_exception_request(SH4_INTC_DMTE1); + break; + case 2: + m_SH4_DMATCR2 = 0; + m_SH4_CHCR2 |= CHCR_TE; + if (m_SH4_CHCR2 & CHCR_IE) + sh4_exception_request(SH4_INTC_DMTE2); + break; + case 3: + m_SH4_DMATCR3 = 0; + m_SH4_CHCR3 |= CHCR_TE; + if (m_SH4_CHCR3 & CHCR_IE) + sh4_exception_request(SH4_INTC_DMTE3); + break; + } +} + +static int sh4_dma_transfer(int channel, int timermode, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr) +{ + int incs, incd, size; + UINT32 src, dst, count; + + incd = (chcr & CHCR_DM) >> 14; + incs = (chcr & CHCR_SM) >> 12; + + if (m_cpu_type == CPU_TYPE_SH4) + { + size = dmasize[(chcr & CHCR_TS) >> 4]; + } + else + { + size = sh3_dmasize[(chcr >> 3) & 3]; + } + + if(incd == 3 || incs == 3) + { + logerror("SH4: DMA: bad increment values (%d, %d, %d, %04x)\n", incd, incs, size, chcr); + return 0; + } + src = *sar; + dst = *dar; + count = *dmatcr; + if (!count) + count = 0x1000000; + + //LOG(("SH4: DMA %d start %x, %x, %x, %04x, %d, %d, %d\n", channel, src, dst, count, chcr, incs, incd, size)); + //bprintf(0, _T("SH4: DMA %d start %x, %x, %x, %04x, %d, %d, %d\n"), channel, src, dst, count, chcr, incs, incd, size); + + if (timermode == 1) // timer actvated after a time based on the number of words to transfer + { + INT32 cycles = 2*count+1; + m_dma_timer_active[channel] = 1; + //m_dma_timer[channel]->adjust(cycles_to_attotime(2*count+1), channel); + //bprintf(0, _T("dma timer %d cycles!\n"), cycles); + m_dma_timer[channel].start(cycles, -1, 1, 0); + } + else if (timermode == 2) // timer activated immediately + { + m_dma_timer_active[channel] = 1; + //m_dma_timer[channel]->adjust(attotime::zero, channel); + //bprintf(0, _T("dma timer now!\n")); + m_dma_timer[channel].start(0, -1, 1, 0); + } + + src &= AM; + dst &= AM; + + switch(size) + { + case 1: // 8 bit + for(;count > 0; count --) + { + if(incs == 2) + src --; + if(incd == 2) + dst --; + //m_program->write_byte(dst, m_program->read_byte(src)); + WB(dst, RB(src)); + if(incs == 1) + src ++; + if(incd == 1) + dst ++; + } + break; + case 2: // 16 bit + src &= ~1; + dst &= ~1; + for(;count > 0; count --) + { + if(incs == 2) + src -= 2; + if(incd == 2) + dst -= 2; + //m_program->write_word(dst, m_program->read_word(src)); + WW(dst, RW(src)); + if(incs == 1) + src += 2; + if(incd == 1) + dst += 2; + } + break; + case 8: // 64 bit + src &= ~7; + dst &= ~7; + for(;count > 0; count --) + { + if(incs == 2) + src -= 8; + if(incd == 2) + dst -= 8; + //m_program->write_qword(dst, m_program->read_qword(src)); + WL(dst, RL(src)); + WL(dst+4, RL(src+4)); + if(incs == 1) + src += 8; + if(incd == 1) + dst += 8; + + } + break; + case 4: // 32 bit + src &= ~3; + dst &= ~3; + for(;count > 0; count --) + { + if(incs == 2) + src -= 4; + if(incd == 2) + dst -= 4; + //m_program->write_dword(dst, m_program->read_dword(src)); + WL(dst, RL(src)); + if(incs == 1) + src += 4; + if(incd == 1) + dst += 4; + + } + break; + case 32: + src &= ~31; + dst &= ~31; + for(;count > 0; count --) + { + if(incs == 2) + src -= 32; + if(incd == 2) + dst -= 32; + //m_program->write_qword(dst, m_program->read_qword(src)); + //m_program->write_qword(dst+8, m_program->read_qword(src+8)); + //m_program->write_qword(dst+16, m_program->read_qword(src+16)); + //m_program->write_qword(dst+24, m_program->read_qword(src+24)); + WL(dst, RL(src)); WL(dst+4, RL(src+4)); + WL(dst+8, RL(src+8)); WL(dst+12, RL(src+12)); + WL(dst+16, RL(src+16)); WL(dst+20, RL(src+20)); + WL(dst+24, RL(src+24)); WL(dst+28, RL(src+28)); + if(incs == 1) + src += 32; + if(incd == 1) + dst += 32; + } + break; + } + *sar = (*sar & !AM) | src; + *dar = (*dar & !AM) | dst; + *dmatcr = count; + return 1; +} + +static int sh4_dma_transfer_device(int channel, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr) +{ + int incs, incd, size, mod; + UINT32 src, dst, count; + + incd = (chcr & CHCR_DM) >> 14; + incs = (chcr & CHCR_SM) >> 12; + + + if (m_cpu_type == CPU_TYPE_SH4) + { + size = dmasize[(chcr & CHCR_TS) >> 4]; + } + else + { + size = sh3_dmasize[(chcr >> 3) & 3]; + } + + mod = ((chcr & CHCR_RS) >> 8); + if (incd == 3 || incs == 3) + { + logerror("SH4: DMA: bad increment values (%d, %d, %d, %04x)\n", incd, incs, size, chcr); + return 0; + } + src = *sar; + dst = *dar; + count = *dmatcr; + if (!count) + count = 0x1000000; + + LOG(("SH4: DMA %d start device<->memory %x, %x, %x, %04x, %d, %d, %d\n", channel, src, dst, count, chcr, incs, incd, size)); + + m_dma_timer_active[channel] = 1; + + src &= AM; + dst &= AM; + + // remember parameters + m_dma_source[channel]=src; + m_dma_destination[channel]=dst; + m_dma_count[channel]=count; + m_dma_wordsize[channel]=size; + m_dma_source_increment[channel]=incs; + m_dma_destination_increment[channel]=incd; + m_dma_mode[channel]=mod; + + // inform device its ready to transfer + //m_io->write_dword(SH4_IOPORT_DMA, channel | (mod << 16)); + WritePort(SH4_IOPORT_DMA, channel | (mod << 16)); + + return 1; +} + +static void sh4_dmac_check(int channel) +{ + UINT32 dmatcr, chcr, sar, dar; + + switch (channel) + { + case 0: + sar = m_SH4_SAR0; + dar = m_SH4_DAR0; + chcr = m_SH4_CHCR0; + dmatcr = m_SH4_DMATCR0; + break; + case 1: + sar = m_SH4_SAR1; + dar = m_SH4_DAR1; + chcr = m_SH4_CHCR1; + dmatcr = m_SH4_DMATCR1; + break; + case 2: + sar = m_SH4_SAR2; + dar = m_SH4_DAR2; + chcr = m_SH4_CHCR2; + dmatcr = m_SH4_DMATCR2; + break; + case 3: + sar = m_SH4_SAR3; + dar = m_SH4_DAR3; + chcr = m_SH4_CHCR3; + dmatcr = m_SH4_DMATCR3; + break; + default: + return; + } + if (chcr & m_SH4_DMAOR & DMAOR_DME) + { + if ((((chcr & CHCR_RS) >> 8) < 2) || (((chcr & CHCR_RS) >> 8) > 6)) + return; + if (!m_dma_timer_active[channel] && !(chcr & CHCR_TE) && !(m_SH4_DMAOR & (DMAOR_AE | DMAOR_NMIF))) + { + if (((chcr & CHCR_RS) >> 8) > 3) + sh4_dma_transfer(channel, 1, chcr, &sar, &dar, &dmatcr); + else if ((m_SH4_DMAOR & DMAOR_DDT) == 0) + sh4_dma_transfer_device(channel, chcr, &sar, &dar, &dmatcr); // tell device we are ready to transfer + } + } + else + { + if (m_dma_timer_active[channel]) + { + logerror("SH4: DMA %d cancelled in-flight but all data transferred", channel); + //m_dma_timer[channel]->adjust(attotime::never, channel); + m_dma_timer[channel].stop(); + m_dma_timer_active[channel] = 0; + } + } +} + +#if 0 +// sh3-only core for now -dink + +// called by drivers to transfer data in a cpu<->device dma. 'device' must be a SH4 cpu +static int sh4_dma_data(struct sh4_device_dma *s) +{ + UINT32 pos, len, siz; + int channel = s->channel; + void *data = s->buffer; + + if (!m_dma_timer_active[channel]) + return 0; + + if (m_dma_mode[channel] == 2) + { + // device receives data + len = m_dma_count[channel]; + if (s->length < len) + len = s->length; + siz = m_dma_wordsize[channel]; + for (pos = 0;pos < len;pos++) { + switch (siz) + { + case 8: + if (m_dma_source_increment[channel] == 2) + m_dma_source[channel] -= 8; + *(UINT64 *)data = m_program->read_qword(m_dma_source[channel] & ~7); + if (m_dma_source_increment[channel] == 1) + m_dma_source[channel] += 8; + break; + case 1: + if (m_dma_source_increment[channel] == 2) + m_dma_source[channel]--; + *(UINT8 *)data = m_program->read_byte(m_dma_source[channel]); + if (m_dma_source_increment[channel] == 1) + m_dma_source[channel]++; + break; + case 2: + if (m_dma_source_increment[channel] == 2) + m_dma_source[channel] -= 2; + *(UINT16 *)data = m_program->read_word(m_dma_source[channel] & ~1); + if (m_dma_source_increment[channel] == 1) + m_dma_source[channel] += 2; + break; + case 4: + if (m_dma_source_increment[channel] == 2) + m_dma_source[channel] -= 4; + *(UINT32 *)data = m_program->read_dword(m_dma_source[channel] & ~3); + if (m_dma_source_increment[channel] == 1) + m_dma_source[channel] += 4; + break; + case 32: + if (m_dma_source_increment[channel] == 2) + m_dma_source[channel] -= 32; + *(UINT64 *)data = m_program->read_qword(m_dma_source[channel] & ~31); + *((UINT64 *)data+1) = m_program->read_qword((m_dma_source[channel] & ~31)+8); + *((UINT64 *)data+2) = m_program->read_qword((m_dma_source[channel] & ~31)+16); + *((UINT64 *)data+3) = m_program->read_qword((m_dma_source[channel] & ~31)+24); + if (m_dma_source_increment[channel] == 1) + m_dma_source[channel] += 32; + break; + } + m_dma_count[channel]--; + } + if (m_dma_count[channel] == 0) // all data transferred ? + { + m_dma_timer[channel]->adjust(attotime::zero, channel); + return 2; + } + return 1; + } + else if (m_dma_mode[channel] == 3) + { + // device sends data + len = m_dma_count[channel]; + if (s->length < len) + len = s->length; + siz = m_dma_wordsize[channel]; + for (pos = 0;pos < len;pos++) { + switch (siz) + { + case 8: + if (m_dma_destination_increment[channel] == 2) + m_dma_destination[channel]-=8; + m_program->write_qword(m_dma_destination[channel] & ~7, *(UINT64 *)data); + if (m_dma_destination_increment[channel] == 1) + m_dma_destination[channel]+=8; + break; + case 1: + if (m_dma_destination_increment[channel] == 2) + m_dma_destination[channel]--; + m_program->write_byte(m_dma_destination[channel], *(UINT8 *)data); + if (m_dma_destination_increment[channel] == 1) + m_dma_destination[channel]++; + break; + case 2: + if (m_dma_destination_increment[channel] == 2) + m_dma_destination[channel]-=2; + m_program->write_word(m_dma_destination[channel] & ~1, *(UINT16 *)data); + if (m_dma_destination_increment[channel] == 1) + m_dma_destination[channel]+=2; + break; + case 4: + if (m_dma_destination_increment[channel] == 2) + m_dma_destination[channel]-=4; + m_program->write_dword(m_dma_destination[channel] & ~3, *(UINT32 *)data); + if (m_dma_destination_increment[channel] == 1) + m_dma_destination[channel]+=4; + break; + case 32: + if (m_dma_destination_increment[channel] == 2) + m_dma_destination[channel]-=32; + m_program->write_qword(m_dma_destination[channel] & ~31, *(UINT64 *)data); + m_program->write_qword((m_dma_destination[channel] & ~31)+8, *((UINT64 *)data+1)); + m_program->write_qword((m_dma_destination[channel] & ~31)+16, *((UINT64 *)data+2)); + m_program->write_qword((m_dma_destination[channel] & ~31)+24, *((UINT64 *)data+3)); + if (m_dma_destination_increment[channel] == 1) + m_dma_destination[channel]+=32; + break; + } + m_dma_count[channel]--; + } + + if (m_dma_count[channel] == 0) // all data transferred ? + { + m_dma_timer[channel]->adjust(attotime::zero, channel); + return 2; + } + return 1; + } + else + return 0; +} + +// called by drivers to transfer data in a DDT dma. +static void sh4_dma_ddt(struct sh4_ddt_dma *s) +{ + UINT32 chcr; + UINT32 *p32bits; + UINT64 *p32bytes; + UINT32 pos,len,siz; + + if (m_cpu_type != CPU_TYPE_SH4) + fatalerror("sh4_dma_ddt uses m_m[] with SH3\n"); + + if (m_dma_timer_active[s->channel]) + return; + if (s->mode >= 0) { + switch (s->channel) + { + case 0: + if (s->mode & 1) + s->source = m_SH4_SAR0; + if (s->mode & 2) + m_SH4_SAR0 = s->source; + if (s->mode & 4) + s->destination = m_SH4_DAR0; + if (s->mode & 8) + m_SH4_DAR0 = s->destination; + break; + case 1: + if (s->mode & 1) + s->source = m_SH4_SAR1; + if (s->mode & 2) + m_SH4_SAR1 = s->source; + if (s->mode & 4) + s->destination = m_SH4_DAR1; + if (s->mode & 8) + m_SH4_DAR1 = s->destination; + break; + case 2: + if (s->mode & 1) + s->source = m_SH4_SAR2; + if (s->mode & 2) + m_SH4_SAR2 = s->source; + if (s->mode & 4) + s->destination = m_SH4_DAR2; + if (s->mode & 8) + m_SH4_DAR2 = s->destination; + break; + case 3: + default: + if (s->mode & 1) + s->source = m_SH4_SAR3; + if (s->mode & 2) + m_SH4_SAR3 = s->source; + if (s->mode & 4) + s->destination = m_SH4_DAR3; + if (s->mode & 8) + m_SH4_DAR3 = s->destination; + break; + } + switch (s->channel) + { + case 0: + chcr = m_SH4_CHCR0; + len = m_SH4_DMATCR0; + break; + case 1: + chcr = m_SH4_CHCR1; + len = m_SH4_DMATCR1; + break; + case 2: + chcr = m_SH4_CHCR2; + len = m_SH4_DMATCR2; + break; + case 3: + default: + chcr = m_SH4_CHCR3; + len = m_SH4_DMATCR3; + break; + } + if ((s->direction) == 0) { + chcr = (chcr & 0xffff3fff) | ((s->mode & 0x30) << 10); + } else { + chcr = (chcr & 0xffffcfff) | ((s->mode & 0x30) << 8); + } + + + if (m_cpu_type == CPU_TYPE_SH4) + { + //siz = dmasize[(chcr & CHCR_TS) >> 4]; + siz = dmasize[(chcr >> 4) & 7]; + } + else + { + siz = sh3_dmasize[(chcr >> 3) & 3]; + } + + + if (siz && (s->size)) + if ((len * siz) != (s->length * s->size)) + return; + sh4_dma_transfer(s->channel, 0, chcr, &s->source, &s->destination, &len); + } else { + if (s->size == 4) { + if ((s->direction) == 0) { + len = s->length; + p32bits = (UINT32 *)(s->buffer); + for (pos = 0;pos < len;pos++) { + *p32bits = m_program->read_dword(s->source); + p32bits++; + s->source = s->source + 4; + } + } else { + len = s->length; + p32bits = (UINT32 *)(s->buffer); + for (pos = 0;pos < len;pos++) { + m_program->write_dword(s->destination, *p32bits); + p32bits++; + s->destination = s->destination + 4; + } + } + } + if (s->size == 32) { + if ((s->direction) == 0) { + len = s->length * 4; + p32bytes = (UINT64 *)(s->buffer); + for (pos = 0;pos < len;pos++) { + *p32bytes = m_program->read_qword(s->source); + p32bytes++; + s->destination = s->destination + 8; + } + } else { + len = s->length * 4; + p32bytes = (UINT64 *)(s->buffer); + for (pos = 0;pos < len;pos++) { + m_program->write_qword(s->destination, *p32bytes); + p32bytes++; + s->destination = s->destination + 8; + } + } + } + } +} +#endif // end sh4-disabled -dink + +static void sh4_handle_sar0_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_SAR0); +} + +static void sh4_handle_sar1_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_SAR1); +} + +static void sh4_handle_sar2_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_SAR2); +} + +static void sh4_handle_sar3_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_SAR3); +} + +static void sh4_handle_dar0_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_DAR0); +} + +static void sh4_handle_dar1_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_DAR1); +} + +static void sh4_handle_dar2_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_DAR2); +} + +static void sh4_handle_dar3_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_DAR3); +} + +static void sh4_handle_dmatcr0_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_DMATCR0); +} + +static void sh4_handle_dmatcr1_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_DMATCR1); +} + +static void sh4_handle_dmatcr2_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_DMATCR2); +} + +static void sh4_handle_dmatcr3_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_DMATCR3); +} + +static void sh4_handle_chcr0_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_CHCR0); + sh4_dmac_check(0); +} + +static void sh4_handle_chcr1_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_CHCR1); + sh4_dmac_check(1); +} + +static void sh4_handle_chcr2_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_CHCR2); + sh4_dmac_check(2); +} + +static void sh4_handle_chcr3_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_CHCR3); + sh4_dmac_check(3); +} + +static void sh4_handle_dmaor_addr_w(UINT32 data, UINT32 mem_mask) +{ + UINT32 old = m_SH4_DMAOR; + COMBINE_DATA(&m_SH4_DMAOR); + + if ((m_SH4_DMAOR & DMAOR_AE) && (~old & DMAOR_AE)) + m_SH4_DMAOR &= ~DMAOR_AE; + if ((m_SH4_DMAOR & DMAOR_NMIF) && (~old & DMAOR_NMIF)) + m_SH4_DMAOR &= ~DMAOR_NMIF; + sh4_dmac_check(0); + sh4_dmac_check(1); + sh4_dmac_check(2); + sh4_dmac_check(3); +} diff --git a/src/cpu/sh4/sh4regs.h b/src/cpu/sh4/sh4regs.h new file mode 100644 index 000000000..8fc26a207 --- /dev/null +++ b/src/cpu/sh4/sh4regs.h @@ -0,0 +1,181 @@ +#pragma once + +#ifndef __SH4REGS_H__ +#define __SH4REGS_H__ + +/* 00000001111111100000000011111100 */ +#define PTEH 0x2000 /* FF000000 */ +#define PTEL 0x2001 /* FF000004 */ +#define TTB 0x2002 /* FF000008 */ +#define TEA 0x2003 /* FF00000C */ +#define MMUCR 0x2004 /* FF000010 */ +#define BASRA 0x2005 /* FF000014 */ +#define BASRB 0x2006 /* FF000018 */ +#define CCR 0x2007 /* FF00001C */ +#define TRA 0x2008 /* FF000020 */ +#define EXPEVT 0x2009 /* FF000024 */ +#define INTEVT 0x200A /* FF000028 */ +#define VERSION 0x200C /* FF000030 */ +#define PTEA 0x200D /* FF000034 */ +#define QACR0 0x200E /* FF000038 */ +#define QACR1 0x200F /* FF00003C */ +#define PRR 0x2011 /* FF000044 */ +#define BARA 0x2400 /* FF200000 */ +#define BAMRA 0x2401 /* FF200004 */ +#define BBRA 0x2402 /* FF200008 */ +#define BARB 0x2403 /* FF20000C */ +#define BAMRB 0x2404 /* FF200010 */ +#define BBRB 0x2405 /* FF200014 */ +#define BDRB 0x2406 /* FF200018 */ +#define BDMRB 0x2407 /* FF20001C */ +#define BRCR 0x2408 /* FF200020 */ +#define BCR1 0x3000 /* FF800000 */ +#define BCR2 0x3001 /* FF800004 */ +#define BCR3 0x3014 /* FF800050 */ +#define BCR4 0x17C /* FE0A00F0 */ +#define WCR1 0x3002 /* FF800008 */ +#define WCR2 0x3003 /* FF80000C */ +#define WCR3 0x3004 /* FF800010 */ +#define MCR 0x3005 /* FF800014 */ +#define PCR 0x3006 /* FF800018 */ +#define RTCSR 0x3007 /* FF80001C */ +#define RTCNT 0x3008 /* FF800020 */ +#define RTCOR 0x3009 /* FF800024 */ +#define RFCR 0x300A /* FF800028 */ +#define PCTRA 0x300B /* FF80002C */ +#define PDTRA 0x300C /* FF800030 */ +#define PCTRB 0x3010 /* FF800040 */ +#define PDTRB 0x3011 /* FF800044 */ +#define GPIOIC 0x3012 /* FF800048 */ +#define SDMR2 0x3200 /* FF900000 */ +#define SDMR3 0x3280 /* FF940000 */ +#define SH4_SAR0_ADDR 0x3400 /* FFA00000 */ +#define SH4_DAR0_ADDR 0x3401 /* FFA00004 */ +#define SH4_DMATCR0_ADDR 0x3402 /* FFA00008 */ +#define SH4_CHCR0_ADDR 0x3403 /* FFA0000C */ +#define SH4_SAR1_ADDR 0x3404 /* FFA00010 */ +#define SH4_DAR1_ADDR 0x3405 /* FFA00014 */ +#define SH4_DMATCR1_ADDR 0x3406 /* FFA00018 */ +#define SH4_CHCR1_ADDR 0x3407 /* FFA0001C */ +#define SH4_SAR2_ADDR 0x3408 /* FFA00020 */ +#define SH4_DAR2_ADDR 0x3409 /* FFA00024 */ +#define SH4_DMATCR2_ADDR 0x340A /* FFA00028 */ +#define SH4_CHCR2_ADDR 0x340B /* FFA0002C */ +#define SH4_SAR3_ADDR 0x340C /* FFA00030 */ +#define SH4_DAR3_ADDR 0x340D /* FFA00034 */ +#define SH4_DMATCR3_ADDR 0x340E /* FFA00038 */ +#define SH4_CHCR3_ADDR 0x340F /* FFA0003C */ +#define SH4_DMAOR_ADDR 0x3410 /* FFA00040 */ +#define SAR4 0x3414 /* FFA00050 */ +#define DAR4 0x3415 /* FFA00054 */ +#define DMATCR4 0x3416 /* FFA00058 */ +#define CHCR4 0x3417 /* FFA0005C */ +#define SAR5 0x3418 /* FFA00060 */ +#define DAR5 0x3419 /* FFA00064 */ +#define DMATCR5 0x341A /* FFA00068 */ +#define CHCR5 0x341B /* FFA0006C */ +#define SAR6 0x341C /* FFA00070 */ +#define DAR6 0x341D /* FFA00074 */ +#define DMATCR6 0x341E /* FFA00078 */ +#define CHCR6 0x341F /* FFA0007C */ +#define SAR7 0x3420 /* FFA00080 */ +#define DAR7 0x3421 /* FFA00084 */ +#define DMATCR7 0x3422 /* FFA00088 */ +#define CHCR7 0x3423 /* FFA0008C */ +#define FRQCR 0x3800 /* FFC00000 */ +#define STBCR 0x3801 /* FFC00004 */ +#define WTCNT 0x3802 /* FFC00008 */ +#define WTCSR 0x3803 /* FFC0000C */ +#define STBCR2 0x3804 /* FFC00010 */ +#define R64CNT 0x3900 /* FFC80000 */ +#define RSECCNT 0x3901 /* FFC80004 */ +#define RMINCNT 0x3902 /* FFC80008 */ +#define RHRCNT 0x3903 /* FFC8000C */ +#define RWKCNT 0x3904 /* FFC80010 */ +#define RDAYCNT 0x3905 /* FFC80014 */ +#define RMONCNT 0x3906 /* FFC80018 */ +#define RYRCNT 0x3907 /* FFC8001C */ +#define RSECAR 0x3908 /* FFC80020 */ +#define RMINAR 0x3909 /* FFC80024 */ +#define RHRAR 0x390A /* FFC80028 */ +#define RWKAR 0x390B /* FFC8002C */ +#define RDAYAR 0x390C /* FFC80030 */ +#define RMONAR 0x390D /* FFC80034 */ +#define RCR1 0x390E /* FFC80038 */ +#define RCR2 0x390F /* FFC8003C */ +#define RCR3 0x3914 /* FFC80050 */ +#define RYRAR 0x3915 /* FFC80054 */ +#define ICR 0x3A00 /* FFD00000 */ +#define IPRA 0x3A01 /* FFD00004 */ +#define IPRB 0x3A02 /* FFD00008 */ +#define IPRC 0x3A03 /* FFD0000C */ +#define IPRD 0x3A04 /* FFD00010 */ +#define INTPRI00 0x100 /* FE080000 */ +#define INTREQ00 0x108 /* FE080020 */ +#define INTMSK00 0x110 /* FE080040 */ +#define INTMSKCLR00 0x118 /* FE080060 */ +#define CLKSTP00 0x140 /* FE0A0000 */ +#define CLKSTPCLR00 0x142 /* FE0A0008 */ +#define TSTR2 0x201 /* FE100004 */ +#define TCOR3 0x202 /* FE100008 */ +#define TCNT3 0x203 /* FE10000C */ +#define TCR3 0x204 /* FE100010 */ +#define TCOR4 0x205 /* FE100014 */ +#define TCNT4 0x206 /* FE100018 */ +#define TCR4 0x207 /* FE10001C */ +#define SH4_TOCR_ADDR 0x3B00 /* FFD80000 */ +#define SH4_TSTR_ADDR 0x3B01 /* FFD80004 */ +#define SH4_TCOR0_ADDR 0x3B02 /* FFD80008 */ +#define SH4_TCNT0_ADDR 0x3B03 /* FFD8000C */ +#define SH4_TCR0_ADDR 0x3B04 /* FFD80010 */ +#define SH4_TCOR1_ADDR 0x3B05 /* FFD80014 */ +#define SH4_TCNT1_ADDR 0x3B06 /* FFD80018 */ +#define SH4_TCR1_ADDR 0x3B07 /* FFD8001C */ +#define SH4_TCOR2_ADDR 0x3B08 /* FFD80020 */ +#define SH4_TCNT2_ADDR 0x3B09 /* FFD80024 */ +#define SH4_TCR2_ADDR 0x3B0A /* FFD80028 */ +#define SH4_TCPR2_ADDR 0x3B0B /* FFD8002C */ +#define SCSMR1 0x3C00 /* FFE00000 */ +#define SCBRR1 0x3C01 /* FFE00004 */ +#define SCSCR1 0x3C02 /* FFE00008 */ +#define SCTDR1 0x3C03 /* FFE0000C */ +#define SCSSR1 0x3C04 /* FFE00010 */ +#define SCRDR1 0x3C05 /* FFE00014 */ +#define SCSCMR1 0x3C06 /* FFE00018 */ +#define SCSPTR1 0x3C07 /* FFE0001C */ +#define SCSMR2 0x3D00 /* FFE80000 */ +#define SCBRR2 0x3D01 /* FFE80004 */ +#define SCSCR2 0x3D02 /* FFE80008 */ +#define SCFTDR2 0x3D03 /* FFE8000C */ +#define SCFSR2 0x3D04 /* FFE80010 */ +#define SCFRDR2 0x3D05 /* FFE80014 */ +#define SCFCR2 0x3D06 /* FFE80018 */ +#define SCFDR2 0x3D07 /* FFE8001C */ +#define SCSPTR2 0x3D08 /* FFE80020 */ +#define SCLSR2 0x3D09 /* FFE80024 */ +#define SDIR 0x3E00 /* FFF00000 */ +#define SDDR 0x3E02 /* FFF00008 */ +#define SDINT 0x3E05 /* FFF00014 */ +#define SIZEREGS 15878 + + + +#define MMUCR_LRUI 0xfc000000 +#define MMUCR_URB 0x00fc0000 +#define MMUCR_URC 0x0000fc00 +#define MMUCR_SQMD 0x00000200 +#define MMUCR_SV 0x00000100 +#define MMUCR_TI 0x00000004 +#define MMUCR_AT 0x00000001 + +/* constants */ +#define PVR_SH7091 0x040205c1 +#define PVR_SH7750 0x04020500 // from TN-SH7-361B/E +#define PVR_SH7750S 0x04020600 +#define PVR_SH7750R 0x04050000 +#define PRR_SH7750R 0x00000100 +#define PVR_SH7751 0x04110000 +#define PVR_SH7751R 0x04050000 +#define PRR_SH7751R 0x00000110 + +#endif /* __SH4REGS_H__ */ diff --git a/src/cpu/sh4/sh4tmu.h b/src/cpu/sh4/sh4tmu.h new file mode 100644 index 000000000..84840d24e --- /dev/null +++ b/src/cpu/sh4/sh4tmu.h @@ -0,0 +1 @@ +/* SH3/4 Timer Unit */ diff --git a/src/cpu/sh4/sh4tmu.inc b/src/cpu/sh4/sh4tmu.inc new file mode 100644 index 000000000..eb83b6355 --- /dev/null +++ b/src/cpu/sh4/sh4tmu.inc @@ -0,0 +1,323 @@ +/* SH3/4 Timer Unit */ + +/*#include "emu.h" +#include "debugger.h" +#include "sh4.h" +#include "sh4comn.h" +#include "sh3comn.h" +#include "sh4tmu.h"*/ + +static const int tcnt_div[8] = { 4, 16, 64, 256, 1024, 1, 1, 1 }; + +/*------------------------------------------------- + sh4_scale_up_mame_time - multiply a attotime by + a (constant+1) where 0 <= constant < 2^32 +-------------------------------------------------*/ + +/*INLINE attotime sh4_scale_up_mame_time(const attotime &_time1, UINT32 factor1) +{ + return _time1 * factor1 + _time1; +}*/ + +static UINT32 compute_ticks_timer(int timer_num, int hertz, int divisor) +{ + //double ret=((timer->remaining().as_double() * (double)hertz) / (double)divisor) - 1; + return (m_timer[timer_num].timeleft()) - 1; +} + +static void sh4_timer_recompute(int which) +{ +// double ticks; + + UINT32 tcnt = 0; + UINT32 tcr = 0; + switch (which) + { + case 0: + tcr = m_SH4_TCR0; + tcnt = m_SH4_TCNT0; + break; + + case 1: + tcr = m_SH4_TCR1; + tcnt = m_SH4_TCNT1; + break; + + case 2: + tcr = m_SH4_TCR2; + tcnt = m_SH4_TCNT2; + break; + } + + //ticks = tcnt; + //m_timer[which]->adjust(sh4_scale_up_mame_time(attotime::from_hz(m_pm_clock) * tcnt_div[tcr & 7], ticks), which); + //bprintf(0, _T("sh4_timer_recompute(), starting timer #%d\n"), which); + m_timer[which].set_prescaler((m_pm_divider) * (tcnt_div[tcr & 7])); + m_timer[which].start(tcnt, which, 1, 0); +} + + +static void sh4_timer_callback(int param) +{ + int which = param; + m_cpu_off = 0; //dink + switch (which) + { + case 0: + m_SH4_TCNT0 = m_SH4_TCOR0; + break; + + case 1: + m_SH4_TCNT1 = m_SH4_TCOR1; + break; + + case 2: + m_SH4_TCNT2 = m_SH4_TCOR2; + break; + + } + + sh4_timer_recompute(which); + + switch (which) + { + case 0: + m_SH4_TCR0 |= 0x100; + break; + + case 1: + m_SH4_TCR1 |= 0x100; + break; + + case 2: + m_SH4_TCR2 |= 0x100; + break; + + } + + switch (which) + { + case 0: + if (m_SH4_TCR0 & 0x20) + { + sh4_exception_request(SH4_INTC_TUNI0); + // logerror("SH4_INTC_TUNI0 requested\n"); + } + break; + + case 1: + if (m_SH4_TCR1 & 0x20) + { + sh4_exception_request(SH4_INTC_TUNI1); + // logerror("SH4_INTC_TUNI1 requested\n"); + } + break; + + case 2: + if (m_SH4_TCR2 & 0x20) + { + sh4_exception_request(SH4_INTC_TUNI2); + // logerror("SH4_INTC_TUNI2 requested\n"); + } + break; + + } +} + + +static UINT32 sh4_handle_tcnt0_addr_r(UINT32 mem_mask) +{ + if (m_SH4_TSTR & 1) + return compute_ticks_timer(0, m_pm_clock, tcnt_div[m_SH4_TCR0 & 7]); + else + return m_SH4_TCNT0; +} + +static UINT32 sh4_handle_tcnt1_addr_r(UINT32 mem_mask) +{ + if (m_SH4_TSTR & 2) + return compute_ticks_timer(1, m_pm_clock, tcnt_div[m_SH4_TCR1 & 7]); + else + return m_SH4_TCNT1; +} + +static UINT32 sh4_handle_tcnt2_addr_r(UINT32 mem_mask) +{ + if (m_SH4_TSTR & 4) + return compute_ticks_timer(2, m_pm_clock, tcnt_div[m_SH4_TCR2 & 7]); + else + return m_SH4_TCNT2; +} + +static UINT32 sh4_handle_tcor0_addr_r(UINT32 mem_mask) +{ + return m_SH4_TCOR0; +} + +static UINT32 sh4_handle_tcor1_addr_r(UINT32 mem_mask) +{ + return m_SH4_TCOR1; +} + +static UINT32 sh4_handle_tcor2_addr_r(UINT32 mem_mask) +{ + return m_SH4_TCOR2; +} + +static UINT32 sh4_handle_tcr0_addr_r(UINT32 mem_mask) +{ + return m_SH4_TCR0; +} + +static UINT32 sh4_handle_tcr1_addr_r(UINT32 mem_mask) +{ + return m_SH4_TCR1; +} + +static UINT32 sh4_handle_tcr2_addr_r(UINT32 mem_mask) +{ + return m_SH4_TCR2; +} + +static UINT32 sh4_handle_tstr_addr_r(UINT32 mem_mask) +{ + return m_SH4_TSTR; +} + +static UINT32 sh4_handle_tocr_addr_r(UINT32 mem_mask) +{ + return m_SH4_TOCR; +} + +static UINT32 sh4_handle_tcpr2_addr_r(UINT32 mem_mask) +{ + return m_SH4_TCPR2; +} + + +static void sh4_handle_tstr_addr_w(UINT32 data, UINT32 mem_mask) +{ + UINT32 old2 = m_SH4_TSTR; + COMBINE_DATA(&m_SH4_TSTR); + + if (old2 & 1) + m_SH4_TCNT0 = compute_ticks_timer(0, m_pm_clock, tcnt_div[m_SH4_TCR0 & 7]); + if ((m_SH4_TSTR & 1) == 0) { + m_timer[0].stop(); + } else + sh4_timer_recompute(0); + + if (old2 & 2) + m_SH4_TCNT1 = compute_ticks_timer(1, m_pm_clock, tcnt_div[m_SH4_TCR1 & 7]); + if ((m_SH4_TSTR & 2) == 0) { + m_timer[1].stop(); + } else + sh4_timer_recompute(1); + + if (old2 & 4) + m_SH4_TCNT2 = compute_ticks_timer(2, m_pm_clock, tcnt_div[m_SH4_TCR2 & 7]); + if ((m_SH4_TSTR & 4) == 0) { + m_timer[2].stop(); + } else + sh4_timer_recompute(2); +} + +static void sh4_handle_tcr0_addr_w(UINT32 data, UINT32 mem_mask) +{ + UINT32 old2 = m_SH4_TCR0; + COMBINE_DATA(&m_SH4_TCR0); + if (m_SH4_TSTR & 1) + { + m_SH4_TCNT0 = compute_ticks_timer(0, m_pm_clock, tcnt_div[old2 & 7]); + sh4_timer_recompute(0); + } + if (!(m_SH4_TCR0 & 0x20) || !(m_SH4_TCR0 & 0x100)) + sh4_exception_unrequest(SH4_INTC_TUNI0); +} + +static void sh4_handle_tcr1_addr_w(UINT32 data, UINT32 mem_mask) +{ + UINT32 old2 = m_SH4_TCR1; + COMBINE_DATA(&m_SH4_TCR1); + if (m_SH4_TSTR & 2) + { + m_SH4_TCNT1 = compute_ticks_timer(1, m_pm_clock, tcnt_div[old2 & 7]); + sh4_timer_recompute(1); + } + if (!(m_SH4_TCR1 & 0x20) || !(m_SH4_TCR1 & 0x100)) + sh4_exception_unrequest(SH4_INTC_TUNI1); +} + +static void sh4_handle_tcr2_addr_w(UINT32 data, UINT32 mem_mask) +{ + UINT32 old2 = m_SH4_TCR2; + COMBINE_DATA(&m_SH4_TCR2); + if (m_SH4_TSTR & 4) + { + m_SH4_TCNT2 = compute_ticks_timer(2, m_pm_clock, tcnt_div[old2 & 7]); + sh4_timer_recompute(2); + } + if (!(m_SH4_TCR2 & 0x20) || !(m_SH4_TCR2 & 0x100)) + sh4_exception_unrequest(SH4_INTC_TUNI2); +} + +static void sh4_handle_tcor0_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_TCOR0); + if (m_SH4_TSTR & 1) + { + m_SH4_TCNT0 = compute_ticks_timer(0, m_pm_clock, tcnt_div[m_SH4_TCR0 & 7]); + sh4_timer_recompute(0); + } +} + +static void sh4_handle_tcor1_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_TCOR1); + if (m_SH4_TSTR & 2) + { + m_SH4_TCNT1 = compute_ticks_timer(1, m_pm_clock, tcnt_div[m_SH4_TCR1 & 7]); + sh4_timer_recompute(1); + } +} + +static void sh4_handle_tcor2_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_TCOR2); + if (m_SH4_TSTR & 4) + { + m_SH4_TCNT2 = compute_ticks_timer(2, m_pm_clock, tcnt_div[m_SH4_TCR2 & 7]); + sh4_timer_recompute(2); + } +} + +static void sh4_handle_tcnt0_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_TCNT0); + if (m_SH4_TSTR & 1) + sh4_timer_recompute(0); +} + +static void sh4_handle_tcnt1_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_TCNT1); + if (m_SH4_TSTR & 2) + sh4_timer_recompute(1); +} + +static void sh4_handle_tcnt2_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_TCNT2); + if (m_SH4_TSTR & 4) + sh4_timer_recompute(2); +} + +static void sh4_handle_tocr_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_TOCR); +} + +static void sh4_handle_tcpr2_addr_w(UINT32 data, UINT32 mem_mask) +{ + COMBINE_DATA(&m_SH4_TCPR2); +}