make happy tlcs90.cpp. fixed icount in tlcs90Run, timer_period hack in init (needs to be properly calculated based on clock), re-ported some irq code from mame.
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dinkc64
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d2d8d4a04c
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4ad36b7ea0
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@ -1297,7 +1297,7 @@ INT2 P82 Rising Edge -
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*************************************************************************************************************/
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enum e_irq { INTSWI = 0, INTNMI, INTWD, INT0, INTT0, INTT1, INTT2, INTT3, INTT4, INT1, INTT5, INT2, INTRX, INTTX, INTMAX };
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enum e_irq { INTSWI = 0, INTNMI = 1, INTWD = 2, INT0 = 3, INTT0 = 4, INTT1 = 5, INTT2 = 6, INTT3 = 7, INTT4 = 8, INT1 = 9, INTT5 = 10, INT2 = 11, INTRX = 12, INTTX = 13, INTMAX = 14 };
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//DECLARE_ENUM_OPERATORS(e_irq)
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INLINE void leave_halt(t90_Regs *cpustate)
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@ -1327,44 +1327,22 @@ static void take_interrupt(t90_Regs *cpustate, e_irq irq)
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static void check_interrupts(t90_Regs *cpustate)
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{
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// e_irq irq;
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INT32 mask;
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int irq;
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int mask;
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if (!(F & IF))
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return;
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#define check_irq_state_mask(num) \
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mask = (1 << num); \
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if (num >= INT0) mask &= cpustate->irq_mask; \
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if ( cpustate->irq_state & mask) { \
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take_interrupt( cpustate, (num) ); \
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return; \
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for (irq = INTSWI; irq < INTMAX; irq++)
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{
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mask = (1 << irq);
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if(irq >= INT0) mask &= cpustate->irq_mask;
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if ( cpustate->irq_state & mask )
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{
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take_interrupt( cpustate, (e_irq)irq );
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return;
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}
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}
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check_irq_state_mask(INTSWI)
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check_irq_state_mask(INTNMI)
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check_irq_state_mask(INTWD)
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check_irq_state_mask(INT0)
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check_irq_state_mask(INTT0)
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check_irq_state_mask(INTT1)
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check_irq_state_mask(INTT2)
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check_irq_state_mask(INTT3)
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check_irq_state_mask(INTT4)
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check_irq_state_mask(INT1)
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check_irq_state_mask(INTT5)
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check_irq_state_mask(INT2)
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check_irq_state_mask(INTRX)
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check_irq_state_mask(INTTX)
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// check_irq_state_mask(INTMAX) // include this one?
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// for (irq = INT0; irq < INTMAX; irq++)
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// {
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// if ( cpustate->irq_state & cpustate->irq_mask & (1 << irq) )
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// {
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// take_interrupt( cpustate, irq );
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// return;
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// }
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// }
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}
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void tlcs90_set_irq_line(int irq, int state)
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@ -1419,14 +1397,16 @@ INT32 tlcs90Run(INT32 nCycles)
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unsigned a32;
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PAIR tmp;
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cpustate->icount -= cpustate->extra_cycles;
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cpustate->icount=nCycles;
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cpustate->nCycles = nCycles + cpustate->extra_cycles;
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if (cpustate->extra_cycles>0) {
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cpustate->icount+=cpustate->extra_cycles;
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}
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cpustate->extra_cycles = 0;
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cpustate->nCycles = nCycles;
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do
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{
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INT32 prev_cycles = cpustate->icount; // for timers
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cpustate->prvpc.d = cpustate->pc.d;
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// debugger_instruction_hook(device, cpustate->pc.d);
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@ -2053,11 +2033,9 @@ INT32 tlcs90Run(INT32 nCycles)
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for (INT32 i = 0; i < 5; i++) {
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if (cpustate->timer_enable[i]) {
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cpustate->timer_periods[i] -= (prev_cycles - cpustate->icount);
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if (cpustate->timer_periods[i] <= 0)
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{
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cpustate->timer_cb[i](i);
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cpustate->timer_periods[i] = cpustate->timer_periods_full[i]; // retrigger timer!
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}
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}
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@ -2065,22 +2043,10 @@ INT32 tlcs90Run(INT32 nCycles)
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} while( cpustate->icount > 0 && cpustate->run_end == 0 );
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// bprintf (0, _T("RunEnd: %d\n"), cpustate->run_end);
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cpustate->run_end = 0;
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cpustate->total_cycles += nCycles;
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cpustate->icount -= cpustate->extra_cycles;
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cpustate->extra_cycles = 0;
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cpustate->nCycles = 0;
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INT32 ret = nCycles - cpustate->icount;
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cpustate->total_cycles += ret;
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cpustate->icount = 0;
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return ret;
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return nCycles;
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}
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void tlcs90NewFrame()
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@ -2106,7 +2072,7 @@ INT32 tlcs90TotalCycles()
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// bprintf (0, _T("TotalCycles: %d\n"), cpustate->total_cycles + (cpustate->nCycles - cpustate->icount));
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return cpustate->total_cycles + (cpustate->nCycles - cpustate->icount);
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return cpustate->total_cycles;// + (cpustate->nCycles - cpustate->icount);
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}
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INT32 tlcs90Reset()
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@ -2535,6 +2501,7 @@ void t90_timer_callback(INT32 param)
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{
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case 0x02: // 8bit PPG
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case 0x03: // 8bit PWM
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//logerror("CPU Timer %d expired with unhandled mode %d\n", i, mode);
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// TODO: hmm...
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case 0x00: // 8bit
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cpustate->timer_value[i]++;
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@ -2565,13 +2532,11 @@ void t90_timer_callback(INT32 param)
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if ( (cpustate->internal_registers[ T90_TCLK - T90_IOBASE ] & (0x0C << (i * 2))) == 0 ) // T0/T1 match signal clocks T1/T3
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t90_timer_callback(i+1);
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break;
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case 0x01: // 16bit, only can happen for i=0,2
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cpustate->timer_value[i+1] = 0;
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tlcs90_set_irq_line(INTT0 + i+1, 1);
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break;
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}
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// regular handling
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cpustate->timer_value[i] = 0;
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tlcs90_set_irq_line(INTT0 + i, 1);
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@ -2778,7 +2743,7 @@ INT32 tlcs90_init(INT32 clock)
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memset(cpustate, 0, sizeof(t90_Regs));
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cpustate->timer_period = (1.000000000 / clock) * 8;
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cpustate->timer_period = 8; // changed to "8" -dink //(1.000000000 / clock) * 8;
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// Reset registers to their initial values
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