make way for new device
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dinkc64
parent
1cab4d9f89
commit
1111159c75
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@ -1,262 +0,0 @@
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/*
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* rarely used EEPROM code
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* (C) notaz, 2007-2009
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*
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* This work is licensed under the terms of MAME license.
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* See COPYING file in the top-level directory.
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*
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*/
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#include "burnint.h"
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#include "m68000_intf.h"
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struct i2c_eep {
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UINT8 eeprom_type; // eeprom type: 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words
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UINT8 eeprom_bit_cl; // bit number for cl
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UINT8 eeprom_bit_in; // bit number for in
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UINT8 eeprom_bit_out; // bit number for out
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UINT32 last_write;
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UINT16 eeprom_addr; // EEPROM address register
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UINT8 eeprom_cycle; // EEPROM cycle number
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UINT8 eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs
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UINT8 eeprom_status;
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UINT8 eeprom_wb[2]; // EEPROM latch/write buffer
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UINT8 changed;
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UINT8 *data; // pointer to EEPROM block
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};
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static i2c_eep eeprom;
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void EEPROM_init(UINT8 type, UINT8 cl, UINT8 i, UINT8 o, UINT8 *data)
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{
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memset(&eeprom, 0, sizeof(eeprom));
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eeprom.eeprom_type = type; // 0: 7bit (24C01), 2: 2 addr words (X24C02+), 3: 3 addr words
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eeprom.eeprom_bit_cl = cl;
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eeprom.eeprom_bit_in = i;
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eeprom.eeprom_bit_out= o;
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eeprom.data = data;
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eeprom.last_write = 0xffff0000;
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}
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void EEPROM_init(UINT8 *data)
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{
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EEPROM_init(0, 1, 0, 0, data);
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}
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void EEPROM_scan()
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{
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SCAN_VAR(eeprom.last_write);
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SCAN_VAR(eeprom.eeprom_addr);
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SCAN_VAR(eeprom.eeprom_cycle);
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SCAN_VAR(eeprom.eeprom_slave);
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SCAN_VAR(eeprom.eeprom_status);
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SCAN_VAR(eeprom.eeprom_wb);
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SCAN_VAR(eeprom.changed);
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// data block is scanned in megadrive.cpp..
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}
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// eeprom_status: LA.. s.la (L=pending SCL, A=pending SDA,
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// s=started, l=old SCL, a=old SDA)
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static void EEPROM_write_do(UINT32 d) // ???? ??la (l=SCL, a=SDA)
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{
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UINT32 sreg = eeprom.eeprom_status, saddr = eeprom.eeprom_addr;
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UINT32 scyc = eeprom.eeprom_cycle, ssa = eeprom.eeprom_slave;
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//elprintf(EL_EEPROM, "eeprom: scl/sda: %i/%i -> %i/%i, newtime=%i", (sreg&2)>>1, sreg&1, (d&2)>>1, d&1, SekTotalCycles() - eeprom.last_write);
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saddr &= 0x1fff;
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if(sreg & d & 2) {
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// SCL was and is still high..
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if((sreg & 1) && !(d&1)) {
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// ..and SDA went low, means it's a start command, so clear internal addr reg and clock counter
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//elprintf(EL_EEPROM, "eeprom: -start-");
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//saddr = 0;
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scyc = 0;
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sreg |= 8;
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} else if(!(sreg & 1) && (d&1)) {
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// SDA went high == stop command
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//elprintf(EL_EEPROM, "eeprom: -stop-");
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sreg &= ~8;
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}
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}
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else if((sreg & 8) && !(sreg & 2) && (d&2))
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{
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// we are started and SCL went high - next cycle
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scyc++; // pre-increment
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if(eeprom.eeprom_type) {
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// X24C02+
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if((ssa&1) && scyc == 18) {
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scyc = 9;
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saddr++; // next address in read mode
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/*if(eeprom.eeprom_type==2) saddr&=0xff; else*/ saddr&=0x1fff; // mask
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}
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else if(eeprom.eeprom_type == 2 && scyc == 27) scyc = 18;
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else if(scyc == 36) scyc = 27;
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} else {
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// X24C01
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if(scyc == 18) {
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scyc = 9; // wrap
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if(saddr&1) { saddr+=2; saddr&=0xff; } // next addr in read mode
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}
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}
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//elprintf(EL_EEPROM, "eeprom: scyc: %i", scyc);
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}
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else if((sreg & 8) && (sreg & 2) && !(d&2))
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{
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// we are started and SCL went low (falling edge)
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if(eeprom.eeprom_type) {
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// X24C02+
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if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles
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else if( (eeprom.eeprom_type == 3 && scyc > 27) || (eeprom.eeprom_type == 2 && scyc > 18) ) {
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if(!(ssa&1)) {
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// data write
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UINT8 *pm=eeprom.data+saddr;
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*pm <<= 1; *pm |= d&1;
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if(scyc == 26 || scyc == 35) {
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saddr=(saddr&~0xf)|((saddr+1)&0xf); // only 4 (?) lowest bits are incremented
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//elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr, *pm);
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}
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eeprom.changed = 1;
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}
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} else if(scyc > 9) {
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if(!(ssa&1)) {
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// we latch another addr bit
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saddr<<=1;
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if(eeprom.eeprom_type == 2) saddr&=0xff; else saddr&=0x1fff; // mask
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saddr|=d&1;
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if(scyc==17||scyc==26) {
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//elprintf(EL_EEPROM, "eeprom: addr reg done: %x", saddr);
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if(scyc==17&&eeprom.eeprom_type==2) { saddr&=0xff; saddr|=(ssa<<7)&0x700; } // add device bits too
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}
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}
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} else {
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// slave address
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ssa<<=1; ssa|=d&1;
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//if(scyc==8) elprintf(EL_EEPROM, "eeprom: slave done: %x", ssa);
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}
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} else {
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// X24C01
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if(scyc == 9); // ACK cycle, do nothing
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else if(scyc > 9) {
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if(!(saddr&1)) {
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// data write
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UINT8 *pm=eeprom.data+(saddr>>1);
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*pm <<= 1; *pm |= d&1;
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if(scyc == 17) {
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saddr=(saddr&0xf9)|((saddr+2)&6); // only 2 lowest bits are incremented
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//elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr>>1, *pm);
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}
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eeprom.changed = 1;
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}
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} else {
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// we latch another addr bit
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saddr<<=1; saddr|=d&1; saddr&=0xff;
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//if(scyc==8) elprintf(EL_EEPROM, "eeprom: addr done: %x", saddr>>1);
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}
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}
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}
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sreg &= ~3; sreg |= d&3; // remember SCL and SDA
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eeprom.eeprom_status = (UINT8) sreg;
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eeprom.eeprom_cycle = (UINT8) scyc;
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eeprom.eeprom_slave = (UINT8) ssa;
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eeprom.eeprom_addr = (UINT16)saddr;
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}
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static void EEPROM_upd_pending(UINT32 d)
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{
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UINT32 d1, sreg = eeprom.eeprom_status;
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sreg &= ~0xc0;
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// SCL
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d1 = (d >> eeprom.eeprom_bit_cl) & 1;
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sreg |= d1 << 7;
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// SDA in
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d1 = (d >> eeprom.eeprom_bit_in) & 1;
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sreg |= d1 << 6;
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eeprom.eeprom_status = (UINT8) sreg;
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}
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void EEPROM_write16(UINT32 d)
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{
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// this diff must be at most 16 for NBA Jam to work
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if (SekTotalCycles() - eeprom.last_write < 16) {
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// just update pending state
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//elprintf(EL_EEPROM, "eeprom: skip because cycles=%i", SekTotalCycles() - eeprom.last_write);
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EEPROM_upd_pending(d);
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} else {
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int srs = eeprom.eeprom_status;
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EEPROM_write_do(srs >> 6); // execute pending
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EEPROM_upd_pending(d);
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if ((srs ^ eeprom.eeprom_status) & 0xc0) // update time only if SDA/SCL changed
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eeprom.last_write = SekTotalCycles();
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}
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}
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void EEPROM_write8(UINT32 a, UINT8 d)
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{
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UINT8 *wb = eeprom.eeprom_wb;
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wb[a & 1] = d;
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EEPROM_write16((wb[0] << 8) | wb[1]);
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}
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UINT32 EEPROM_read()
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{
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UINT32 shift, d;
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UINT32 sreg, saddr, scyc, ssa, interval;
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// flush last pending write
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EEPROM_write_do(eeprom.eeprom_status>>6);
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sreg = eeprom.eeprom_status; saddr = eeprom.eeprom_addr&0x1fff; scyc = eeprom.eeprom_cycle; ssa = eeprom.eeprom_slave;
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interval = SekTotalCycles() - eeprom.last_write;
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d = (sreg>>6)&1; // use SDA as "open bus"
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// NBA Jam is nasty enough to read <before> raising the SCL and starting the new cycle.
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// this is probably valid because data changes occur while SCL is low and data can be read
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// before it's actual cycle begins.
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if (!(sreg&0x80) && interval >= 24) {
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//elprintf(EL_EEPROM, "eeprom: early read, cycles=%i", interval);
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scyc++;
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}
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if (!(sreg & 8)); // not started, use open bus
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else if (scyc == 9 || scyc == 18 || scyc == 27) {
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//elprintf(EL_EEPROM, "eeprom: r ack");
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d = 0;
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} else if (scyc > 9 && scyc < 18) {
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// started and first command word received
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shift = 17-scyc;
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if (eeprom.eeprom_type) {
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// X24C02+
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if (ssa&1) {
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//elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg);
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//if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", eeprom.data[saddr]);
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d = (eeprom.data[saddr]>>shift)&1;
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}
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} else {
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// X24C01
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if (saddr&1) {
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//elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr>>1, scyc, sreg);
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//if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", eeprom.data[saddr>>1]);
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d = (eeprom.data[saddr>>1]>>shift)&1;
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}
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}
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}
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return (d << eeprom.eeprom_bit_out);
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}
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UINT32 EEPROM_read8(UINT32 a)
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{
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UINT32 d = EEPROM_read();
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if (!(a & 1))
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d >>= 8;
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return d;
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}
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@ -1,7 +0,0 @@
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void EEPROM_init(UINT8 *data);
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void EEPROM_init(UINT8 type, UINT8 cl, UINT8 i, UINT8 o, UINT8 *data);
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void EEPROM_write16(UINT32 d);
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void EEPROM_write8(UINT32 a, UINT8 d);
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UINT32 EEPROM_read();
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UINT32 EEPROM_read8(UINT32 a);
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void EEPROM_scan();
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