Bus: Calculation of memory timings for external devices
This commit is contained in:
Connor McLaughlin
parent
0b46a8cfc4
commit
fd1c4f1457
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@ -51,14 +51,15 @@ void Bus::Reset()
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m_ram.fill(static_cast<u8>(0));
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m_MEMCTRL.exp1_base = 0x1F000000;
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m_MEMCTRL.exp2_base = 0x1F802000;
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m_MEMCTRL.exp1_delay_size = 0x0013243F;
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m_MEMCTRL.exp3_delay_size = 0x00003022;
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m_MEMCTRL.bios_delay_size = 0x0013243F;
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m_MEMCTRL.spu_delay_size = 0x200931E1;
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m_MEMCTRL.cdrom_delay_size = 0x00020843;
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m_MEMCTRL.exp2_delay_size = 0x00070777;
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m_MEMCTRL.common_delay_size = 0x00031125;
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m_MEMCTRL.exp1_delay_size.bits = 0x0013243F;
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m_MEMCTRL.exp3_delay_size.bits = 0x00003022;
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m_MEMCTRL.bios_delay_size.bits = 0x0013243F;
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m_MEMCTRL.spu_delay_size.bits = 0x200931E1;
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m_MEMCTRL.cdrom_delay_size.bits = 0x00020843;
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m_MEMCTRL.exp2_delay_size.bits = 0x00070777;
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m_MEMCTRL.common_delay.bits = 0x00031125;
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m_ram_size_reg = UINT32_C(0x00000B88);
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RecalculateMemoryTimings();
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}
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bool Bus::DoState(StateWrapper& sw)
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@ -167,6 +168,61 @@ bool Bus::LoadBIOS()
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return true;
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}
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std::tuple<TickCount, TickCount, TickCount> Bus::CalculateMemoryTiming(MEMDELAY mem_delay, COMDELAY common_delay)
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{
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// from nocash spec
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s32 first = 0, seq = 0, min = 0;
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if (mem_delay.use_com0_time)
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{
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first += s32(common_delay.com0) - 1;
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seq += s32(common_delay.com0) - 1;
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}
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if (mem_delay.use_com2_time)
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{
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first += s32(common_delay.com2);
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seq += s32(common_delay.com2);
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}
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if (mem_delay.use_com3_time)
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{
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min = s32(common_delay.com3);
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}
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if (first < 6)
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first++;
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first = first + s32(mem_delay.access_time) + 2;
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seq = seq + s32(mem_delay.access_time) + 2;
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if (first < (min + 6))
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first = min + 6;
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if (seq < (min + 2))
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seq = min + 2;
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const TickCount byte_access_time = first;
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const TickCount halfword_access_time = mem_delay.data_bus_16bit ? first : (first + seq);
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const TickCount word_access_time = mem_delay.data_bus_16bit ? (first + seq) : (first + seq + seq + seq);
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return std::tie(byte_access_time, halfword_access_time, word_access_time);
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}
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void Bus::RecalculateMemoryTimings()
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{
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std::tie(m_bios_access_time[0], m_bios_access_time[1], m_bios_access_time[2]) =
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CalculateMemoryTiming(m_MEMCTRL.bios_delay_size, m_MEMCTRL.common_delay);
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std::tie(m_cdrom_access_time[0], m_cdrom_access_time[1], m_cdrom_access_time[2]) =
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CalculateMemoryTiming(m_MEMCTRL.cdrom_delay_size, m_MEMCTRL.common_delay);
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std::tie(m_spu_access_time[0], m_spu_access_time[1], m_spu_access_time[2]) =
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CalculateMemoryTiming(m_MEMCTRL.spu_delay_size, m_MEMCTRL.common_delay);
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Log_DevPrintf("BIOS Memory Timing: %u bit bus, byte=%d, halfword=%d, word=%d",
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m_MEMCTRL.bios_delay_size.data_bus_16bit ? 16 : 8, m_bios_access_time[0], m_bios_access_time[1],
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m_bios_access_time[2]);
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Log_DevPrintf("CDROM Memory Timing: %u bit bus, byte=%d, halfword=%d, word=%d",
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m_MEMCTRL.cdrom_delay_size.data_bus_16bit ? 16 : 8, m_cdrom_access_time[0], m_cdrom_access_time[1],
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m_cdrom_access_time[2]);
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Log_DevPrintf("SPU Memory Timing: %u bit bus, byte=%d, halfword=%d, word=%d",
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m_MEMCTRL.spu_delay_size.data_bus_16bit ? 16 : 8, m_spu_access_time[0], m_spu_access_time[1],
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m_spu_access_time[2]);
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}
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bool Bus::DoInvalidAccess(MemoryAccessType type, MemoryAccessSize size, PhysicalMemoryAddress address, u32& value)
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{
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SmallString str;
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@ -292,7 +348,16 @@ bool Bus::DoReadMemoryControl(MemoryAccessSize size, u32 offset, u32& value)
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bool Bus::DoWriteMemoryControl(MemoryAccessSize size, u32 offset, u32 value)
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{
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FixupUnalignedWordAccessW32(offset, value);
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m_MEMCTRL.regs[offset / 4] = value;
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const u32 index = offset / 4;
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const u32 write_mask = (index == 8) ? COMDELAY::WRITE_MASK : MEMDELAY::WRITE_MASK;
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const u32 new_value = (m_MEMCTRL.regs[index] & ~write_mask) | (value & write_mask);
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if (m_MEMCTRL.regs[index] != new_value)
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{
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m_MEMCTRL.regs[index] = new_value;
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RecalculateMemoryTimings();
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}
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return true;
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}
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@ -455,10 +520,10 @@ bool Bus::DoReadDMA(MemoryAccessSize size, u32 offset, u32& value)
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{
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case MemoryAccessSize::Byte:
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case MemoryAccessSize::HalfWord:
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{
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if ((offset & u32(0xF0)) >= 7 || (offset & u32(0x0F)) != 0x4)
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FixupUnalignedWordAccessW32(offset, value);
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}
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{
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if ((offset & u32(0xF0)) >= 7 || (offset & u32(0x0F)) != 0x4)
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FixupUnalignedWordAccessW32(offset, value);
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}
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default:
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break;
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@ -1,6 +1,7 @@
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#pragma once
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#include "YBaseLib/String.h"
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#include "common/bitfield.h"
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#include "types.h"
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#include <array>
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@ -95,6 +96,34 @@ private:
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MEMCTRL_REG_COUNT = 9
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};
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union MEMDELAY
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{
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u32 bits;
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BitField<u32, u8, 4, 4> access_time; // cycles
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BitField<u32, bool, 8, 1> use_com0_time;
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BitField<u32, bool, 9, 1> use_com1_time;
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BitField<u32, bool, 10, 1> use_com2_time;
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BitField<u32, bool, 11, 1> use_com3_time;
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BitField<u32, bool, 12, 1> data_bus_16bit;
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BitField<u32, u8, 16, 5> memory_window_size;
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static constexpr u32 WRITE_MASK = 0b10101111'00011111'11111111'11111111;
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};
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union COMDELAY
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{
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u32 bits;
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BitField<u32, u8, 0, 4> com0;
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BitField<u32, u8, 4, 4> com1;
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BitField<u32, u8, 8, 4> com2;
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BitField<u32, u8, 12, 4> com3;
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BitField<u32, u8, 16, 2> comunk;
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static constexpr u32 WRITE_MASK = 0b00000000'00000011'11111111'11111111;
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};
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union MEMCTRL
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{
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u32 regs[MEMCTRL_REG_COUNT];
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@ -103,18 +132,21 @@ private:
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{
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u32 exp1_base;
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u32 exp2_base;
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u32 exp1_delay_size;
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u32 exp3_delay_size;
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u32 bios_delay_size;
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u32 spu_delay_size;
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u32 cdrom_delay_size;
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u32 exp2_delay_size;
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u32 common_delay_size;
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MEMDELAY exp1_delay_size;
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MEMDELAY exp3_delay_size;
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MEMDELAY bios_delay_size;
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MEMDELAY spu_delay_size;
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MEMDELAY cdrom_delay_size;
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MEMDELAY exp2_delay_size;
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COMDELAY common_delay;
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};
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};
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bool LoadBIOS();
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static std::tuple<TickCount, TickCount, TickCount> CalculateMemoryTiming(MEMDELAY mem_delay, COMDELAY common_delay);
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void RecalculateMemoryTimings();
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template<MemoryAccessType type, MemoryAccessSize size>
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bool DoRAMAccess(u32 offset, u32& value);
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@ -172,6 +204,10 @@ private:
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SPU* m_spu = nullptr;
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MDEC* m_mdec = nullptr;
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std::array<TickCount, 3> m_bios_access_time = {};
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std::array<TickCount, 3> m_cdrom_access_time = {};
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std::array<TickCount, 3> m_spu_access_time = {};
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std::array<u8, 2097152> m_ram{}; // 2MB RAM
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std::array<u8, 524288> m_bios{}; // 512K BIOS ROM
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std::vector<u8> m_exp1_rom;
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