GTE: Implement DPCT
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fc74d08641
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e8cd174732
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@ -294,6 +294,10 @@ void Core::ExecuteInstruction(Instruction inst)
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Execute_SQR(inst);
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Execute_SQR(inst);
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break;
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break;
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case 0x2A:
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Execute_DPCT(inst);
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break;
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case 0x2D:
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case 0x2D:
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Execute_AVSZ3(inst);
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Execute_AVSZ3(inst);
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break;
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break;
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@ -383,9 +387,10 @@ void Core::PushSZ(s32 value)
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void Core::PushRGB(u8 r, u8 g, u8 b, u8 c)
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void Core::PushRGB(u8 r, u8 g, u8 b, u8 c)
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{
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{
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m_regs.RGB0 = m_regs.RGB1;
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m_regs.dr32[20] = m_regs.dr32[21]; // RGB0 <- RGB1
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m_regs.RGB1 = m_regs.RGB2;
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m_regs.dr32[21] = m_regs.dr32[22]; // RGB1 <- RGB2
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m_regs.RGB2 = ZeroExtend32(r) | (ZeroExtend32(g) << 8) | (ZeroExtend32(b) << 16) | (ZeroExtend32(c) << 24);
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m_regs.dr32[22] =
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ZeroExtend32(r) | (ZeroExtend32(g) << 8) | (ZeroExtend32(b) << 16) | (ZeroExtend32(c) << 24); // RGB2 <- Value
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}
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}
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void Core::RTPS(const s16 V[3], bool sf, bool lm, bool last)
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void Core::RTPS(const s16 V[3], bool sf, bool lm, bool last)
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@ -737,18 +742,15 @@ void Core::Execute_MVMVA(Instruction inst)
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m_regs.FLAG.UpdateError();
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m_regs.FLAG.UpdateError();
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}
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}
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void Core::Execute_DPCS(Instruction inst)
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void Core::DPCS(const u8 color[3], bool sf, bool lm)
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{
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{
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m_regs.FLAG.Clear();
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const u8 shift = sf ? 12 : 0;
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const u8 shift = inst.GetShift();
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const bool lm = inst.lm;
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// In: [IR1,IR2,IR3]=Vector, FC=Far Color, IR0=Interpolation value, CODE=MSB of RGBC
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// In: [IR1,IR2,IR3]=Vector, FC=Far Color, IR0=Interpolation value, CODE=MSB of RGBC
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// [MAC1,MAC2,MAC3] = [R,G,B] SHL 16 ;<--- for DPCS/DPCT
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// [MAC1,MAC2,MAC3] = [R,G,B] SHL 16 ;<--- for DPCS/DPCT
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TruncateAndSetMAC<1>((s64(ZeroExtend64(m_regs.RGBC[0])) << 16), 0);
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TruncateAndSetMAC<1>((s64(ZeroExtend64(color[0])) << 16), 0);
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TruncateAndSetMAC<2>((s64(ZeroExtend64(m_regs.RGBC[1])) << 16), 0);
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TruncateAndSetMAC<2>((s64(ZeroExtend64(color[1])) << 16), 0);
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TruncateAndSetMAC<3>((s64(ZeroExtend64(m_regs.RGBC[2])) << 16), 0);
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TruncateAndSetMAC<3>((s64(ZeroExtend64(color[2])) << 16), 0);
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// [MAC1,MAC2,MAC3] = MAC+(FC-MAC)*IR0
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// [MAC1,MAC2,MAC3] = MAC+(FC-MAC)*IR0
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// [IR1,IR2,IR3] = (([RFC,GFC,BFC] SHL 12) - [MAC1,MAC2,MAC3]) SAR (sf*12)
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// [IR1,IR2,IR3] = (([RFC,GFC,BFC] SHL 12) - [MAC1,MAC2,MAC3]) SAR (sf*12)
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@ -772,4 +774,27 @@ void Core::Execute_DPCS(Instruction inst)
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m_regs.FLAG.UpdateError();
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m_regs.FLAG.UpdateError();
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}
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}
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void Core::Execute_DPCS(Instruction inst)
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{
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m_regs.FLAG.Clear();
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DPCS(m_regs.RGBC, inst.sf, inst.lm);
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m_regs.FLAG.UpdateError();
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}
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void Core::Execute_DPCT(Instruction inst)
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{
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m_regs.FLAG.Clear();
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const bool sf = inst.sf;
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const bool lm = inst.lm;
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DPCS(m_regs.RGB0, sf, lm);
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DPCS(m_regs.RGB0, sf, lm);
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DPCS(m_regs.RGB0, sf, lm);
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m_regs.FLAG.UpdateError();
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}
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} // namespace GTE
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} // namespace GTE
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@ -62,6 +62,7 @@ private:
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void RTPS(const s16 V[3], bool sf, bool lm, bool last);
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void RTPS(const s16 V[3], bool sf, bool lm, bool last);
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void NCCS(const s16 V[3], bool sf, bool lm);
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void NCCS(const s16 V[3], bool sf, bool lm);
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void NCDS(const s16 V[3], bool sf, bool lm);
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void NCDS(const s16 V[3], bool sf, bool lm);
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void DPCS(const u8 color[3], bool sf, bool lm);
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void Execute_RTPS(Instruction inst);
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void Execute_RTPS(Instruction inst);
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void Execute_RTPT(Instruction inst);
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void Execute_RTPT(Instruction inst);
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@ -75,6 +76,7 @@ private:
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void Execute_NCDT(Instruction inst);
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void Execute_NCDT(Instruction inst);
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void Execute_MVMVA(Instruction inst);
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void Execute_MVMVA(Instruction inst);
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void Execute_DPCS(Instruction inst);
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void Execute_DPCS(Instruction inst);
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void Execute_DPCT(Instruction inst);
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Regs m_regs = {};
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Regs m_regs = {};
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};
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};
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@ -86,9 +86,9 @@ union Regs
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u16 pad15; // 18
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u16 pad15; // 18
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u16 SZ3; // 19
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u16 SZ3; // 19
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u16 pad16; // 19
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u16 pad16; // 19
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u32 RGB0; // 20
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u8 RGB0[4]; // 20
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u32 RGB1; // 21
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u8 RGB1[4]; // 21
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u32 RGB2; // 22
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u8 RGB2[4]; // 22
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u32 RES1; // 23
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u32 RES1; // 23
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s32 MAC0; // 24
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s32 MAC0; // 24
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s32 MAC1; // 25
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s32 MAC1; // 25
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