parent
20de40a597
commit
e10ff550d5
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@ -1602,11 +1602,13 @@ void CPU::NewRec::Compiler::CompileLoadStoreTemplate(void (Compiler::*func)(Comp
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// constant address?
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std::optional<VirtualMemoryAddress> addr;
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std::optional<VirtualMemoryAddress> spec_addr;
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bool use_fastmem = CodeCache::IsUsingFastmem() && !g_settings.cpu_recompiler_memory_exceptions &&
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!SpecIsCacheIsolated() && !CodeCache::HasPreviouslyFaultedOnPC(m_current_instruction_pc);
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if (HasConstantReg(rs))
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{
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addr = GetConstantRegU32(rs) + inst->i.imm_sext32();
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spec_addr = addr;
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cf.const_s = true;
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if (!Bus::CanUseFastmemForAddress(addr.value()))
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@ -1617,7 +1619,7 @@ void CPU::NewRec::Compiler::CompileLoadStoreTemplate(void (Compiler::*func)(Comp
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}
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else
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{
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const std::optional<VirtualMemoryAddress> spec_addr = SpecExec_LoadStoreAddr();
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spec_addr = SpecExec_LoadStoreAddr();
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if (use_fastmem && spec_addr.has_value() && !Bus::CanUseFastmemForAddress(spec_addr.value()))
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{
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Log_DebugFmt("Not using fastmem for speculative {:08X}", spec_addr.value());
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@ -1671,6 +1673,22 @@ void CPU::NewRec::Compiler::CompileLoadStoreTemplate(void (Compiler::*func)(Comp
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}
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(this->*func)(cf, size, sign, use_fastmem, addr);
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if (store && !m_block_ended && !m_current_instruction_branch_delay_slot && spec_addr.has_value() &&
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GetSegmentForAddress(spec_addr.value()) != Segment::KSEG2)
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{
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// Get rid of physical aliases.
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const u32 phys_spec_addr = VirtualAddressToPhysical(spec_addr.value());
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if (phys_spec_addr >= VirtualAddressToPhysical(m_block->pc) &&
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phys_spec_addr < VirtualAddressToPhysical(m_block->pc + (m_block->size * sizeof(Instruction))))
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{
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Log_WarningFmt("Instruction {:08X} speculatively writes to {:08X} inside block {:08X}-{:08X}. Truncating block.",
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m_current_instruction_pc, phys_spec_addr, m_block->pc,
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m_block->pc + (m_block->size * sizeof(Instruction)));
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m_block->size = ((m_current_instruction_pc - m_block->pc) / sizeof(Instruction)) + 1;
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iinfo->is_last_instruction = true;
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}
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}
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}
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void CPU::NewRec::Compiler::FlushForLoadStore(const std::optional<VirtualMemoryAddress>& address, bool store,
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@ -402,7 +402,7 @@ protected:
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TickCount m_gte_done_cycle = 0;
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const Instruction* inst = nullptr;
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const CodeCache::InstructionInfo* iinfo = nullptr;
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CodeCache::InstructionInfo* iinfo = nullptr;
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u32 m_current_instruction_pc = 0;
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bool m_current_instruction_branch_delay_slot = false;
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bool m_branch_delay_slot_swapped = false;
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@ -1983,6 +1983,10 @@ void CPU::NewRec::AArch32Compiler::TestInterrupts(const vixl::aarch32::Register&
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SwitchToFarCode(true, ne);
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BackupHostState();
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// Update load delay, this normally happens at the end of an instruction, but we're finishing it early.
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UpdateLoadDelay();
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Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
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// Can't use EndBlockWithException() here, because it'll use the wrong PC.
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@ -1957,6 +1957,10 @@ void CPU::NewRec::AArch64Compiler::TestInterrupts(const vixl::aarch64::WRegister
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SwitchToFarCode(true, ne);
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BackupHostState();
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// Update load delay, this normally happens at the end of an instruction, but we're finishing it early.
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UpdateLoadDelay();
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Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
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// Can't use EndBlockWithException() here, because it'll use the wrong PC.
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@ -2212,7 +2212,12 @@ void CPU::NewRec::RISCV64Compiler::TestInterrupts(const biscuit::GPR& sr)
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rvAsm->SRLIW(sr, sr, 8);
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rvAsm->ANDI(sr, sr, 0xFF);
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SwitchToFarCode(true, &Assembler::BEQ, sr, zero);
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BackupHostState();
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// Update load delay, this normally happens at the end of an instruction, but we're finishing it early.
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UpdateLoadDelay();
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Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
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// Can't use EndBlockWithException() here, because it'll use the wrong PC.
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@ -1935,6 +1935,10 @@ void CPU::NewRec::X64Compiler::TestInterrupts(const Xbyak::Reg32& sr)
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SwitchToFarCode(true, &CodeGenerator::jnz);
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BackupHostState();
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// Update load delay, this normally happens at the end of an instruction, but we're finishing it early.
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UpdateLoadDelay();
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Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
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// Can't use EndBlockWithException() here, because it'll use the wrong PC.
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