CPU/Recompiler: Fix build error
Build currently fails on a GCC 13.2.x with: /var/tmp/portage/games-emulation/duckstation-9999/work/duckstation/src/core/cpu_recompiler_code_generator.cpp: In member function ‘bool CPU::Recompiler::CodeGenerator::Compile_Bitwise(CPU::Instruction, const CPU::CodeCache::InstructionInfo&)’: /var/tmp/portage/games-emulation/duckstation-9999/work/duckstation/src/core/cpu_recompiler_code_generator.cpp:1330:81: error: operands to ‘?:’ have different types ‘BitField<unsigned int, CPU::Reg, 16, 5>’ and ‘BitField<unsigned int, CPU::Reg, 21, 5>’ 1330 | PGXP::PackMoveArgs(dest, lhs.HasConstantValue(0) ? instruction.r.rt : instruction.r.rs)), | ~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ /var/tmp/portage/games-emulation/duckstation-9999/work/duckstation/src/core/cpu_recompiler_code_generator.cpp:1362:81: error: operands to ‘?:’ have different types ‘BitField<unsigned int, CPU::Reg, 16, 5>’ and ‘BitField<unsigned int, CPU::Reg, 21, 5>’ 1362 | PGXP::PackMoveArgs(dest, lhs.HasConstantValue(0) ? instruction.r.rt : instruction.r.rs)), | ~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@ -1325,9 +1325,11 @@ bool CodeGenerator::Compile_Bitwise(Instruction instruction, const CodeCache::In
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((lhs.HasConstantValue(0) && instruction.r.rt != Reg::zero && dest != instruction.r.rs) ||
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((lhs.HasConstantValue(0) && instruction.r.rt != Reg::zero && dest != instruction.r.rs) ||
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(rhs.HasConstantValue(0) && instruction.r.rs != Reg::zero && dest != instruction.r.rt)))
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(rhs.HasConstantValue(0) && instruction.r.rs != Reg::zero && dest != instruction.r.rt)))
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{
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{
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const auto rs = lhs.HasConstantValue(0) ? static_cast<CPU::Reg>(instruction.r.rt) : static_cast<CPU::Reg>(instruction.r.rs);
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EmitFunctionCall(nullptr, &PGXP::CPU_MOVE_Packed,
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EmitFunctionCall(nullptr, &PGXP::CPU_MOVE_Packed,
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Value::FromConstantU32(
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Value::FromConstantU32(
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PGXP::PackMoveArgs(dest, lhs.HasConstantValue(0) ? instruction.r.rt : instruction.r.rs)),
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PGXP::PackMoveArgs(dest, rs)),
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lhs.HasConstantValue(0) ? rhs : lhs);
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lhs.HasConstantValue(0) ? rhs : lhs);
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}
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}
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}
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}
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@ -1357,9 +1359,11 @@ bool CodeGenerator::Compile_Bitwise(Instruction instruction, const CodeCache::In
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((lhs.HasConstantValue(0) && instruction.r.rt != Reg::zero && dest != instruction.r.rs) ||
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((lhs.HasConstantValue(0) && instruction.r.rt != Reg::zero && dest != instruction.r.rs) ||
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(rhs.HasConstantValue(0) && instruction.r.rs != Reg::zero && dest != instruction.r.rt)))
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(rhs.HasConstantValue(0) && instruction.r.rs != Reg::zero && dest != instruction.r.rt)))
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{
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{
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const auto rs = lhs.HasConstantValue(0) ? static_cast<CPU::Reg>(instruction.r.rt) : static_cast<CPU::Reg>(instruction.r.rs);
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EmitFunctionCall(nullptr, &PGXP::CPU_MOVE_Packed,
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EmitFunctionCall(nullptr, &PGXP::CPU_MOVE_Packed,
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Value::FromConstantU32(
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Value::FromConstantU32(
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PGXP::PackMoveArgs(dest, lhs.HasConstantValue(0) ? instruction.r.rt : instruction.r.rs)),
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PGXP::PackMoveArgs(dest, rs)),
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lhs.HasConstantValue(0) ? rhs : lhs);
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lhs.HasConstantValue(0) ? rhs : lhs);
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}
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}
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}
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}
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