GTE: More cleanups
This commit is contained in:
Connor McLaughlin
parent
f704d8fc63
commit
d885abc528
102
src/pse/gte.cpp
102
src/pse/gte.cpp
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@ -316,44 +316,6 @@ void Core::ExecuteInstruction(Instruction inst)
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}
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}
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void Core::SetMAC(u32 index, s64 value)
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{
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if (value < INT64_C(-2147483648))
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m_regs.FLAG.SetMACUnderflow(index);
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else if (value > INT64_C(2147483647))
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m_regs.FLAG.SetMACOverflow(index);
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m_regs.dr32[24 + index] = Truncate32(static_cast<u64>(value));
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}
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void Core::SetIR(u32 index, s32 value, bool lm)
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{
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if (lm && value < 0)
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{
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m_regs.FLAG.SetIRSaturated(index);
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m_regs.dr32[8 + index] = 0;
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return;
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}
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// saturate to -32768..32767
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if (!lm && value < -32768)
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{
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m_regs.FLAG.SetIRSaturated(index);
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m_regs.dr32[8 + index] = static_cast<u32>(-1);
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return;
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}
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if (value > 32767)
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{
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m_regs.FLAG.SetIRSaturated(index);
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m_regs.dr32[8 + index] = UINT32_C(0x7FFF);
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return;
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}
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// store the sign extension in the padding bits
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m_regs.dr32[8 + index] = value;
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}
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void Core::SetOTZ(s32 value)
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{
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if (value < 0)
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@ -455,9 +417,9 @@ void Core::RTPS(const s16 V[3], bool sf, bool lm)
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// MAC0=(((H*20000h/SZ3)+1)/2)*IR1+OFX, SX2=MAC0/10000h ;ScrX FIFO -400h..+3FFh
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// MAC0=(((H*20000h/SZ3)+1)/2)*IR2+OFY, SY2=MAC0/10000h ;ScrY FIFO -400h..+3FFh
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// MAC0=(((H*20000h/SZ3)+1)/2)*DQA+DQB, IR0=MAC0/1000h ;Depth cueing 0..+1000h
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const s32 Sx = TruncateAndSetMAC<0>(s64(result) * s64(m_regs.IR1) + s64(m_regs.OFX), 16);
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const s32 Sy = TruncateAndSetMAC<0>(s64(result) * s64(m_regs.IR2) + s64(m_regs.OFY), 16);
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const s32 Sz = TruncateAndSetMAC<0>(s64(result) * s64(m_regs.DQA) + s64(m_regs.DQB), 12);
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const s32 Sx = s32(TruncateAndSetMAC<0>(s64(result) * s64(m_regs.IR1) + s64(m_regs.OFX), 16));
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const s32 Sy = s32(TruncateAndSetMAC<0>(s64(result) * s64(m_regs.IR2) + s64(m_regs.OFY), 16));
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const s32 Sz = s32(TruncateAndSetMAC<0>(s64(result) * s64(m_regs.DQA) + s64(m_regs.DQB), 12));
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PushSXY(Sx, Sy);
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TruncateAndSetIR<0>(Sz, true);
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}
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@ -486,11 +448,10 @@ void Core::Execute_NCLIP(Instruction inst)
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// MAC0 = SX0*SY1 + SX1*SY2 + SX2*SY0 - SX0*SY2 - SX1*SY0 - SX2*SY1
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m_regs.FLAG.Clear();
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const s64 MAC0x = s64(m_regs.SXY0[0]) * s64(m_regs.SXY1[1]) + s64(m_regs.SXY1[0]) * s64(m_regs.SXY2[1]) +
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TruncateAndSetMAC<0>(s64(m_regs.SXY0[0]) * s64(m_regs.SXY1[1]) + s64(m_regs.SXY1[0]) * s64(m_regs.SXY2[1]) +
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s64(m_regs.SXY2[0]) * s64(m_regs.SXY0[1]) - s64(m_regs.SXY0[0]) * s64(m_regs.SXY2[1]) -
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s64(m_regs.SXY1[0]) * s64(m_regs.SXY0[1]) - s64(m_regs.SXY2[0]) * s64(m_regs.SXY1[1]);
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SetMAC(0, MAC0x);
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s64(m_regs.SXY1[0]) * s64(m_regs.SXY0[1]) - s64(m_regs.SXY2[0]) * s64(m_regs.SXY1[1]),
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0);
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m_regs.FLAG.UpdateError();
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}
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@ -499,15 +460,16 @@ void Core::Execute_SQR(Instruction inst)
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{
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m_regs.FLAG.Clear();
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const u8 shift = inst.sf ? 12 : 0;
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SetMAC(1, (s32(m_regs.IR1) * s32(m_regs.IR1)) >> shift);
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SetMAC(2, (s32(m_regs.IR2) * s32(m_regs.IR2)) >> shift);
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SetMAC(3, (s32(m_regs.IR3) * s32(m_regs.IR3)) >> shift);
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// 32-bit multiply for speed - 16x16 isn't >32bit, and we know it won't overflow/underflow.
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const u8 shift = inst.GetShift();
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m_regs.MAC1 = (s32(m_regs.IR1) * s32(m_regs.IR1)) >> shift;
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m_regs.MAC2 = (s32(m_regs.IR2) * s32(m_regs.IR2)) >> shift;
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m_regs.MAC3 = (s32(m_regs.IR3) * s32(m_regs.IR3)) >> shift;
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const bool lm = inst.lm;
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SetIR(1, m_regs.MAC1, lm);
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SetIR(2, m_regs.MAC2, lm);
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SetIR(3, m_regs.MAC3, lm);
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TruncateAndSetIR<1>(m_regs.MAC1, lm);
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TruncateAndSetIR<2>(m_regs.MAC2, lm);
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TruncateAndSetIR<3>(m_regs.MAC3, lm);
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m_regs.FLAG.UpdateError();
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}
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@ -516,10 +478,10 @@ void Core::Execute_AVSZ3(Instruction inst)
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{
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m_regs.FLAG.Clear();
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const s64 MAC0 = static_cast<s64>(m_regs.ZSF3) *
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static_cast<s32>(ZeroExtend32(m_regs.SZ1) + ZeroExtend32(m_regs.SZ2) + ZeroExtend32(m_regs.SZ3));
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SetMAC(0, MAC0);
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SetOTZ(static_cast<s32>(MAC0 / 0x1000));
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const s64 result =
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TruncateAndSetMAC<0>(s64(m_regs.ZSF3) * s32(u32(m_regs.SZ1) + u32(m_regs.SZ2) + u32(m_regs.SZ3)), 0);
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TruncateAndSetMAC<0>(result, 0);
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SetOTZ(s32(result >> 12));
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m_regs.FLAG.UpdateError();
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}
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@ -528,30 +490,19 @@ void Core::Execute_AVSZ4(Instruction inst)
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{
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m_regs.FLAG.Clear();
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const s64 MAC0 =
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static_cast<s64>(m_regs.ZSF4) * static_cast<s32>(ZeroExtend32(m_regs.SZ0) + ZeroExtend32(m_regs.SZ1) +
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ZeroExtend32(m_regs.SZ2) + ZeroExtend32(m_regs.SZ3));
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SetMAC(0, MAC0);
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SetOTZ(static_cast<s32>(MAC0 / 0x1000));
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const s64 result = TruncateAndSetMAC<0>(
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s64(m_regs.ZSF4) * s32(u32(m_regs.SZ0) + u32(m_regs.SZ1) + u32(m_regs.SZ2) + u32(m_regs.SZ3)), 0);
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TruncateAndSetMAC<0>(result, 0);
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SetOTZ(s32(result >> 12));
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m_regs.FLAG.UpdateError();
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}
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s64 Core::VecDot(const s16 A[3], const s16 B[3])
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{
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return s64(s32(A[0]) * s32(B[0])) + s64(s32(A[1]) * s32(B[1])) + s64(s32(A[2]) * s32(B[2]));
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}
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s64 Core::VecDot(const s16 A[3], s16 B_x, s16 B_y, s16 B_z)
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{
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return s64(s32(A[0]) * s32(B_x)) + s64(s32(A[1]) * s32(B_y)) + s64(s32(A[2]) * s32(B_z));
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}
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void Core::MulMatVec(const s16 M[3][3], const s16 Vx, const s16 Vy, const s16 Vz, u8 shift, bool lm)
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{
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#define dot3(i) \
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TruncateAndSetMAC<i + 1>( \
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TruncateMAC<i + 1>(TruncateMAC<i + 1>(s64(s32(M[i][0]) * s32(Vx))) + s64(s32(M[i][1]) * s32(Vy))) + \
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CheckMACResult<i + 1>(CheckMACResult<i + 1>(s64(s32(M[i][0]) * s32(Vx))) + s64(s32(M[i][1]) * s32(Vy))) + \
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s64(s32(M[i][2]) * s32(Vz)), \
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shift)
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@ -569,9 +520,10 @@ void Core::MulMatVec(const s16 M[3][3], const s16 Vx, const s16 Vy, const s16 Vz
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void Core::MulMatVec(const s16 M[3][3], const s32 T[3], const s16 Vx, const s16 Vy, const s16 Vz, u8 shift, bool lm)
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{
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#define dot3(i) \
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TruncateAndSetMAC<i + 1>((s64(T[i]) << 12) + \
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TruncateMAC<i + 1>(TruncateMAC<i + 1>(TruncateMAC<i + 1>(s64(s32(M[i][0]) * s32(Vx))) + \
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s64(s32(M[i][1]) * s32(Vy))) + \
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TruncateAndSetMAC<i + 1>( \
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(s64(T[i]) << 12) + \
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CheckMACResult<i + 1>( \
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CheckMACResult<i + 1>(CheckMACResult<i + 1>(s64(s32(M[i][0]) * s32(Vx))) + s64(s32(M[i][1]) * s32(Vy))) + \
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s64(s32(M[i][2]) * s32(Vz))), \
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shift)
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@ -26,8 +26,8 @@ public:
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void ExecuteInstruction(Instruction inst);
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private:
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static constexpr s64 MAC0_MIN_VALUE = -(INT64_C(1) << 43);
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static constexpr s64 MAC0_MAX_VALUE = (INT64_C(1) << 43) - 1;
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static constexpr s64 MAC0_MIN_VALUE = -(INT64_C(1) << 31);
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static constexpr s64 MAC0_MAX_VALUE = (INT64_C(1) << 31) - 1;
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static constexpr s64 MAC123_MIN_VALUE = -(INT64_C(1) << 43);
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static constexpr s64 MAC123_MAX_VALUE = (INT64_C(1) << 43) - 1;
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static constexpr s32 IR0_MIN_VALUE = 0x0000;
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@ -35,28 +35,24 @@ private:
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static constexpr s32 IR123_MIN_VALUE = -(INT64_C(1) << 15);
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static constexpr s32 IR123_MAX_VALUE = (INT64_C(1) << 15) - 1;
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// Checks for underflow/overflow. Returns the value untouched so it can be threaded through an expression.
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template<u32 index>
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s64 TruncateMAC(s64 value);
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s64 CheckMACResult(s64 value);
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template<u32 index>
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s32 TruncateAndSetMAC(s64 value, u8 shift);
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template<u32 index>
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u8 TruncateRGB(s32 value);
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s64 TruncateAndSetMAC(s64 value, u8 shift);
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template<u32 index>
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s16 TruncateAndSetIR(s32 value, bool lm);
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void SetMAC(u32 index, s64 value);
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void SetIR(u32 index, s32 value, bool lm);
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template<u32 index>
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u8 TruncateRGB(s32 value);
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void SetOTZ(s32 value);
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void PushSXY(s32 x, s32 y);
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void PushSZ(s32 value);
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void PushRGB(u8 r, u8 g, u8 b, u8 c);
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s64 VecDot(const s16 A[3], const s16 B[3]);
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s64 VecDot(const s16 A[3], s16 B_x, s16 B_y, s16 B_z);
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// 3x3 matrix * 3x1 vector, updates MAC[1-3] and IR[1-3]
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void MulMatVec(const s16 M[3][3], const s16 Vx, const s16 Vy, const s16 Vz, u8 shift, bool lm);
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@ -1,25 +1,7 @@
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#include "gte.h"
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template<u32 index>
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u8 GTE::Core::TruncateRGB(s32 value)
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{
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if (value < 0 || value > 0xFF)
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{
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if constexpr (index == 0)
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m_regs.FLAG.color_r_saturated = true;
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else if constexpr (index == 1)
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m_regs.FLAG.color_g_saturated = true;
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else
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m_regs.FLAG.color_b_saturated = true;
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value = (value < 0) ? 0 : 0xFF;
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}
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return static_cast<u8>(value);
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}
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template<u32 index>
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s64 GTE::Core::TruncateMAC(s64 value)
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s64 GTE::Core::CheckMACResult(s64 value)
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{
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constexpr s64 MIN_VALUE = (index == 0) ? MAC0_MIN_VALUE : MAC123_MIN_VALUE;
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constexpr s64 MAX_VALUE = (index == 0) ? MAC0_MAX_VALUE : MAC123_MAX_VALUE;
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@ -33,8 +15,6 @@ s64 GTE::Core::TruncateMAC(s64 value)
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m_regs.FLAG.mac2_underflow = true;
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else if constexpr (index == 3)
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m_regs.FLAG.mac3_underflow = true;
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return MIN_VALUE;
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}
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else if (value > MAX_VALUE)
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{
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@ -46,26 +26,21 @@ s64 GTE::Core::TruncateMAC(s64 value)
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m_regs.FLAG.mac2_overflow = true;
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else if constexpr (index == 3)
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m_regs.FLAG.mac3_overflow = true;
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}
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return MAX_VALUE;
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}
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else
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{
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return value;
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}
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}
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template<u32 index>
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s32 GTE::Core::TruncateAndSetMAC(s64 value, u8 shift)
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s64 GTE::Core::TruncateAndSetMAC(s64 value, u8 shift)
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{
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value = TruncateMAC<index>(value);
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value = CheckMACResult<index>(value);
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// shift should be done before storing to avoid losing precision
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value >>= shift;
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const s32 value32 = static_cast<s32>(value);
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m_regs.dr32[24 + index] = value32;
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return value32;
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m_regs.dr32[24 + index] = Truncate32(static_cast<u64>(value));
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return value;
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}
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template<u32 index>
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@ -103,3 +78,21 @@ s16 GTE::Core::TruncateAndSetIR(s32 value, bool lm)
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m_regs.dr32[8 + index] = value;
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return static_cast<s16>(value);
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}
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template<u32 index>
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u8 GTE::Core::TruncateRGB(s32 value)
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{
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if (value < 0 || value > 0xFF)
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{
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if constexpr (index == 0)
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m_regs.FLAG.color_r_saturated = true;
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else if constexpr (index == 1)
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m_regs.FLAG.color_g_saturated = true;
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else
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m_regs.FLAG.color_b_saturated = true;
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value = (value < 0) ? 0 : 0xFF;
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}
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return static_cast<u8>(value);
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}
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