CPU/Recompiler: Reduce register pressure of lwl/lwr/swl/swr
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6df5824616
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@ -730,6 +730,57 @@ Value CodeGenerator::AndValues(const Value& lhs, const Value& rhs)
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return res;
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}
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void CodeGenerator::AndValueInPlace(Value& lhs, const Value& rhs)
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{
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DebugAssert(lhs.size == rhs.size);
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if (lhs.IsConstant() && rhs.IsConstant())
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{
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// compile-time
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u64 new_cv = lhs.constant_value & rhs.constant_value;
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switch (lhs.size)
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{
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case RegSize_8:
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lhs = Value::FromConstantU8(Truncate8(new_cv));
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break;
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case RegSize_16:
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lhs = Value::FromConstantU16(Truncate16(new_cv));
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break;
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case RegSize_32:
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lhs = Value::FromConstantU32(Truncate32(new_cv));
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break;
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case RegSize_64:
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lhs = Value::FromConstantU64(new_cv);
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break;
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default:
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lhs = Value();
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break;
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}
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}
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// TODO: and with -1 -> noop
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if (lhs.HasConstantValue(0) || rhs.HasConstantValue(0))
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{
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EmitXor(lhs.host_reg, lhs.host_reg, lhs);
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return;
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}
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if (lhs.IsInHostRegister())
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{
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EmitAnd(lhs.host_reg, lhs.host_reg, rhs);
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}
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else
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{
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Value new_lhs = m_register_cache.AllocateScratch(lhs.size);
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EmitCopyValue(new_lhs.host_reg, lhs);
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EmitAnd(new_lhs.host_reg, new_lhs.host_reg, rhs);
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lhs = std::move(new_lhs);
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}
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}
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Value CodeGenerator::XorValues(const Value& lhs, const Value& rhs)
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{
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DebugAssert(lhs.size == rhs.size);
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@ -1438,14 +1489,19 @@ bool CodeGenerator::Compile_LoadLeftRight(const CodeBlockInstruction& cbi)
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if (cbi.instruction.op == InstructionOp::lwl)
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{
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Value lhs = AndValues(value, ShrValues(Value::FromConstantU32(0x00FFFFFF), shift));
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Value lhs = ShrValues(Value::FromConstantU32(0x00FFFFFF), shift);
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AndValueInPlace(lhs, value);
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value.ReleaseAndClear();
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mem = ShlValues(mem, SubValues(Value::FromConstantU32(24), shift, false));
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EmitOr(mem.GetHostRegister(), mem.GetHostRegister(), lhs);
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}
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else
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{
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Value lhs = AndValues(
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value, ShlValues(Value::FromConstantU32(0xFFFFFF00), SubValues(Value::FromConstantU32(24), shift, false)));
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Value lhs = ShlValues(Value::FromConstantU32(0xFFFFFF00), SubValues(Value::FromConstantU32(24), shift, false));
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AndValueInPlace(lhs, value);
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value.ReleaseAndClear();
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EmitShr(mem.GetHostRegister(), mem.GetHostRegister(), RegSize_32, shift);
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EmitOr(mem.GetHostRegister(), mem.GetHostRegister(), lhs);
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}
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@ -1491,13 +1547,17 @@ bool CodeGenerator::Compile_StoreLeftRight(const CodeBlockInstruction& cbi)
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if (cbi.instruction.op == InstructionOp::swl)
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{
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Value lhs = ShrValues(reg, SubValues(Value::FromConstantU32(24), shift, false));
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reg.ReleaseAndClear();
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EmitAnd(mem.GetHostRegister(), mem.GetHostRegister(), ShlValues(Value::FromConstantU32(0xFFFFFF00), shift));
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EmitOr(mem.GetHostRegister(), mem.GetHostRegister(), lhs);
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}
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else
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{
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Value lhs = ShlValues(reg, shift);
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mem = AndValues(mem,
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reg.ReleaseAndClear();
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AndValueInPlace(mem,
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ShrValues(Value::FromConstantU32(0x00FFFFFF), SubValues(Value::FromConstantU32(24), shift, false)));
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EmitOr(mem.GetHostRegister(), mem.GetHostRegister(), lhs);
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}
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@ -163,6 +163,7 @@ public:
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Value SarValues(const Value& lhs, const Value& rhs, bool assume_amount_masked = true);
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Value OrValues(const Value& lhs, const Value& rhs);
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Value AndValues(const Value& lhs, const Value& rhs);
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void AndValueInPlace(Value& lhs, const Value& rhs);
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Value XorValues(const Value& lhs, const Value& rhs);
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Value NotValue(const Value& val);
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