CPU/Intepreter: Raise #RI on invalid COP0 move
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Stenzek
parent
62414b0c4c
commit
c6746e76f1
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@ -48,9 +48,6 @@ static u32 ReadReg(Reg rs);
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static void WriteReg(Reg rd, u32 value);
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static void WriteRegDelayed(Reg rd, u32 value);
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static u32 ReadCop0Reg(Cop0Reg reg);
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static void WriteCop0Reg(Cop0Reg reg, u32 value);
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static void DispatchCop0Breakpoint();
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static bool IsCop0ExecutionBreakpointUnmasked();
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static void Cop0ExecutionBreakpointCheck();
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@ -494,123 +491,6 @@ ALWAYS_INLINE_RELEASE void CPU::WriteRegDelayed(Reg rd, u32 value)
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g_state.next_load_delay_value = value;
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}
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ALWAYS_INLINE_RELEASE u32 CPU::ReadCop0Reg(Cop0Reg reg)
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{
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switch (reg)
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{
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case Cop0Reg::BPC:
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return g_state.cop0_regs.BPC;
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case Cop0Reg::BPCM:
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return g_state.cop0_regs.BPCM;
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case Cop0Reg::BDA:
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return g_state.cop0_regs.BDA;
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case Cop0Reg::BDAM:
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return g_state.cop0_regs.BDAM;
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case Cop0Reg::DCIC:
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return g_state.cop0_regs.dcic.bits;
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case Cop0Reg::JUMPDEST:
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return g_state.cop0_regs.TAR;
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case Cop0Reg::BadVaddr:
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return g_state.cop0_regs.BadVaddr;
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case Cop0Reg::SR:
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return g_state.cop0_regs.sr.bits;
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case Cop0Reg::CAUSE:
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return g_state.cop0_regs.cause.bits;
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case Cop0Reg::EPC:
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return g_state.cop0_regs.EPC;
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case Cop0Reg::PRID:
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return g_state.cop0_regs.PRID;
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default:
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return 0;
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}
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}
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ALWAYS_INLINE_RELEASE void CPU::WriteCop0Reg(Cop0Reg reg, u32 value)
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{
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switch (reg)
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{
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case Cop0Reg::BPC:
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{
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g_state.cop0_regs.BPC = value;
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DEV_LOG("COP0 BPC <- {:08X}", value);
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}
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break;
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case Cop0Reg::BPCM:
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{
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g_state.cop0_regs.BPCM = value;
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DEV_LOG("COP0 BPCM <- {:08X}", value);
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if (UpdateDebugDispatcherFlag())
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ExitExecution();
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}
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break;
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case Cop0Reg::BDA:
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{
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g_state.cop0_regs.BDA = value;
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DEV_LOG("COP0 BDA <- {:08X}", value);
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}
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break;
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case Cop0Reg::BDAM:
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{
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g_state.cop0_regs.BDAM = value;
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DEV_LOG("COP0 BDAM <- {:08X}", value);
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}
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break;
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case Cop0Reg::JUMPDEST:
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{
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WARNING_LOG("Ignoring write to Cop0 JUMPDEST");
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}
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break;
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case Cop0Reg::DCIC:
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{
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g_state.cop0_regs.dcic.bits =
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(g_state.cop0_regs.dcic.bits & ~Cop0Registers::DCIC::WRITE_MASK) | (value & Cop0Registers::DCIC::WRITE_MASK);
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DEV_LOG("COP0 DCIC <- {:08X} (now {:08X})", value, g_state.cop0_regs.dcic.bits);
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if (UpdateDebugDispatcherFlag())
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ExitExecution();
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}
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break;
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case Cop0Reg::SR:
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{
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g_state.cop0_regs.sr.bits =
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(g_state.cop0_regs.sr.bits & ~Cop0Registers::SR::WRITE_MASK) | (value & Cop0Registers::SR::WRITE_MASK);
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DEBUG_LOG("COP0 SR <- {:08X} (now {:08X})", value, g_state.cop0_regs.sr.bits);
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UpdateMemoryPointers();
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CheckForPendingInterrupt();
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}
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break;
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case Cop0Reg::CAUSE:
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{
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g_state.cop0_regs.cause.bits =
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(g_state.cop0_regs.cause.bits & ~Cop0Registers::CAUSE::WRITE_MASK) | (value & Cop0Registers::CAUSE::WRITE_MASK);
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DEBUG_LOG("COP0 CAUSE <- {:08X} (now {:08X})", value, g_state.cop0_regs.cause.bits);
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CheckForPendingInterrupt();
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}
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break;
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[[unlikely]] default:
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DEV_LOG("Unknown COP0 reg write {} ({:08X})", static_cast<u8>(reg), value);
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break;
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}
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}
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ALWAYS_INLINE_RELEASE bool CPU::IsCop0ExecutionBreakpointUnmasked()
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{
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static constexpr const u32 code_address_ranges[][2] = {
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@ -1776,7 +1656,59 @@ restart_instruction:
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{
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case CopCommonInstruction::mfcn:
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{
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const u32 value = ReadCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue()));
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u32 value;
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switch (static_cast<Cop0Reg>(inst.r.rd.GetValue()))
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{
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case Cop0Reg::BPC:
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value = g_state.cop0_regs.BPC;
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break;
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case Cop0Reg::BPCM:
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value = g_state.cop0_regs.BPCM;
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break;
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case Cop0Reg::BDA:
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value = g_state.cop0_regs.BDA;
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break;
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case Cop0Reg::BDAM:
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value = g_state.cop0_regs.BDAM;
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break;
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case Cop0Reg::DCIC:
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value = g_state.cop0_regs.dcic.bits;
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break;
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case Cop0Reg::JUMPDEST:
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value = g_state.cop0_regs.TAR;
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break;
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case Cop0Reg::BadVaddr:
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value = g_state.cop0_regs.BadVaddr;
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break;
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case Cop0Reg::SR:
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value = g_state.cop0_regs.sr.bits;
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break;
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case Cop0Reg::CAUSE:
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value = g_state.cop0_regs.cause.bits;
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break;
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case Cop0Reg::EPC:
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value = g_state.cop0_regs.EPC;
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break;
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case Cop0Reg::PRID:
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value = g_state.cop0_regs.PRID;
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break;
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default:
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RaiseException(Exception::RI);
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return;
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}
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WriteRegDelayed(inst.r.rt, value);
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if constexpr (pgxp_mode == PGXPMode::CPU)
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@ -1786,11 +1718,86 @@ restart_instruction:
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case CopCommonInstruction::mtcn:
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{
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const u32 rtVal = ReadReg(inst.r.rt);
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WriteCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue()), rtVal);
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u32 value = ReadReg(inst.r.rt);
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[[maybe_unused]] const u32 orig_value = value;
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switch (static_cast<Cop0Reg>(inst.r.rd.GetValue()))
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{
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case Cop0Reg::BPC:
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{
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g_state.cop0_regs.BPC = value;
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DEV_LOG("COP0 BPC <- {:08X}", value);
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}
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break;
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case Cop0Reg::BPCM:
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{
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g_state.cop0_regs.BPCM = value;
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DEV_LOG("COP0 BPCM <- {:08X}", value);
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if (UpdateDebugDispatcherFlag())
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ExitExecution();
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}
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break;
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case Cop0Reg::BDA:
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{
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g_state.cop0_regs.BDA = value;
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DEV_LOG("COP0 BDA <- {:08X}", value);
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}
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break;
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case Cop0Reg::BDAM:
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{
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g_state.cop0_regs.BDAM = value;
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DEV_LOG("COP0 BDAM <- {:08X}", value);
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}
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break;
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case Cop0Reg::JUMPDEST:
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{
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WARNING_LOG("Ignoring write to Cop0 JUMPDEST");
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}
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break;
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case Cop0Reg::DCIC:
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{
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g_state.cop0_regs.dcic.bits = (g_state.cop0_regs.dcic.bits & ~Cop0Registers::DCIC::WRITE_MASK) |
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(value & Cop0Registers::DCIC::WRITE_MASK);
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DEV_LOG("COP0 DCIC <- {:08X} (now {:08X})", value, g_state.cop0_regs.dcic.bits);
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value = g_state.cop0_regs.dcic.bits;
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if (UpdateDebugDispatcherFlag())
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ExitExecution();
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}
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break;
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case Cop0Reg::SR:
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{
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g_state.cop0_regs.sr.bits = (g_state.cop0_regs.sr.bits & ~Cop0Registers::SR::WRITE_MASK) |
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(value & Cop0Registers::SR::WRITE_MASK);
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DEBUG_LOG("COP0 SR <- {:08X} (now {:08X})", value, g_state.cop0_regs.sr.bits);
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value = g_state.cop0_regs.sr.bits;
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UpdateMemoryPointers();
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CheckForPendingInterrupt();
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}
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break;
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case Cop0Reg::CAUSE:
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{
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g_state.cop0_regs.cause.bits = (g_state.cop0_regs.cause.bits & ~Cop0Registers::CAUSE::WRITE_MASK) |
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(value & Cop0Registers::CAUSE::WRITE_MASK);
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DEBUG_LOG("COP0 CAUSE <- {:08X} (now {:08X})", value, g_state.cop0_regs.cause.bits);
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value = g_state.cop0_regs.cause.bits;
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CheckForPendingInterrupt();
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}
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break;
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[[unlikely]] default:
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RaiseException(Exception::RI);
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return;
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}
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if constexpr (pgxp_mode == PGXPMode::CPU)
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PGXP::CPU_MTC0(inst, ReadCop0Reg(static_cast<Cop0Reg>(inst.r.rd.GetValue())), rtVal);
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PGXP::CPU_MTC0(inst, value, orig_value);
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}
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break;
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@ -1818,7 +1825,7 @@ restart_instruction:
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case Cop0Instruction::tlbwr:
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case Cop0Instruction::tlbp:
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RaiseException(Exception::RI);
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break;
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return;
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default:
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[[unlikely]] ERROR_LOG("Unhandled instruction at {:08X}: {:08X}", g_state.current_instruction_pc,
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