CPU/NewRec/RISCV64: Implement PGXP
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8206b2b74a
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@ -8,6 +8,7 @@
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#include "common/string_util.h"
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#include "cpu_code_cache_private.h"
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#include "cpu_core_private.h"
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#include "cpu_pgxp.h"
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#include "cpu_recompiler_thunks.h"
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#include "gte.h"
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#include "settings.h"
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@ -1601,7 +1602,7 @@ biscuit::GPR CPU::NewRec::RISCV64Compiler::ComputeLoadStoreAddressArg(
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}
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template<typename RegAllocFn>
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void CPU::NewRec::RISCV64Compiler::GenerateLoad(const biscuit::GPR& addr_reg, MemoryAccessSize size, bool sign,
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biscuit::GPR CPU::NewRec::RISCV64Compiler::GenerateLoad(const biscuit::GPR& addr_reg, MemoryAccessSize size, bool sign,
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bool use_fastmem, const RegAllocFn& dst_reg_alloc)
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{
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if (use_fastmem)
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@ -1648,7 +1649,7 @@ void CPU::NewRec::RISCV64Compiler::GenerateLoad(const biscuit::GPR& addr_reg, Me
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rvAsm->NOP();
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AddLoadStoreInfo(start, 8, addr_reg.Index(), dst.Index(), size, sign, true);
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return;
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return dst;
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}
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if (addr_reg.Index() != RARG1.Index())
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@ -1727,6 +1728,8 @@ void CPU::NewRec::RISCV64Compiler::GenerateLoad(const biscuit::GPR& addr_reg, Me
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}
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break;
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}
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return dst_reg;
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}
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void CPU::NewRec::RISCV64Compiler::GenerateStore(const biscuit::GPR& addr_reg, const biscuit::GPR& value_reg,
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@ -1832,15 +1835,29 @@ void CPU::NewRec::RISCV64Compiler::GenerateStore(const biscuit::GPR& addr_reg, c
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void CPU::NewRec::RISCV64Compiler::Compile_lxx(CompileFlags cf, MemoryAccessSize size, bool sign, bool use_fastmem,
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const std::optional<VirtualMemoryAddress>& address)
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{
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const std::optional<GPR> addr_reg = (g_settings.gpu_pgxp_enable && cf.MipsT() != Reg::zero) ?
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std::optional<GPR>(GPR(AllocateTempHostReg(HR_CALLEE_SAVED))) :
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std::optional<GPR>();
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FlushForLoadStore(address, false, use_fastmem);
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const GPR addr = ComputeLoadStoreAddressArg(cf, address);
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GenerateLoad(addr, size, sign, use_fastmem, [this, cf]() {
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const GPR addr = ComputeLoadStoreAddressArg(cf, address, addr_reg);
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const GPR data = GenerateLoad(addr, size, sign, use_fastmem, [this, cf]() {
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if (cf.MipsT() == Reg::zero)
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return RRET;
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return GPR(AllocateHostReg(HR_MODE_WRITE, EMULATE_LOAD_DELAYS ? HR_TYPE_NEXT_LOAD_DELAY_VALUE : HR_TYPE_CPU_REG,
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cf.MipsT()));
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return GPR(AllocateHostReg(GetFlagsForNewLoadDelayedReg(),
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EMULATE_LOAD_DELAYS ? HR_TYPE_NEXT_LOAD_DELAY_VALUE : HR_TYPE_CPU_REG, cf.MipsT()));
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});
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if (g_settings.gpu_pgxp_enable && cf.MipsT() != Reg::zero)
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{
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Flush(FLUSH_FOR_C_CALL);
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EmitMov(RARG1, inst->bits);
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rvAsm->MV(RARG2, addr);
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rvAsm->MV(RARG3, data);
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EmitCall(s_pgxp_mem_load_functions[static_cast<u32>(size)][static_cast<u32>(sign)]);
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FreeHostReg(addr_reg.value().Index());
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}
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}
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void CPU::NewRec::RISCV64Compiler::Compile_lwx(CompileFlags cf, MemoryAccessSize size, bool sign, bool use_fastmem,
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@ -1931,8 +1948,10 @@ void CPU::NewRec::RISCV64Compiler::Compile_lwx(CompileFlags cf, MemoryAccessSize
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void CPU::NewRec::RISCV64Compiler::Compile_lwc2(CompileFlags cf, MemoryAccessSize size, bool sign, bool use_fastmem,
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const std::optional<VirtualMemoryAddress>& address)
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{
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const std::optional<GPR> addr_reg =
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g_settings.gpu_pgxp_enable ? std::optional<GPR>(GPR(AllocateTempHostReg(HR_CALLEE_SAVED))) : std::optional<GPR>();
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FlushForLoadStore(address, false, use_fastmem);
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const GPR addr = ComputeLoadStoreAddressArg(cf, address);
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const GPR addr = ComputeLoadStoreAddressArg(cf, address, addr_reg);
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GenerateLoad(addr, MemoryAccessSize::Word, false, use_fastmem, []() { return RRET; });
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const u32 index = static_cast<u32>(inst->r.rt.GetValue());
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@ -1941,27 +1960,27 @@ void CPU::NewRec::RISCV64Compiler::Compile_lwc2(CompileFlags cf, MemoryAccessSiz
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{
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case GTERegisterAccessAction::Ignore:
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{
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return;
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break;
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}
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case GTERegisterAccessAction::Direct:
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{
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rvAsm->SW(RRET, PTR(ptr));
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return;
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break;
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}
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case GTERegisterAccessAction::SignExtend16:
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{
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EmitSExtH(RRET, RRET);
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rvAsm->SW(RRET, PTR(ptr));
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return;
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break;
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}
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case GTERegisterAccessAction::ZeroExtend16:
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{
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EmitUExtH(RRET, RRET);
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rvAsm->SW(RRET, PTR(ptr));
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return;
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break;
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}
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case GTERegisterAccessAction::CallHandler:
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@ -1970,7 +1989,7 @@ void CPU::NewRec::RISCV64Compiler::Compile_lwc2(CompileFlags cf, MemoryAccessSiz
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rvAsm->MV(RARG2, RRET);
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EmitMov(RARG1, index);
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EmitCall(reinterpret_cast<const void*>(>E::WriteRegister));
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return;
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break;
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}
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case GTERegisterAccessAction::PushFIFO:
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@ -1984,7 +2003,7 @@ void CPU::NewRec::RISCV64Compiler::Compile_lwc2(CompileFlags cf, MemoryAccessSiz
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rvAsm->SW(RARG2, PTR(&g_state.gte_regs.SXY0[0]));
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rvAsm->SW(RARG3, PTR(&g_state.gte_regs.SXY1[0]));
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rvAsm->SW(RRET, PTR(&g_state.gte_regs.SXY2[0]));
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return;
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break;
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}
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default:
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@ -1993,6 +2012,16 @@ void CPU::NewRec::RISCV64Compiler::Compile_lwc2(CompileFlags cf, MemoryAccessSiz
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return;
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}
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}
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if (g_settings.gpu_pgxp_enable)
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{
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Flush(FLUSH_FOR_C_CALL);
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rvAsm->MV(RARG3, RRET);
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rvAsm->MV(RARG2, addr);
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EmitMov(RARG1, inst->bits);
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EmitCall(reinterpret_cast<const void*>(&PGXP::CPU_LWC2));
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FreeHostReg(addr_reg.value().Index());
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}
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}
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void CPU::NewRec::RISCV64Compiler::Compile_sxx(CompileFlags cf, MemoryAccessSize size, bool sign, bool use_fastmem,
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@ -2000,13 +2029,26 @@ void CPU::NewRec::RISCV64Compiler::Compile_sxx(CompileFlags cf, MemoryAccessSize
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{
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AssertRegOrConstS(cf);
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AssertRegOrConstT(cf);
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FlushForLoadStore(address, true, use_fastmem);
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const GPR addr = ComputeLoadStoreAddressArg(cf, address);
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const std::optional<GPR> addr_reg =
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g_settings.gpu_pgxp_enable ? std::optional<GPR>(GPR(AllocateTempHostReg(HR_CALLEE_SAVED))) : std::optional<GPR>();
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FlushForLoadStore(address, true, use_fastmem);
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const GPR addr = ComputeLoadStoreAddressArg(cf, address, addr_reg);
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const GPR data = cf.valid_host_t ? CFGetRegT(cf) : RARG2;
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if (!cf.valid_host_t)
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MoveTToReg(RARG2, cf);
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GenerateStore(addr, cf.valid_host_t ? CFGetRegT(cf) : RARG2, size, use_fastmem);
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GenerateStore(addr, data, size, use_fastmem);
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if (g_settings.gpu_pgxp_enable)
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{
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Flush(FLUSH_FOR_C_CALL);
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MoveMIPSRegToReg(RARG3, cf.MipsT());
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rvAsm->MV(RARG2, addr);
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EmitMov(RARG1, inst->bits);
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EmitCall(s_pgxp_mem_store_functions[static_cast<u32>(size)]);
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FreeHostReg(addr_reg.value().Index());
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}
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}
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void CPU::NewRec::RISCV64Compiler::Compile_swx(CompileFlags cf, MemoryAccessSize size, bool sign, bool use_fastmem,
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@ -2102,8 +2144,29 @@ void CPU::NewRec::RISCV64Compiler::Compile_swc2(CompileFlags cf, MemoryAccessSiz
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break;
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}
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// PGXP makes this a giant pain.
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if (!g_settings.gpu_pgxp_enable)
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{
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const GPR addr = ComputeLoadStoreAddressArg(cf, address);
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GenerateStore(addr, RARG2, size, use_fastmem);
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return;
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}
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// TODO: This can be simplified because we don't need to validate in PGXP..
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const GPR addr_reg = GPR(AllocateTempHostReg(HR_CALLEE_SAVED));
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const GPR data_backup = GPR(AllocateTempHostReg(HR_CALLEE_SAVED));
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FlushForLoadStore(address, true, use_fastmem);
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ComputeLoadStoreAddressArg(cf, address, addr_reg);
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rvAsm->MV(data_backup, RARG2);
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GenerateStore(addr_reg, RARG2, size, use_fastmem);
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Flush(FLUSH_FOR_C_CALL);
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rvAsm->MV(RARG3, data_backup);
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rvAsm->MV(RARG2, addr_reg);
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EmitMov(RARG1, inst->bits);
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EmitCall(reinterpret_cast<const void*>(&PGXP::CPU_SWC2));
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FreeHostReg(addr_reg.Index());
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FreeHostReg(data_backup.Index());
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}
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void CPU::NewRec::RISCV64Compiler::Compile_mtc0(CompileFlags cf)
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if (action == GTERegisterAccessAction::Ignore)
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return;
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u32 hreg;
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if (action == GTERegisterAccessAction::Direct)
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{
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const u32 hreg =
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AllocateHostReg(HR_MODE_WRITE, EMULATE_LOAD_DELAYS ? HR_TYPE_NEXT_LOAD_DELAY_VALUE : HR_TYPE_CPU_REG, rt);
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hreg = AllocateHostReg(GetFlagsForNewLoadDelayedReg(),
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EMULATE_LOAD_DELAYS ? HR_TYPE_NEXT_LOAD_DELAY_VALUE : HR_TYPE_CPU_REG, rt);
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rvAsm->LW(GPR(hreg), PTR(ptr));
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}
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else if (action == GTERegisterAccessAction::CallHandler)
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EmitMov(RARG1, index);
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EmitCall(reinterpret_cast<const void*>(>E::ReadRegister));
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const u32 hreg =
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AllocateHostReg(HR_MODE_WRITE, EMULATE_LOAD_DELAYS ? HR_TYPE_NEXT_LOAD_DELAY_VALUE : HR_TYPE_CPU_REG, rt);
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hreg = AllocateHostReg(GetFlagsForNewLoadDelayedReg(),
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EMULATE_LOAD_DELAYS ? HR_TYPE_NEXT_LOAD_DELAY_VALUE : HR_TYPE_CPU_REG, rt);
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rvAsm->MV(GPR(hreg), RRET);
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}
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else
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{
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Panic("Unknown action");
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}
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if (g_settings.gpu_pgxp_enable)
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{
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Flush(FLUSH_FOR_C_CALL);
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EmitMov(RARG1, inst->bits);
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rvAsm->MV(RARG2, GPR(hreg));
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EmitCall(reinterpret_cast<const void*>(&PGXP::CPU_MFC2));
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}
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}
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void CPU::NewRec::RISCV64Compiler::Compile_mtc2(CompileFlags cf)
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@ -90,7 +90,7 @@ protected:
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biscuit::GPR ComputeLoadStoreAddressArg(CompileFlags cf, const std::optional<VirtualMemoryAddress>& address,
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const std::optional<const biscuit::GPR>& reg = std::nullopt);
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template<typename RegAllocFn>
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void GenerateLoad(const biscuit::GPR& addr_reg, MemoryAccessSize size, bool sign, bool use_fastmem,
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biscuit::GPR GenerateLoad(const biscuit::GPR& addr_reg, MemoryAccessSize size, bool sign, bool use_fastmem,
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const RegAllocFn& dst_reg_alloc);
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void GenerateStore(const biscuit::GPR& addr_reg, const biscuit::GPR& value_reg, MemoryAccessSize size,
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bool use_fastmem);
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