GTE: Implement GPL instruction
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8aed0cc174
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@ -314,6 +314,10 @@ void Core::ExecuteInstruction(Instruction inst)
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Execute_RTPT(inst);
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Execute_RTPT(inst);
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break;
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break;
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case 0x3E:
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Execute_GPL(inst);
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break;
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case 0x3F:
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case 0x3F:
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Execute_NCCT(inst);
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Execute_NCCT(inst);
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break;
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break;
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@ -834,4 +838,34 @@ void Core::Execute_DPCL(Instruction inst)
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m_regs.FLAG.UpdateError();
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m_regs.FLAG.UpdateError();
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}
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}
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void Core::Execute_GPL(Instruction inst)
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{
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m_regs.FLAG.Clear();
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const u8 shift = inst.GetShift();
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const bool lm = inst.lm;
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// [MAC1,MAC2,MAC3] = [MAC1,MAC2,MAC3] SHL (sf*12) ;<--- for GPL only
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if (inst.sf)
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{
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TruncateAndSetMAC<1>(s64(m_regs.MAC1), shift);
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TruncateAndSetMAC<2>(s64(m_regs.MAC2), shift);
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TruncateAndSetMAC<3>(s64(m_regs.MAC3), shift);
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}
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// [MAC1,MAC2,MAC3] = (([IR1,IR2,IR3] * IR0) + [MAC1,MAC2,MAC3]) SAR (sf*12)
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TruncateAndSetMAC<1>((s64(s32(m_regs.IR1) * s32(m_regs.IR0)) + s64(m_regs.MAC1)) >> shift, 0);
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TruncateAndSetMAC<2>((s64(s32(m_regs.IR2) * s32(m_regs.IR0)) + s64(m_regs.MAC2)) >> shift, 0);
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TruncateAndSetMAC<3>((s64(s32(m_regs.IR3) * s32(m_regs.IR0)) + s64(m_regs.MAC3)) >> shift, 0);
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// Color FIFO = [MAC1/16,MAC2/16,MAC3/16,CODE], [IR1,IR2,IR3] = [MAC1,MAC2,MAC3]
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PushRGB(TruncateRGB<0>(m_regs.MAC1 / 16), TruncateRGB<1>(m_regs.MAC2 / 16), TruncateRGB<2>(m_regs.MAC3 / 16),
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m_regs.RGBC[3]);
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TruncateAndSetIR<1>(m_regs.MAC1, lm);
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TruncateAndSetIR<2>(m_regs.MAC2, lm);
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TruncateAndSetIR<3>(m_regs.MAC3, lm);
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m_regs.FLAG.UpdateError();
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}
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} // namespace GTE
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} // namespace GTE
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@ -78,6 +78,7 @@ private:
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void Execute_DPCS(Instruction inst);
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void Execute_DPCS(Instruction inst);
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void Execute_DPCT(Instruction inst);
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void Execute_DPCT(Instruction inst);
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void Execute_DPCL(Instruction inst);
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void Execute_DPCL(Instruction inst);
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void Execute_GPL(Instruction inst);
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Regs m_regs = {};
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Regs m_regs = {};
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};
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};
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