DMA: Properly handle infinite linked lists, add cycle stealing
Fixes Tekken 2, Hot Wheels Turbo Racing, probably others.
This commit is contained in:
parent
07e8ddcae2
commit
9d1eb321ec
122
src/core/dma.cpp
122
src/core/dma.cpp
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@ -26,12 +26,12 @@ void DMA::Initialize(System* system, Bus* bus, InterruptController* interrupt_co
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m_spu = spu;
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m_spu = spu;
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m_mdec = mdec;
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m_mdec = mdec;
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m_transfer_buffer.resize(32);
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m_transfer_buffer.resize(32);
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m_unhalt_event = system->CreateTimingEvent("DMA Transfer Unhalt", 1, m_max_slice_ticks,
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std::bind(&DMA::UnhaltTransfer, this, std::placeholders::_1), false);
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}
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}
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void DMA::Reset()
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void DMA::Reset()
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{
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{
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m_DPCR.bits = 0x07654321;
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m_DICR.bits = 0;
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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{
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ChannelState& cs = m_state[i];
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ChannelState& cs = m_state[i];
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@ -40,10 +40,18 @@ void DMA::Reset()
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cs.channel_control.bits = 0;
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cs.channel_control.bits = 0;
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cs.request = false;
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cs.request = false;
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}
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}
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m_DPCR.bits = 0x07654321;
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m_DICR.bits = 0;
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m_halt_ticks_remaining = 0;
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m_unhalt_event->Deactivate();
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}
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}
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bool DMA::DoState(StateWrapper& sw)
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bool DMA::DoState(StateWrapper& sw)
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{
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{
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sw.Do(&m_halt_ticks_remaining);
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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{
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ChannelState& cs = m_state[i];
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ChannelState& cs = m_state[i];
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@ -56,6 +64,14 @@ bool DMA::DoState(StateWrapper& sw)
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sw.Do(&m_DPCR.bits);
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sw.Do(&m_DPCR.bits);
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sw.Do(&m_DICR.bits);
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sw.Do(&m_DICR.bits);
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if (sw.IsReading())
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{
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if (m_halt_ticks_remaining > 0)
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m_unhalt_event->SetIntervalAndSchedule(m_halt_ticks_remaining);
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else
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m_unhalt_event->Deactivate();
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}
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return !sw.HasError();
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return !sw.HasError();
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}
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}
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@ -121,8 +137,6 @@ void DMA::WriteRegister(u32 offset, u32 value)
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{
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{
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Log_TracePrintf("DMA channel %u block control <- 0x%08X", channel_index, value);
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Log_TracePrintf("DMA channel %u block control <- 0x%08X", channel_index, value);
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state.block_control.bits = value;
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state.block_control.bits = value;
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if (CanTransferChannel(static_cast<Channel>(channel_index)))
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TransferChannel(static_cast<Channel>(channel_index));
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return;
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return;
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}
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}
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@ -136,7 +150,7 @@ void DMA::WriteRegister(u32 offset, u32 value)
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if (static_cast<Channel>(channel_index) == Channel::OTC)
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if (static_cast<Channel>(channel_index) == Channel::OTC)
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SetRequest(static_cast<Channel>(channel_index), state.channel_control.start_trigger);
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SetRequest(static_cast<Channel>(channel_index), state.channel_control.start_trigger);
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if (CanTransferChannel(static_cast<Channel>(channel_index)))
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if (!IsTransferHalted() && CanTransferChannel(static_cast<Channel>(channel_index)))
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TransferChannel(static_cast<Channel>(channel_index));
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TransferChannel(static_cast<Channel>(channel_index));
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return;
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return;
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}
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}
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@ -153,10 +167,16 @@ void DMA::WriteRegister(u32 offset, u32 value)
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{
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{
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Log_TracePrintf("DPCR <- 0x%08X", value);
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Log_TracePrintf("DPCR <- 0x%08X", value);
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m_DPCR.bits = value;
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m_DPCR.bits = value;
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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if (!IsTransferHalted())
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{
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{
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if (CanTransferChannel(static_cast<Channel>(i)))
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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TransferChannel(static_cast<Channel>(i));
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{
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if (CanTransferChannel(static_cast<Channel>(i)))
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{
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if (!TransferChannel(static_cast<Channel>(i)))
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break;
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}
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}
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}
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}
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return;
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return;
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}
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}
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@ -185,7 +205,7 @@ void DMA::SetRequest(Channel channel, bool request)
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return;
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return;
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cs.request = request;
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cs.request = request;
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if (CanTransferChannel(channel))
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if (!IsTransferHalted() && CanTransferChannel(channel))
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TransferChannel(channel);
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TransferChannel(channel);
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}
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}
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@ -201,6 +221,11 @@ bool DMA::CanTransferChannel(Channel channel) const
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return cs.request;
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return cs.request;
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}
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}
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bool DMA::IsTransferHalted() const
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{
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return m_unhalt_event->IsActive();
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}
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void DMA::UpdateIRQ()
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void DMA::UpdateIRQ()
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{
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{
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m_DICR.UpdateMasterFlag();
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m_DICR.UpdateMasterFlag();
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@ -211,7 +236,7 @@ void DMA::UpdateIRQ()
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}
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}
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}
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}
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void DMA::TransferChannel(Channel channel)
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bool DMA::TransferChannel(Channel channel)
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{
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{
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ChannelState& cs = m_state[static_cast<u32>(channel)];
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ChannelState& cs = m_state[static_cast<u32>(channel)];
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@ -229,15 +254,20 @@ void DMA::TransferChannel(Channel channel)
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const u32 word_count = cs.block_control.manual.GetWordCount();
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const u32 word_count = cs.block_control.manual.GetWordCount();
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Log_DebugPrintf("DMA%u: Copying %u words %s 0x%08X", static_cast<u32>(channel), word_count,
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Log_DebugPrintf("DMA%u: Copying %u words %s 0x%08X", static_cast<u32>(channel), word_count,
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copy_to_device ? "from" : "to", current_address & ADDRESS_MASK);
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copy_to_device ? "from" : "to", current_address & ADDRESS_MASK);
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TickCount used_ticks;
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if (copy_to_device)
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if (copy_to_device)
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TransferMemoryToDevice(channel, current_address & ADDRESS_MASK, increment, word_count);
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used_ticks = TransferMemoryToDevice(channel, current_address & ADDRESS_MASK, increment, word_count);
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else
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else
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TransferDeviceToMemory(channel, current_address & ADDRESS_MASK, increment, word_count);
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used_ticks = TransferDeviceToMemory(channel, current_address & ADDRESS_MASK, increment, word_count);
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m_system->StallCPU(used_ticks);
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}
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}
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break;
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break;
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case SyncMode::LinkedList:
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case SyncMode::LinkedList:
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{
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{
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TickCount used_ticks = 0;
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if (!copy_to_device)
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if (!copy_to_device)
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{
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{
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Panic("Linked list not implemented for DMA reads");
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Panic("Linked list not implemented for DMA reads");
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@ -248,17 +278,21 @@ void DMA::TransferChannel(Channel channel)
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current_address & ADDRESS_MASK);
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current_address & ADDRESS_MASK);
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u8* ram_pointer = m_bus->GetRAM();
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u8* ram_pointer = m_bus->GetRAM();
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while (cs.request)
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while (cs.request && used_ticks < m_max_slice_ticks)
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{
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{
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u32 header;
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u32 header;
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std::memcpy(&header, &ram_pointer[current_address & ADDRESS_MASK], sizeof(header));
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std::memcpy(&header, &ram_pointer[current_address & ADDRESS_MASK], sizeof(header));
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used_ticks++;
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const u32 word_count = header >> 24;
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const u32 word_count = header >> 24;
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const u32 next_address = header & UINT32_C(0x00FFFFFF);
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const u32 next_address = header & UINT32_C(0x00FFFFFF);
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Log_TracePrintf(" .. linked list entry at 0x%08X size=%u(%u words) next=0x%08X",
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Log_TracePrintf(" .. linked list entry at 0x%08X size=%u(%u words) next=0x%08X",
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current_address & ADDRESS_MASK, word_count * UINT32_C(4), word_count, next_address);
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current_address & ADDRESS_MASK, word_count * UINT32_C(4), word_count, next_address);
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if (word_count > 0)
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if (word_count > 0)
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TransferMemoryToDevice(channel, (current_address + sizeof(header)) & ADDRESS_MASK, 4, word_count);
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{
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used_ticks +=
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TransferMemoryToDevice(channel, (current_address + sizeof(header)) & ADDRESS_MASK, 4, word_count);
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}
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current_address = next_address;
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current_address = next_address;
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if (current_address & UINT32_C(0x800000))
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if (current_address & UINT32_C(0x800000))
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@ -267,11 +301,20 @@ void DMA::TransferChannel(Channel channel)
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}
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}
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cs.base_address = current_address;
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cs.base_address = current_address;
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m_system->StallCPU(used_ticks);
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if (used_ticks >= m_max_slice_ticks)
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{
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// stall the transfer for a bit if we ran for too long
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//Log_WarningPrintf("breaking dma chain at 0x%08X", current_address);
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HaltTransfer(m_halt_ticks);
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return false;
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}
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if ((current_address & UINT32_C(0x800000)) == 0)
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if ((current_address & UINT32_C(0x800000)) == 0)
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{
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{
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// linked list not yet complete
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// linked list not yet complete
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return;
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return true;
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}
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}
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}
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}
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break;
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break;
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@ -285,13 +328,14 @@ void DMA::TransferChannel(Channel channel)
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const u32 block_size = cs.block_control.request.GetBlockSize();
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const u32 block_size = cs.block_control.request.GetBlockSize();
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u32 blocks_remaining = cs.block_control.request.GetBlockCount();
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u32 blocks_remaining = cs.block_control.request.GetBlockCount();
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TickCount used_ticks = 0;
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if (copy_to_device)
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if (copy_to_device)
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{
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{
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do
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do
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{
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{
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blocks_remaining--;
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blocks_remaining--;
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TransferMemoryToDevice(channel, current_address & ADDRESS_MASK, increment, block_size);
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used_ticks += TransferMemoryToDevice(channel, current_address & ADDRESS_MASK, increment, block_size);
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current_address = (current_address + (increment * block_size));
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current_address = (current_address + (increment * block_size));
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} while (cs.request && blocks_remaining > 0);
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} while (cs.request && blocks_remaining > 0);
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}
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}
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@ -300,17 +344,18 @@ void DMA::TransferChannel(Channel channel)
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do
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do
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{
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{
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blocks_remaining--;
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blocks_remaining--;
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TransferDeviceToMemory(channel, current_address & ADDRESS_MASK, increment, block_size);
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used_ticks += TransferDeviceToMemory(channel, current_address & ADDRESS_MASK, increment, block_size);
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current_address = (current_address + (increment * block_size));
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current_address = (current_address + (increment * block_size));
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} while (cs.request && blocks_remaining > 0);
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} while (cs.request && blocks_remaining > 0);
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}
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}
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cs.base_address = current_address & BASE_ADDRESS_MASK;
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cs.base_address = current_address & BASE_ADDRESS_MASK;
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cs.block_control.request.block_count = blocks_remaining;
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cs.block_control.request.block_count = blocks_remaining;
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m_system->StallCPU(used_ticks);
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// finish transfer later if the request was cleared
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// finish transfer later if the request was cleared
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if (blocks_remaining > 0)
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if (blocks_remaining > 0)
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return;
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return true;
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}
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}
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break;
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break;
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@ -327,9 +372,41 @@ void DMA::TransferChannel(Channel channel)
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m_DICR.SetIRQFlag(channel);
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m_DICR.SetIRQFlag(channel);
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UpdateIRQ();
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UpdateIRQ();
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}
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}
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return true;
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}
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}
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void DMA::TransferMemoryToDevice(Channel channel, u32 address, u32 increment, u32 word_count)
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void DMA::HaltTransfer(TickCount duration)
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{
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m_halt_ticks_remaining += duration;
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Log_DebugPrintf("Halting DMA for %d ticks", m_halt_ticks_remaining);
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DebugAssert(!m_unhalt_event->IsActive());
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m_unhalt_event->SetIntervalAndSchedule(m_halt_ticks_remaining);
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}
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void DMA::UnhaltTransfer(TickCount ticks)
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{
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Log_DebugPrintf("Resuming DMA after %d ticks, %d ticks late", ticks, -(m_halt_ticks_remaining - ticks));
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m_halt_ticks_remaining -= ticks;
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m_unhalt_event->Deactivate();
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// TODO: Use channel priority. But doing it in ascending order is probably good enough.
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// Main thing is that OTC happens after GPU, because otherwise it'll wipe out the LL.
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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if (CanTransferChannel(static_cast<Channel>(i)))
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{
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if (!TransferChannel(static_cast<Channel>(i)))
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return;
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}
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}
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// We didn't run too long, so reset timer.
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m_halt_ticks_remaining = 0;
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}
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TickCount DMA::TransferMemoryToDevice(Channel channel, u32 address, u32 increment, u32 word_count)
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{
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{
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const u32* src_pointer = reinterpret_cast<u32*>(m_bus->GetRAM() + address);
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const u32* src_pointer = reinterpret_cast<u32*>(m_bus->GetRAM() + address);
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if (static_cast<s32>(increment) < 0 || ((address + (increment * word_count)) & ADDRESS_MASK) <= address)
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if (static_cast<s32>(increment) < 0 || ((address + (increment * word_count)) & ADDRESS_MASK) <= address)
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@ -362,9 +439,11 @@ void DMA::TransferMemoryToDevice(Channel channel, u32 address, u32 increment, u3
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Panic("Unhandled DMA channel for device write");
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Panic("Unhandled DMA channel for device write");
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break;
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break;
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}
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}
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return m_bus->GetDMARAMTickCount(word_count);
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}
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}
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void DMA::TransferDeviceToMemory(Channel channel, u32 address, u32 increment, u32 word_count)
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TickCount DMA::TransferDeviceToMemory(Channel channel, u32 address, u32 increment, u32 word_count)
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{
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{
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if (channel == Channel::OTC)
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if (channel == Channel::OTC)
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{
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{
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@ -381,7 +460,7 @@ void DMA::TransferDeviceToMemory(Channel channel, u32 address, u32 increment, u3
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const u32 terminator = UINT32_C(0xFFFFFFF);
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const u32 terminator = UINT32_C(0xFFFFFFF);
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std::memcpy(&ram_pointer[address], &terminator, sizeof(terminator));
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std::memcpy(&ram_pointer[address], &terminator, sizeof(terminator));
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m_bus->InvalidateCodePages(address, word_count);
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m_bus->InvalidateCodePages(address, word_count);
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return;
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return m_bus->GetDMARAMTickCount(word_count);
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}
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}
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u32* dest_pointer = reinterpret_cast<u32*>(&m_bus->m_ram[address]);
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u32* dest_pointer = reinterpret_cast<u32*>(&m_bus->m_ram[address]);
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@ -429,4 +508,5 @@ void DMA::TransferDeviceToMemory(Channel channel, u32 address, u32 increment, u3
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}
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}
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m_bus->InvalidateCodePages(address, word_count);
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m_bus->InvalidateCodePages(address, word_count);
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return m_bus->GetDMARAMTickCount(word_count);
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}
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}
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@ -66,15 +66,19 @@ private:
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// is everything enabled for a channel to operate?
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// is everything enabled for a channel to operate?
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bool CanTransferChannel(Channel channel) const;
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bool CanTransferChannel(Channel channel) const;
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bool IsTransferHalted() const;
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void UpdateIRQ();
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void UpdateIRQ();
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void TransferChannel(Channel channel);
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// returns false if the DMA should now be halted
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bool TransferChannel(Channel channel);
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void HaltTransfer(TickCount duration);
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void UnhaltTransfer(TickCount ticks);
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// from device -> memory
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// from device -> memory
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void TransferDeviceToMemory(Channel channel, u32 address, u32 increment, u32 word_count);
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TickCount TransferDeviceToMemory(Channel channel, u32 address, u32 increment, u32 word_count);
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// from memory -> device
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// from memory -> device
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void TransferMemoryToDevice(Channel channel, u32 address, u32 increment, u32 word_count);
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TickCount TransferMemoryToDevice(Channel channel, u32 address, u32 increment, u32 word_count);
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System* m_system = nullptr;
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System* m_system = nullptr;
|
||||||
Bus* m_bus = nullptr;
|
Bus* m_bus = nullptr;
|
||||||
|
@ -84,7 +88,13 @@ private:
|
||||||
SPU* m_spu = nullptr;
|
SPU* m_spu = nullptr;
|
||||||
MDEC* m_mdec = nullptr;
|
MDEC* m_mdec = nullptr;
|
||||||
|
|
||||||
|
// configuration
|
||||||
|
TickCount m_max_slice_ticks = 1000;
|
||||||
|
TickCount m_halt_ticks = 100;
|
||||||
|
|
||||||
std::vector<u32> m_transfer_buffer;
|
std::vector<u32> m_transfer_buffer;
|
||||||
|
std::unique_ptr<TimingEvent> m_unhalt_event;
|
||||||
|
TickCount m_halt_ticks_remaining = 0;
|
||||||
|
|
||||||
struct ChannelState
|
struct ChannelState
|
||||||
{
|
{
|
||||||
|
|
|
@ -394,7 +394,7 @@ protected:
|
||||||
#if 0
|
#if 0
|
||||||
const u32 draw_ticks = static_cast<u32>((std::abs(x1 * (y2 - y3) + x2 * (y3 - y1) + x3 * (y1 - y2)) + 1u) / 2u);
|
const u32 draw_ticks = static_cast<u32>((std::abs(x1 * (y2 - y3) + x2 * (y3 - y1) + x3 * (y1 - y2)) + 1u) / 2u);
|
||||||
#else
|
#else
|
||||||
const u32 draw_ticks = ((width + 1) / 2) * height;
|
const u32 draw_ticks = ((width + 2) / 3) * height;
|
||||||
#endif
|
#endif
|
||||||
AddCommandTicks(draw_ticks);
|
AddCommandTicks(draw_ticks);
|
||||||
}
|
}
|
||||||
|
|
|
@ -2,7 +2,7 @@
|
||||||
#include "types.h"
|
#include "types.h"
|
||||||
|
|
||||||
static constexpr u32 SAVE_STATE_MAGIC = 0x43435544;
|
static constexpr u32 SAVE_STATE_MAGIC = 0x43435544;
|
||||||
static constexpr u32 SAVE_STATE_VERSION = 28;
|
static constexpr u32 SAVE_STATE_VERSION = 29;
|
||||||
|
|
||||||
#pragma pack(push, 4)
|
#pragma pack(push, 4)
|
||||||
struct SAVE_STATE_HEADER
|
struct SAVE_STATE_HEADER
|
||||||
|
|
|
@ -766,8 +766,10 @@ bool System::SetExpansionROM(const char* filename)
|
||||||
void System::StallCPU(TickCount ticks)
|
void System::StallCPU(TickCount ticks)
|
||||||
{
|
{
|
||||||
m_cpu->AddPendingTicks(ticks);
|
m_cpu->AddPendingTicks(ticks);
|
||||||
|
#if 0
|
||||||
if (m_cpu->GetPendingTicks() >= m_cpu->GetDowncount() && !m_running_events)
|
if (m_cpu->GetPendingTicks() >= m_cpu->GetDowncount() && !m_running_events)
|
||||||
RunEvents();
|
RunEvents();
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
Controller* System::GetController(u32 slot) const
|
Controller* System::GetController(u32 slot) const
|
||||||
|
|
Loading…
Reference in New Issue