GPU: Fix handling of GP1(09h)
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ffe90083d3
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8f624afb59
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@ -38,6 +38,7 @@ void GPU::UpdateSettings()
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void GPU::Reset()
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void GPU::Reset()
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{
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{
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SoftReset();
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SoftReset();
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m_set_texture_disable_mask = false;
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m_GPUREAD_latch = 0;
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m_GPUREAD_latch = 0;
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}
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}
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@ -96,6 +97,8 @@ bool GPU::DoState(StateWrapper& sw)
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sw.Do(&m_drawing_offset.y);
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sw.Do(&m_drawing_offset.y);
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sw.Do(&m_drawing_offset.x);
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sw.Do(&m_drawing_offset.x);
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sw.Do(&m_set_texture_disable_mask);
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sw.Do(&m_crtc_state.regs.display_address_start);
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sw.Do(&m_crtc_state.regs.display_address_start);
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sw.Do(&m_crtc_state.regs.horizontal_display_range);
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sw.Do(&m_crtc_state.regs.horizontal_display_range);
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sw.Do(&m_crtc_state.regs.vertical_display_range);
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sw.Do(&m_crtc_state.regs.vertical_display_range);
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@ -600,6 +603,13 @@ void GPU::WriteGP1(u32 value)
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}
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}
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break;
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break;
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case 0x09: // Allow texture disable
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{
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m_set_texture_disable_mask = ConvertToBoolUnchecked(param & 0x01);
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Log_DebugPrintf("Set texture disable mask <- %s", m_set_texture_disable_mask ? "allowed" : "ignored");
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}
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break;
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case 0x10:
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case 0x10:
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case 0x11:
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case 0x11:
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case 0x12:
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case 0x12:
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@ -725,22 +735,26 @@ void GPU::FlushRender() {}
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void GPU::SetDrawMode(u16 value)
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void GPU::SetDrawMode(u16 value)
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{
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{
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const DrawMode::Reg reg{static_cast<u16>(value & DrawMode::Reg::MASK)};
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DrawMode::Reg new_mode_reg{static_cast<u16>(value & DrawMode::Reg::MASK)};
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if (reg.bits == m_draw_mode.mode_reg.bits)
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if (!m_set_texture_disable_mask)
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new_mode_reg.texture_disable = false;
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if (new_mode_reg.bits == m_draw_mode.mode_reg.bits)
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return;
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return;
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if ((reg.bits & DrawMode::Reg::TEXTURE_PAGE_MASK) != (m_draw_mode.mode_reg.bits & DrawMode::Reg::TEXTURE_PAGE_MASK))
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if ((new_mode_reg.bits & DrawMode::Reg::TEXTURE_PAGE_MASK) !=
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(m_draw_mode.mode_reg.bits & DrawMode::Reg::TEXTURE_PAGE_MASK))
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{
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{
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m_draw_mode.texture_page_x = reg.GetTexturePageXBase();
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m_draw_mode.texture_page_x = new_mode_reg.GetTexturePageXBase();
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m_draw_mode.texture_page_y = reg.GetTexturePageYBase();
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m_draw_mode.texture_page_y = new_mode_reg.GetTexturePageYBase();
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m_draw_mode.texture_page_changed = true;
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m_draw_mode.texture_page_changed = true;
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}
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}
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m_draw_mode.mode_reg.bits = reg.bits;
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m_draw_mode.mode_reg.bits = new_mode_reg.bits;
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// Bits 0..10 are returned in the GPU status register.
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// Bits 0..10 are returned in the GPU status register.
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m_GPUSTAT.bits =
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m_GPUSTAT.bits =
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m_GPUSTAT.bits & ~(DrawMode::Reg::GPUSTAT_MASK) | (ZeroExtend32(reg.bits) & DrawMode::Reg::GPUSTAT_MASK);
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m_GPUSTAT.bits & ~(DrawMode::Reg::GPUSTAT_MASK) | (ZeroExtend32(new_mode_reg.bits) & DrawMode::Reg::GPUSTAT_MASK);
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m_GPUSTAT.texture_disable = m_draw_mode.mode_reg.texture_disable;
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m_GPUSTAT.texture_disable = m_draw_mode.mode_reg.texture_disable;
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}
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}
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@ -469,6 +469,7 @@ protected:
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s32 y;
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s32 y;
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} m_drawing_offset = {};
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} m_drawing_offset = {};
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bool m_set_texture_disable_mask = false;
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bool m_drawing_area_changed = false;
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bool m_drawing_area_changed = false;
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bool m_drawing_offset_changed = false;
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bool m_drawing_offset_changed = false;
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bool m_force_progressive_scan = false;
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bool m_force_progressive_scan = false;
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