GPU: Use start address in computation of drawing_even_line
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42ee55ae17
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@ -208,12 +208,7 @@ u32 GPU::ReadRegister(u32 offset)
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return ReadGPUREAD();
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case 0x04:
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{
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// Bit 31 of GPUSTAT is always clear during vblank.
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u32 bits = m_GPUSTAT.bits;
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bits &= ~(BoolToUInt32(m_crtc_state.in_vblank) << 31);
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return bits;
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}
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return m_GPUSTAT.bits;
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default:
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Log_ErrorPrintf("Unhandled register read: %02X", offset);
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@ -407,10 +402,7 @@ void GPU::Execute(TickCount ticks)
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if (m_GPUSTAT.vertical_interlace)
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{
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m_GPUSTAT.interlaced_field ^= true;
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m_crtc_state.current_scanline = BoolToUInt32(m_GPUSTAT.interlaced_field);
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if (m_GPUSTAT.vertical_resolution)
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m_GPUSTAT.drawing_even_line = m_GPUSTAT.interlaced_field;
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m_crtc_state.current_scanline = BoolToUInt32(!m_GPUSTAT.interlaced_field);
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}
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else
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{
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@ -439,8 +431,16 @@ void GPU::Execute(TickCount ticks)
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}
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// alternating even line bit in 240-line mode
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if (!m_GPUSTAT.In480iMode())
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m_GPUSTAT.drawing_even_line = ConvertToBoolUnchecked(m_crtc_state.current_scanline & u32(1));
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if (m_GPUSTAT.In480iMode())
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{
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m_GPUSTAT.drawing_even_line =
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ConvertToBoolUnchecked((m_crtc_state.regs.Y + BoolToUInt32(!m_GPUSTAT.interlaced_field)) & u32(1));
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}
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else
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{
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m_GPUSTAT.drawing_even_line =
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ConvertToBoolUnchecked(m_crtc_state.regs.Y + m_crtc_state.current_scanline & u32(1));
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}
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}
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const bool new_hblank = m_crtc_state.current_tick_in_scanline < m_crtc_state.horizontal_display_start ||
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