DMA: Refactoring, support split block transfers
This commit is contained in:
Connor McLaughlin
parent
2d9d999713
commit
88ec178380
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@ -2,6 +2,7 @@
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#include "YBaseLib/Log.h"
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#include "common/cd_image.h"
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#include "common/state_wrapper.h"
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#include "dma.h"
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#include "interrupt_controller.h"
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#include "system.h"
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Log_SetChannel(CDROM);
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@ -394,6 +395,8 @@ void CDROM::UpdateStatusRegister()
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m_status.RSLRRDY = !m_response_fifo.IsEmpty();
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m_status.DRQSTS = !m_data_fifo.IsEmpty();
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m_status.BUSYSTS = m_command_state == CommandState::WaitForExecute;
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m_dma->SetRequest(DMA::Channel::CDROM, m_status.DRQSTS);
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}
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u32 CDROM::GetAckDelayForCommand() const
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142
src/core/dma.cpp
142
src/core/dma.cpp
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@ -30,7 +30,7 @@ bool DMA::Initialize(System* system, Bus* bus, InterruptController* interrupt_co
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void DMA::Reset()
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{
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m_transfer_ticks = 0;
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m_transfer_pending = false;
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m_transfer_in_progress = false;
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m_state = {};
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m_DPCR.bits = 0x07654321;
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m_DICR.bits = 0;
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@ -99,6 +99,7 @@ void DMA::WriteRegister(u32 offset, u32 value)
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{
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Log_TracePrintf("DMA channel %u block control <- 0x%08X", channel_index, value);
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state.block_control.bits = value;
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Transfer();
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return;
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}
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@ -107,9 +108,7 @@ void DMA::WriteRegister(u32 offset, u32 value)
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state.channel_control.bits = (state.channel_control.bits & ~ChannelState::ChannelControl::WRITE_MASK) |
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(value & ChannelState::ChannelControl::WRITE_MASK);
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Log_TracePrintf("DMA channel %u channel control <- 0x%08X", channel_index, state.channel_control.bits);
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if (CanRunChannel(static_cast<Channel>(channel_index)))
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UpdateTransferPending();
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Transfer();
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return;
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}
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@ -125,7 +124,7 @@ void DMA::WriteRegister(u32 offset, u32 value)
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{
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Log_TracePrintf("DPCR <- 0x%08X", value);
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m_DPCR.bits = value;
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UpdateTransferPending();
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Transfer();
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return;
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}
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@ -153,65 +152,70 @@ void DMA::SetRequest(Channel channel, bool request)
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return;
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cs.request = request;
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UpdateTransferPending();
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if (request)
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Transfer();
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}
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void DMA::Execute(TickCount ticks)
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{
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if (!m_transfer_pending)
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return;
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m_transfer_ticks -= ticks;
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if (m_transfer_ticks <= 0)
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{
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m_transfer_pending = false;
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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const Channel channel = static_cast<Channel>(i);
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if (CanRunChannel(channel))
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{
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RunDMA(channel);
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m_transfer_pending |= CanRunChannel(channel);
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}
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}
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if (m_transfer_pending)
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{
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m_transfer_ticks += TRANSFER_TICKS;
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m_system->SetDowncount(m_transfer_ticks);
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}
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}
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else
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{
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m_system->SetDowncount(m_transfer_ticks);
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}
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}
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bool DMA::CanRunChannel(Channel channel) const
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bool DMA::CanTransferChannel(Channel channel) const
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{
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if (!m_DPCR.GetMasterEnable(channel))
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return false;
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const ChannelState& cs = m_state[static_cast<u32>(channel)];
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if (cs.channel_control.start_trigger)
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return true;
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if (!cs.channel_control.enable_busy)
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return false;
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return (cs.channel_control.enable_busy && cs.request);
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if (!cs.request && channel != Channel::OTC)
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return false;
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if (cs.channel_control.sync_mode == SyncMode::Manual && !cs.channel_control.start_trigger)
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return false;
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return true;
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}
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bool DMA::CanRunAnyChannels() const
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{
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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if (CanRunChannel(static_cast<Channel>(i)))
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if (CanTransferChannel(static_cast<Channel>(i)))
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return true;
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}
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return false;
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}
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void DMA::RunDMA(Channel channel)
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void DMA::Transfer()
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{
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if (m_transfer_in_progress)
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return;
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// prevent recursive calls
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m_transfer_in_progress = true;
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// keep going until all transfers are done. one channel can start others (e.g. MDEC)
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for (;;)
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{
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bool any_channels_active = false;
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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{
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const Channel channel = static_cast<Channel>(i);
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if (CanTransferChannel(channel))
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{
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TransferChannel(channel);
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any_channels_active = true;
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}
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}
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if (!any_channels_active)
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break;
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}
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m_transfer_in_progress = false;
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}
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void DMA::TransferChannel(Channel channel)
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{
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ChannelState& cs = m_state[static_cast<u32>(channel)];
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const bool copy_to_device = cs.channel_control.copy_to_device;
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@ -305,13 +309,19 @@ void DMA::RunDMA(Channel channel)
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case SyncMode::Request:
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{
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const u32 block_size = cs.block_control.request.GetBlockSize();
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const u32 block_count = cs.block_control.request.GetBlockCount();
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Log_DebugPrintf("DMA%u: Copying %u blocks of size %u %s 0x%08X", static_cast<u32>(channel), block_count,
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block_size, copy_to_device ? "from" : "to", current_address);
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Log_DebugPrintf("DMA%u: Copying %u blocks of size %u %s 0x%08X", static_cast<u32>(channel),
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cs.block_control.request.GetBlockCount(), cs.block_control.request.GetBlockSize(),
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copy_to_device ? "from" : "to", current_address);
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u32 blocks_remaining = cs.block_control.request.block_count;
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if (copy_to_device)
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{
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u32 words_remaining = block_size * block_count;
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do
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{
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blocks_remaining--;
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u32 words_remaining = cs.block_control.request.block_size;
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do
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{
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words_remaining--;
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@ -322,10 +332,15 @@ void DMA::RunDMA(Channel channel)
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current_address = (current_address + increment) & ADDRESS_MASK;
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} while (words_remaining > 0);
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} while (cs.request && blocks_remaining > 0);
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}
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else
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{
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u32 words_remaining = block_size * block_count;
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do
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{
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blocks_remaining--;
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u32 words_remaining = cs.block_control.request.block_size;
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do
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{
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words_remaining--;
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@ -335,7 +350,15 @@ void DMA::RunDMA(Channel channel)
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current_address = (current_address + increment) & ADDRESS_MASK;
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} while (words_remaining > 0);
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} while (cs.request && blocks_remaining > 0);
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}
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cs.base_address = current_address;
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cs.block_control.request.block_count = blocks_remaining;
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// finish transfer later if the request was cleared
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if (blocks_remaining > 0)
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return;
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}
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break;
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@ -412,22 +435,3 @@ void DMA::DMAWrite(Channel channel, u32 value, PhysicalMemoryAddress src_address
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break;
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}
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}
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void DMA::UpdateTransferPending()
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{
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if (CanRunAnyChannels())
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{
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if (m_transfer_pending)
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return;
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m_system->Synchronize();
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m_transfer_pending = true;
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m_transfer_ticks = TRANSFER_TICKS;
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m_system->SetDowncount(m_transfer_ticks);
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}
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else
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{
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m_transfer_pending = false;
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m_transfer_ticks = 0;
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}
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}
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@ -35,8 +35,8 @@ public:
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DMA();
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~DMA();
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bool Initialize(System* system, Bus* bus, InterruptController* interrupt_controller, GPU* gpu, CDROM* cdrom,
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SPU* spu, MDEC* mdec);
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bool Initialize(System* system, Bus* bus, InterruptController* interrupt_controller, GPU* gpu, CDROM* cdrom, SPU* spu,
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MDEC* mdec);
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void Reset();
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bool DoState(StateWrapper& sw);
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@ -45,8 +45,6 @@ public:
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void SetRequest(Channel channel, bool request);
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void Execute(TickCount ticks);
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private:
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static constexpr PhysicalMemoryAddress ADDRESS_MASK = UINT32_C(0x00FFFFFF);
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static constexpr u32 TRANSFER_TICKS = 10;
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@ -60,10 +58,11 @@ private:
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};
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// is everything enabled for a channel to operate?
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bool CanRunChannel(Channel channel) const;
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bool CanTransferChannel(Channel channel) const;
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bool CanRunAnyChannels() const;
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void RunDMA(Channel channel);
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void Transfer();
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void TransferChannel(Channel channel);
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// from device -> memory
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u32 DMARead(Channel channel, PhysicalMemoryAddress dst_address, u32 remaining_words);
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@ -71,8 +70,6 @@ private:
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// from memory -> device
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void DMAWrite(Channel channel, u32 value, PhysicalMemoryAddress src_address, u32 remaining_words);
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void UpdateTransferPending();
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System* m_system = nullptr;
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Bus* m_bus = nullptr;
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InterruptController* m_interrupt_controller = nullptr;
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@ -82,7 +79,7 @@ private:
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MDEC* m_mdec = nullptr;
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TickCount m_transfer_ticks = 0;
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bool m_transfer_pending = false;
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bool m_transfer_in_progress = false;
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struct ChannelState
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{
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@ -48,7 +48,6 @@ u32 MDEC::ReadRegister(u32 offset)
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switch (offset)
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{
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case 0:
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UpdateStatusRegister();
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return ReadDataRegister();
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case 4:
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@ -85,6 +84,7 @@ void MDEC::WriteRegister(u32 offset, u32 value)
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m_enable_dma_in = cr.enable_dma_in;
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m_enable_dma_out = cr.enable_dma_out;
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UpdateStatusRegister();
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UpdateDMARequest();
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return;
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}
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@ -114,6 +114,7 @@ void MDEC::SoftReset()
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m_enable_dma_out = false;
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m_data_in_fifo.Clear();
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m_data_out_fifo.Clear();
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UpdateStatusRegister();
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UpdateDMARequest();
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}
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@ -122,7 +123,7 @@ void MDEC::UpdateStatusRegister()
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m_status.data_out_fifo_empty = m_data_out_fifo.IsEmpty();
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m_status.data_in_fifo_full = m_data_in_fifo.IsFull();
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m_status.command_busy = m_command != Command::None;
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m_status.command_busy = false;
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m_status.parameter_words_remaining = Truncate16(m_remaining_words - 1);
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m_status.current_block = (m_current_block + 4) % NUM_BLOCKS;
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}
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@ -130,7 +131,7 @@ void MDEC::UpdateStatusRegister()
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void MDEC::UpdateDMARequest()
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{
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// we always want data in if it's enabled
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const bool data_in_request = m_enable_dma_in && !m_data_in_fifo.IsFull();
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const bool data_in_request = m_enable_dma_in && m_data_in_fifo.GetSpace() >= (32 * 2) && !m_data_out_fifo.IsFull();
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m_status.data_in_request = data_in_request;
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m_dma->SetRequest(DMA::Channel::MDECin, data_in_request);
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@ -142,15 +143,24 @@ void MDEC::UpdateDMARequest()
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u32 MDEC::ReadDataRegister()
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{
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if (m_data_out_fifo.IsEmpty())
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{
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Execute();
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if (m_data_out_fifo.IsEmpty())
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{
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Log_WarningPrintf("MDEC data out FIFO empty on read");
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return UINT32_C(0xFFFFFFFF);
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}
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}
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const u32 value = m_data_out_fifo.Pop();
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if (m_data_out_fifo.IsEmpty())
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{
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UpdateStatusRegister();
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UpdateDMARequest();
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}
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return value;
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}
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@ -197,28 +207,52 @@ void MDEC::WriteCommandRegister(u32 value)
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m_data_in_fifo.Push(Truncate16(value));
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m_data_in_fifo.Push(Truncate16(value >> 16));
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m_remaining_words--;
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UpdateDMARequest();
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}
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Execute();
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}
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void MDEC::Execute()
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{
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switch (m_command)
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{
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case Command::DecodeMacroblock:
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{
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if (!HandleDecodeMacroblockCommand())
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{
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UpdateStatusRegister();
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UpdateDMARequest();
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return;
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}
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}
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break;
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case Command::SetIqTab:
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{
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if (!HandleSetQuantTableCommand())
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{
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UpdateStatusRegister();
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UpdateDMARequest();
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return;
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}
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}
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break;
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case Command::SetScale:
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{
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if (!HandleSetScaleCommand())
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{
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UpdateStatusRegister();
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UpdateDMARequest();
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return;
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}
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}
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break;
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default:
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{
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UpdateStatusRegister();
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UpdateDMARequest();
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return;
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}
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break;
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@ -229,6 +263,7 @@ void MDEC::WriteCommandRegister(u32 value)
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m_current_block = 0;
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m_current_coefficient = 64;
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m_current_q_scale = 0;
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UpdateStatusRegister();
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UpdateDMARequest();
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}
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@ -242,7 +277,7 @@ bool MDEC::HandleDecodeMacroblockCommand()
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break;
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}
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return m_remaining_words == 0;
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return m_data_in_fifo.IsEmpty() && m_remaining_words == 0;
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}
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else
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{
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@ -252,12 +287,24 @@ bool MDEC::HandleDecodeMacroblockCommand()
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break;
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}
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return m_remaining_words == 0;
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return m_data_in_fifo.IsEmpty() && m_remaining_words == 0;
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}
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}
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bool MDEC::DecodeMonoMacroblock()
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{
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// sufficient space in output?
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if (m_status.data_output_depth == DataOutputDepth_4Bit)
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{
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if (m_data_out_fifo.GetSpace() < (64 / 8))
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return false;
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}
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else
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{
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if (m_data_out_fifo.GetSpace() < (64 / 4))
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return false;
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}
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if (!rl_decode_block(m_blocks[0].data(), m_iq_y.data()))
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return false;
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@ -310,7 +357,17 @@ bool MDEC::DecodeMonoMacroblock()
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bool MDEC::DecodeColoredMacroblock()
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{
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std::array<u32, 256> out_rgb;
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// sufficient space in output?
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if (m_status.data_output_depth == DataOutputDepth_24Bit)
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{
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if (m_data_out_fifo.GetSpace() < (256 - (256 / 4)))
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return false;
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}
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else
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{
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if (m_data_out_fifo.GetSpace() < (256 / 2))
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return false;
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}
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for (; m_current_block < NUM_BLOCKS; m_current_block++)
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{
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@ -322,7 +379,9 @@ bool MDEC::DecodeColoredMacroblock()
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// done decoding
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m_current_block = 0;
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Log_DebugPrintf("Decoded colored macroblock");
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std::array<u32, 256> out_rgb;
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yuv_to_rgb(0, 0, m_blocks[0], m_blocks[1], m_blocks[2], out_rgb);
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yuv_to_rgb(8, 0, m_blocks[0], m_blocks[1], m_blocks[3], out_rgb);
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yuv_to_rgb(0, 8, m_blocks[0], m_blocks[1], m_blocks[4], out_rgb);
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@ -612,8 +671,8 @@ void MDEC::DrawDebugWindow()
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if (ImGui::CollapsingHeader("Status", ImGuiTreeNodeFlags_DefaultOpen))
|
||||
{
|
||||
ImGui::Text("Data-Out FIFO Empty: %s", m_status.data_out_fifo_empty ? "Yes" : "No");
|
||||
ImGui::Text("Data-In FIFO Empty: %s", m_status.data_in_fifo_full ? "Yes" : "No");
|
||||
ImGui::Text("Command Busy FIFO Empty: %s", m_status.command_busy ? "Yes" : "No");
|
||||
ImGui::Text("Data-In FIFO Full: %s", m_status.data_in_fifo_full ? "Yes" : "No");
|
||||
ImGui::Text("Command Busy: %s", m_status.command_busy ? "Yes" : "No");
|
||||
ImGui::Text("Data-In Request: %s", m_status.data_in_request ? "Yes" : "No");
|
||||
ImGui::Text("Output Depth: %s", output_depths[static_cast<u8>(m_status.data_output_depth.GetValue())]);
|
||||
ImGui::Text("Output Signed: %s", m_status.data_output_signed ? "Yes" : "No");
|
||||
|
|
|
|||
|
|
@ -91,6 +91,7 @@ private:
|
|||
|
||||
u32 ReadDataRegister();
|
||||
void WriteCommandRegister(u32 value);
|
||||
void Execute();
|
||||
|
||||
bool HandleDecodeMacroblockCommand();
|
||||
bool HandleSetQuantTableCommand();
|
||||
|
|
@ -114,8 +115,8 @@ private:
|
|||
bool m_enable_dma_out = false;
|
||||
|
||||
// Even though the DMA is in words, we access the FIFO as halfwords.
|
||||
InlineFIFOQueue<u16, DATA_IN_FIFO_SIZE> m_data_in_fifo;
|
||||
InlineFIFOQueue<u32, DATA_OUT_FIFO_SIZE> m_data_out_fifo;
|
||||
InlineFIFOQueue<u16, DATA_IN_FIFO_SIZE / sizeof(u16)> m_data_in_fifo;
|
||||
InlineFIFOQueue<u32, DATA_OUT_FIFO_SIZE / sizeof(u32)> m_data_out_fifo;
|
||||
Command m_command = Command::None;
|
||||
u32 m_remaining_words = 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -288,7 +288,6 @@ void System::Synchronize()
|
|||
m_timers->Execute(pending_ticks);
|
||||
m_cdrom->Execute(pending_ticks);
|
||||
m_pad->Execute(pending_ticks);
|
||||
m_dma->Execute(pending_ticks);
|
||||
m_spu->Execute(pending_ticks);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -96,7 +96,7 @@ int main(int argc, char* argv[])
|
|||
#else
|
||||
g_pLog->SetConsoleOutputParams(true, nullptr, LOGLEVEL_DEBUG);
|
||||
// g_pLog->SetConsoleOutputParams(true, "GPU GPU_HW_OpenGL SPU Pad DigitalController", LOGLEVEL_DEBUG);
|
||||
g_pLog->SetConsoleOutputParams(true, "GPU GPU_HW_OpenGL Pad DigitalController InterruptController", LOGLEVEL_DEBUG);
|
||||
g_pLog->SetConsoleOutputParams(true, "Pad DigitalController InterruptController", LOGLEVEL_DEBUG);
|
||||
// g_pLog->SetFilterLevel(LOGLEVEL_TRACE);
|
||||
g_pLog->SetFilterLevel(LOGLEVEL_DEBUG);
|
||||
// g_pLog->SetFilterLevel(LOGLEVEL_DEV);
|
||||
|
|
|
|||
Loading…
Reference in New Issue