CPU: Fix namespacing in disassembler
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95a9edaa65
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8842a46a90
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@ -11,6 +11,7 @@
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#include <array>
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namespace CPU {
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namespace {
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enum Operand : u8
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{
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@ -31,6 +32,28 @@ struct TableEntry
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const char* format;
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};
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struct GTEInstructionTable
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{
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const char* name;
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bool sf;
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bool lm;
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bool mvmva;
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};
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} // namespace
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static void FormatInstruction(SmallStringBase* dest, const Instruction inst, u32 pc, const char* format);
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static void FormatComment(SmallStringBase* dest, const Instruction inst, u32 pc, Registers* regs, const char* format);
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template<typename T>
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static void FormatCopInstruction(SmallStringBase* dest, u32 pc, const Instruction inst,
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const std::pair<T, const char*>* table, size_t table_size, T table_key);
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template<typename T>
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static void FormatCopComment(SmallStringBase* dest, u32 pc, Registers* regs, const Instruction inst,
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const std::pair<T, const char*>* table, size_t table_size, T table_key);
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static void FormatGTEInstruction(SmallStringBase* dest, u32 pc, const Instruction inst);
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static const std::array<const char*, 64> s_base_table = {{
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"", // 0
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"UNKNOWN", // 1
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@ -180,15 +203,6 @@ static constexpr const std::array<const char*, 64> s_gte_register_names = {
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"trz", "llm_0", "llm_1", "llm_2", "llm_3", "llm_4", "rbk", "gbk", "bbk", "lcm_0", "lcm_1", "lcm_2", "lcm_3",
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"lcm_4", "rfc", "gfc", "bfc", "ofx", "ofy", "h", "dqa", "dqb", "zsf3", "zsf4", "flag"}};
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namespace {
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struct GTEInstructionTable
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{
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const char* name;
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bool sf;
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bool lm;
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bool mvmva;
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};
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} // namespace
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static constexpr const std::array<GTEInstructionTable, 64> s_gte_instructions = {{
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{"rtps", true, true, false}, // 0x00
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{"nclip", false, false, false}, // 0x01
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@ -256,7 +270,9 @@ static constexpr const std::array<GTEInstructionTable, 64> s_gte_instructions =
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{"ncct", true, true, false}, // 0x3F
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}};
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static void FormatInstruction(SmallStringBase* dest, const Instruction inst, u32 pc, const char* format)
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} // namespace CPU
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void CPU::FormatInstruction(SmallStringBase* dest, const Instruction inst, u32 pc, const char* format)
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{
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dest->clear();
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@ -352,7 +368,7 @@ static void FormatInstruction(SmallStringBase* dest, const Instruction inst, u32
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}
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}
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static void FormatComment(SmallStringBase* dest, const Instruction inst, u32 pc, Registers* regs, const char* format)
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void CPU::FormatComment(SmallStringBase* dest, const Instruction inst, u32 pc, Registers* regs, const char* format)
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{
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const char* str = format;
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while (*str != '\0')
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@ -431,8 +447,8 @@ static void FormatComment(SmallStringBase* dest, const Instruction inst, u32 pc,
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}
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template<typename T>
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static void FormatCopInstruction(SmallStringBase* dest, u32 pc, const Instruction inst,
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const std::pair<T, const char*>* table, size_t table_size, T table_key)
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void CPU::FormatCopInstruction(SmallStringBase* dest, u32 pc, const Instruction inst,
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const std::pair<T, const char*>* table, size_t table_size, T table_key)
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{
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for (size_t i = 0; i < table_size; i++)
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{
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@ -447,8 +463,8 @@ static void FormatCopInstruction(SmallStringBase* dest, u32 pc, const Instructio
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}
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template<typename T>
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static void FormatCopComment(SmallStringBase* dest, u32 pc, Registers* regs, const Instruction inst,
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const std::pair<T, const char*>* table, size_t table_size, T table_key)
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void CPU::FormatCopComment(SmallStringBase* dest, u32 pc, Registers* regs, const Instruction inst,
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const std::pair<T, const char*>* table, size_t table_size, T table_key)
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{
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for (size_t i = 0; i < table_size; i++)
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{
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@ -460,7 +476,7 @@ static void FormatCopComment(SmallStringBase* dest, u32 pc, Registers* regs, con
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}
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}
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static void FormatGTEInstruction(SmallStringBase* dest, u32 pc, const Instruction inst)
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void CPU::FormatGTEInstruction(SmallStringBase* dest, u32 pc, const Instruction inst)
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{
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const GTE::Instruction gi{inst.bits};
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const GTEInstructionTable& t = s_gte_instructions[gi.command];
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@ -479,7 +495,7 @@ static void FormatGTEInstruction(SmallStringBase* dest, u32 pc, const Instructio
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}
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}
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void DisassembleInstruction(SmallStringBase* dest, u32 pc, u32 bits)
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void CPU::DisassembleInstruction(SmallStringBase* dest, u32 pc, u32 bits)
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{
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const Instruction inst{bits};
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switch (inst.op)
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@ -544,7 +560,7 @@ void DisassembleInstruction(SmallStringBase* dest, u32 pc, u32 bits)
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}
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}
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void DisassembleInstructionComment(SmallStringBase* dest, u32 pc, u32 bits, Registers* regs)
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void CPU::DisassembleInstructionComment(SmallStringBase* dest, u32 pc, u32 bits, Registers* regs)
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{
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const Instruction inst{bits};
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switch (inst.op)
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@ -612,5 +628,3 @@ const char* CPU::GetGTERegisterName(u32 index)
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{
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return (index < s_gte_register_names.size()) ? s_gte_register_names[index] : "";
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}
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} // namespace CPU
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