CPU: Don't stall until GTE completion on write
Apparently this is what the real CPU does, and some very optimized code can run slower if we stall early. Obviously if you write to a register being read by the command, things are going to break.
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7d80a74dc3
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@ -1851,8 +1851,6 @@ restart_instruction:
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return;
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}
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StallUntilGTEComplete();
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if (inst.cop.IsCommonInstruction())
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{
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// TODO: Combine with cop0.
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@ -1860,6 +1858,8 @@ restart_instruction:
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{
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case CopCommonInstruction::cfcn:
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{
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StallUntilGTEComplete();
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const u32 value = GTE::ReadRegister(static_cast<u32>(inst.r.rd.GetValue()) + 32);
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WriteRegDelayed(inst.r.rt, value);
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@ -1880,6 +1880,8 @@ restart_instruction:
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case CopCommonInstruction::mfcn:
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{
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StallUntilGTEComplete();
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const u32 value = GTE::ReadRegister(static_cast<u32>(inst.r.rd.GetValue()));
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WriteRegDelayed(inst.r.rt, value);
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@ -1906,6 +1908,7 @@ restart_instruction:
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}
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else
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{
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StallUntilGTEComplete();
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GTE::ExecuteInstruction(inst.bits);
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}
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}
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@ -1925,7 +1928,6 @@ restart_instruction:
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if (!ReadMemoryWord(addr, &value))
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return;
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StallUntilGTEComplete();
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GTE::WriteRegister(ZeroExtend32(static_cast<u8>(inst.i.rt.GetValue())), value);
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if constexpr (pgxp_mode >= PGXPMode::Memory)
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@ -1301,8 +1301,8 @@ void CPU::Recompiler::Recompiler::CompileInstruction()
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{
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case CopCommonInstruction::mfcn: if (inst->r.rt != Reg::zero) { CompileTemplate(nullptr, &Recompiler::Compile_mfc2, nullptr, TF_GTE_STALL); } break;
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case CopCommonInstruction::cfcn: if (inst->r.rt != Reg::zero) { CompileTemplate(nullptr, &Recompiler::Compile_mfc2, nullptr, TF_GTE_STALL); } break;
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case CopCommonInstruction::mtcn: CompileTemplate(nullptr, &Recompiler::Compile_mtc2, PGXPFN(CPU_MTC2), TF_GTE_STALL | TF_READS_T | TF_PGXP_WITHOUT_CPU); break;
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case CopCommonInstruction::ctcn: CompileTemplate(nullptr, &Recompiler::Compile_mtc2, PGXPFN(CPU_MTC2), TF_GTE_STALL | TF_READS_T | TF_PGXP_WITHOUT_CPU); break;
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case CopCommonInstruction::mtcn: CompileTemplate(nullptr, &Recompiler::Compile_mtc2, PGXPFN(CPU_MTC2), TF_READS_T | TF_PGXP_WITHOUT_CPU); break;
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case CopCommonInstruction::ctcn: CompileTemplate(nullptr, &Recompiler::Compile_mtc2, PGXPFN(CPU_MTC2), TF_READS_T | TF_PGXP_WITHOUT_CPU); break;
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default: Compile_Fallback(); break;
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}
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}
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@ -1314,7 +1314,7 @@ void CPU::Recompiler::Recompiler::CompileInstruction()
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}
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break;
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case InstructionOp::lwc2: CompileLoadStoreTemplate(&Recompiler::Compile_lwc2, MemoryAccessSize::Word, false, false, TF_GTE_STALL | TF_READS_S | TF_LOAD_DELAY); break;
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case InstructionOp::lwc2: CompileLoadStoreTemplate(&Recompiler::Compile_lwc2, MemoryAccessSize::Word, false, false, TF_READS_S | TF_LOAD_DELAY); break;
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case InstructionOp::swc2: CompileLoadStoreTemplate(&Recompiler::Compile_swc2, MemoryAccessSize::Word, true, false, TF_GTE_STALL | TF_READS_S); SpecExec_swc2(); break;
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// swc0/lwc0/cop1/cop3 are essentially no-ops
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