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GPU: Tie idle bit to FIFO emptyness on VRAM write 

Fixes Tenga Seiha lockup on boot.
This commit is contained in:
Stenzek 2024-05-31 20:12:55 +10:00
parent 53600746c7
commit 73136d7dc4
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1 changed files with 2 additions and 8 deletions
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10
src/core/gpu.cpp
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@ -448,19 +448,13 @@ void GPU::UpdateGPUIdle()
switch (m_blitter_state)
{
case BlitterState::Idle:
case BlitterState::DrawingPolyLine:
m_GPUSTAT.gpu_idle = (m_pending_command_ticks <= 0 && m_fifo.IsEmpty());
break;
case BlitterState::WritingVRAM:
m_GPUSTAT.gpu_idle = false;
break;
case BlitterState::ReadingVRAM:
m_GPUSTAT.gpu_idle = false;
break;
case BlitterState::DrawingPolyLine:
m_GPUSTAT.gpu_idle = false;
m_GPUSTAT.gpu_idle = m_fifo.IsEmpty();
break;
default: