CPU/Recompiler: Implement b{gez,ltz}(al)?
This commit is contained in:
Connor McLaughlin
parent
167e2a3454
commit
641e68db95
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@ -60,8 +60,9 @@ To access the menus with the controller, press the right stick down and use the
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- Passes amidog's CPU and GTE tests, partial passing of CPX tests
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## Screenshots
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## Disclaimers
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@ -93,6 +93,7 @@ bool CodeGenerator::CompileInstruction(const CodeBlockInstruction& cbi)
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case InstructionOp::j:
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case InstructionOp::jal:
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case InstructionOp::b:
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case InstructionOp::beq:
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case InstructionOp::bne:
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case InstructionOp::bgtz:
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@ -1029,7 +1030,7 @@ bool CodeGenerator::Compile_Branch(const CodeBlockInstruction& cbi)
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OrValues(AndValues(m_register_cache.ReadGuestRegister(Reg::pc, false), Value::FromConstantU32(0xF0000000)),
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Value::FromConstantU32(cbi.instruction.j.target << 2));
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EmitBranch(Condition::Always, (cbi.instruction.op == InstructionOp::jal) ? Reg::ra : Reg::count,
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EmitBranch(Condition::Always, (cbi.instruction.op == InstructionOp::jal) ? Reg::ra : Reg::count, false,
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std::move(branch_target));
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}
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break;
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@ -1041,15 +1042,13 @@ bool CodeGenerator::Compile_Branch(const CodeBlockInstruction& cbi)
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// npc = rs, link to rt
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Value branch_target = m_register_cache.ReadGuestRegister(cbi.instruction.r.rs);
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EmitBranch(Condition::Always,
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(cbi.instruction.r.funct == InstructionFunct::jalr) ? cbi.instruction.r.rd : Reg::count,
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(cbi.instruction.r.funct == InstructionFunct::jalr) ? cbi.instruction.r.rd : Reg::count, false,
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std::move(branch_target));
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}
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break;
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case InstructionOp::beq:
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case InstructionOp::bne:
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case InstructionOp::bgtz:
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case InstructionOp::blez:
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{
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// npc = pc + (sext(imm) << 2)
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Value branch_target = AddValues(m_register_cache.ReadGuestRegister(Reg::pc, false),
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@ -1060,27 +1059,42 @@ bool CodeGenerator::Compile_Branch(const CodeBlockInstruction& cbi)
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Value rhs = m_register_cache.ReadGuestRegister(cbi.instruction.i.rt);
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EmitCmp(lhs.host_reg, rhs);
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Condition condition;
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switch (cbi.instruction.op)
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{
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case InstructionOp::beq:
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condition = Condition::Equal;
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break;
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case InstructionOp::bne:
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condition = Condition::NotEqual;
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break;
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case InstructionOp::bgtz:
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condition = Condition::GreaterThanZero;
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break;
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case InstructionOp::blez:
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condition = Condition::LessOrEqualToZero;
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break;
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default:
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condition = Condition::Always;
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break;
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const Condition condition = (cbi.instruction.op == InstructionOp::beq) ? Condition::Equal : Condition::NotEqual;
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EmitBranch(condition, Reg::count, false, std::move(branch_target));
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}
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break;
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EmitBranch(condition, Reg::count, std::move(branch_target));
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case InstructionOp::bgtz:
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case InstructionOp::blez:
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{
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// npc = pc + (sext(imm) << 2)
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Value branch_target = AddValues(m_register_cache.ReadGuestRegister(Reg::pc, false),
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Value::FromConstantU32(cbi.instruction.i.imm_sext32() << 2));
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// branch <- rs op 0
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Value lhs = m_register_cache.ReadGuestRegister(cbi.instruction.i.rs, true, true);
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EmitCmp(lhs.host_reg, Value::FromConstantU32(0));
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const Condition condition =
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(cbi.instruction.op == InstructionOp::bgtz) ? Condition::Greater : Condition::LessOrEqual;
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EmitBranch(condition, Reg::count, false, std::move(branch_target));
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}
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break;
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case InstructionOp::b:
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{
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// npc = pc + (sext(imm) << 2)
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Value branch_target = AddValues(m_register_cache.ReadGuestRegister(Reg::pc, false),
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Value::FromConstantU32(cbi.instruction.i.imm_sext32() << 2));
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const u8 rt = static_cast<u8>(cbi.instruction.i.rt.GetValue());
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const bool bgez = ConvertToBoolUnchecked(rt & u8(1));
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const Condition condition = bgez ? Condition::PositiveOrZero : Condition::Negative;
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const bool link = (rt & u8(0x1E)) == u8(0x10);
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Value lhs = m_register_cache.ReadGuestRegister(cbi.instruction.i.rs, true, true);
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EmitTest(lhs.host_reg, lhs);
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EmitBranch(condition, link ? Reg::ra : Reg::count, link, std::move(branch_target));
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}
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break;
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@ -74,7 +74,7 @@ public:
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void EmitStoreGuestMemory(const Value& address, const Value& value);
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// Branching, generates two paths.
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void EmitBranch(Condition condition, Reg lr_reg, Value&& branch_target);
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void EmitBranch(Condition condition, Reg lr_reg, bool always_link, Value&& branch_target);
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u32 PrepareStackForCall();
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void RestoreStackAfterCall(u32 adjust_size);
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@ -1621,35 +1621,58 @@ static void EmitConditionalJump(Condition condition, bool invert, Xbyak::CodeGen
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invert ? emit->jno(label) : emit->jo(label);
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break;
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case Condition::GreaterThanZero:
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case Condition::Greater:
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invert ? emit->jng(label) : emit->jg(label);
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break;
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case Condition::LessOrEqualToZero:
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case Condition::GreaterEqual:
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invert ? emit->jnge(label) : emit->jge(label);
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break;
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case Condition::Less:
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invert ? emit->jnl(label) : emit->jl(label);
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break;
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case Condition::LessOrEqual:
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invert ? emit->jnle(label) : emit->jle(label);
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break;
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case Condition::Negative:
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invert ? emit->jns(label) : emit->js(label);
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break;
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case Condition::PositiveOrZero:
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invert ? emit->js(label) : emit->jns(label);
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break;
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default:
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UnreachableCode();
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break;
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}
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}
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void CodeGenerator::EmitBranch(Condition condition, Reg lr_reg, Value&& branch_target)
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void CodeGenerator::EmitBranch(Condition condition, Reg lr_reg, bool always_link, Value&& branch_target)
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{
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Xbyak::Label skip_branch;
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// we have to always read the old PC.. when we can push/pop the register cache state this won't be needed
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Value old_npc;
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if (lr_reg != Reg::count)
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{
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old_npc = m_register_cache.ReadGuestRegister(Reg::npc, false, true);
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if (always_link)
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{
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// can't cache because we have two branches
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m_register_cache.WriteGuestRegister(lr_reg, std::move(old_npc));
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m_register_cache.FlushGuestRegister(lr_reg, true, true);
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}
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}
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// condition is inverted because we want the case for skipping it
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Xbyak::Label skip_branch;
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if (condition != Condition::Always)
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EmitConditionalJump(condition, true, m_emit, skip_branch);
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// save the old PC if we want to
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if (lr_reg != Reg::count)
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if (lr_reg != Reg::count && !always_link)
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{
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// can't cache because we have two branches
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m_register_cache.WriteGuestRegister(lr_reg, std::move(old_npc));
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@ -30,8 +30,12 @@ enum class Condition: u8
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NotEqual,
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Equal,
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Overflow,
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GreaterThanZero,
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LessOrEqualToZero,
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Greater,
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GreaterEqual,
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LessOrEqual,
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Less,
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Negative,
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PositiveOrZero,
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NotZero = NotEqual,
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Zero = Equal
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