From 63ec83d18a4c50c0210884baab88738e6abcfa51 Mon Sep 17 00:00:00 2001
From: Stenzek <stenzek@gmail.com>
Date: Tue, 6 Aug 2024 21:56:24 +1000
Subject: [PATCH] SPU: Ensure all samples are generated prior to DMA write

---
 src/core/spu.cpp | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/core/spu.cpp b/src/core/spu.cpp
index d5c90a62f..018301183 100644
--- a/src/core/spu.cpp
+++ b/src/core/spu.cpp
@@ -341,6 +341,7 @@ static s16 ReverbRead(u32 address, s32 offset = 0);
 static void ReverbWrite(u32 address, s16 data);
 static void ProcessReverb(s16 left_in, s16 right_in, s32* left_out, s32* right_out);
 
+static void InternalGeneratePendingSamples();
 static void Execute(void* param, TickCount ticks, TickCount ticks_late);
 static void UpdateEventInterval();
 
@@ -1268,6 +1269,7 @@ void SPU::ExecuteTransfer(void* param, TickCount ticks, TickCount ticks_late)
 {
   const RAMTransferMode mode = s_state.SPUCNT.ram_transfer_mode;
   DebugAssert(mode != RAMTransferMode::Stopped);
+  InternalGeneratePendingSamples();
 
   if (mode == RAMTransferMode::DMARead)
   {
@@ -1483,6 +1485,11 @@ void SPU::GeneratePendingSamples()
   if (s_state.transfer_event.IsActive())
     s_state.transfer_event.InvokeEarly();
 
+  InternalGeneratePendingSamples();
+}
+
+void SPU::InternalGeneratePendingSamples()
+{
   const TickCount ticks_pending = s_state.tick_event.GetTicksSinceLastExecution();
   TickCount frames_to_execute;
   if (g_settings.cpu_overclock_active)