From 5b600789d69f6e9bdfa3a60b464c0cdafc33e7a3 Mon Sep 17 00:00:00 2001
From: Stenzek <stenzek@gmail.com>
Date: Sun, 10 Nov 2024 14:02:03 +1000
Subject: [PATCH] GPU: Page align VRAM storage on Apple Silicon

---
 src/core/gpu.cpp | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/core/gpu.cpp b/src/core/gpu.cpp
index 50df1b22c..9ec22af4a 100644
--- a/src/core/gpu.cpp
+++ b/src/core/gpu.cpp
@@ -45,8 +45,13 @@ LOG_CHANNEL(GPU);
 std::unique_ptr<GPU> g_gpu;
 
 // aligning VRAM to 4K is fine, since the ARM64 instructions compute 4K page aligned addresses
-// TOOD: REMOVE ME
-alignas(4096) u16 g_vram[VRAM_SIZE / sizeof(u16)];
+// or it would be, except we want to import the memory for readbacks on metal..
+#ifdef DYNAMIC_HOST_PAGE_SIZE
+#define VRAM_STORAGE_ALIGNMENT MIN_HOST_PAGE_SIZE
+#else
+#define VRAM_STORAGE_ALIGNMENT HOST_PAGE_SIZE
+#endif
+alignas(VRAM_STORAGE_ALIGNMENT) u16 g_vram[VRAM_SIZE / sizeof(u16)];
 u16 g_gpu_clut[GPU_CLUT_SIZE];
 
 const GPU::GP0CommandHandlerTable GPU::s_GP0_command_handler_table = GPU::GenerateGP0CommandHandlerTable();