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Misc: RISC-V build fixes

This commit is contained in:
Stenzek 2024-07-19 22:23:13 +10:00
parent 0815aedca2
commit 56dd9878e1
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2 changed files with 6 additions and 6 deletions
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2
src/common/gsvector_nosimd.h
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@ -115,7 +115,7 @@ public:
{
}
ALWAYS_INLINE explicit GSVector2i(const GSVector2i& v) { std::memcpy(I32, v.I32, sizeof(I32)); }
ALWAYS_INLINE GSVector2i(const GSVector2i& v) { std::memcpy(I32, v.I32, sizeof(I32)); }
// MSVC has bad codegen for the constexpr version when applied to non-constexpr things (https://godbolt.org/z/h8qbn7),
// so leave the non-constexpr version default

10
src/core/spu.cpp
View File

@ -73,7 +73,7 @@ enum class RAMTransferMode : u8
DMARead = 3
};
union SPUCNT
union SPUCNTRegister
{
u16 bits;
@ -91,7 +91,7 @@ union SPUCNT
BitField<u16, u8, 0, 6> mode;
};
union SPUSTAT
union SPUSTATRegister
{
u16 bits;
@ -362,8 +362,8 @@ struct SPUState
TickCount cpu_ticks_per_spu_tick = 0;
TickCount cpu_tick_divider = 0;
SPUCNT SPUCNT = {};
SPUSTAT SPUSTAT = {};
SPUCNTRegister SPUCNT = {};
SPUSTATRegister SPUSTAT = {};
TransferControl transfer_control = {};
u16 transfer_address_reg = 0;
@ -911,7 +911,7 @@ void SPU::WriteRegister(u32 offset, u16 value)
DEBUG_LOG("SPU control register <- 0x{:04X}", value);
GeneratePendingSamples();
const SPUCNT new_value{value};
const SPUCNTRegister new_value{value};
if (new_value.ram_transfer_mode != s_state.SPUCNT.ram_transfer_mode &&
new_value.ram_transfer_mode == RAMTransferMode::Stopped)
{